summaryrefslogtreecommitdiff
path: root/include
diff options
context:
space:
mode:
authorAlbert ARIBAUD <albert.u.boot@aribaud.net>2014-05-20 10:05:42 +0200
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2014-05-20 10:05:42 +0200
commit05d134b084590684bcf4d832c0035952727b7cd9 (patch)
tree8f5d5fd811634fa621792cad7ca361251c06cd88 /include
parent6130c14605de760bdcaef36b8a0d34eac2a955f0 (diff)
parentd7782d06534fe4fa47a49fa7c106de5ba85a9687 (diff)
downloadu-boot-imx-05d134b084590684bcf4d832c0035952727b7cd9.zip
u-boot-imx-05d134b084590684bcf4d832c0035952727b7cd9.tar.gz
u-boot-imx-05d134b084590684bcf4d832c0035952727b7cd9.tar.bz2
Merge remote-tracking branch 'u-boot/master'
Conflicts: boards.cfg Conflicts were trivial once u-boot-arm/master boards.cfg was reformatted (commit 6130c146) to match u-boot/master's own reformatting (commit 1b37fa83).
Diffstat (limited to 'include')
-rw-r--r--include/asm-generic/u-boot.h1
-rw-r--r--include/common.h7
-rw-r--r--include/config_fallbacks.h4
-rw-r--r--include/configs/B4860QDS.h27
-rw-r--r--include/configs/BSC9132QDS.h2
-rw-r--r--include/configs/MPC8536DS.h2
-rw-r--r--include/configs/MPC8572DS.h5
-rw-r--r--include/configs/MPC8641HPCN.h3
-rw-r--r--include/configs/P1_P2_RDB.h265
-rw-r--r--include/configs/P2041RDB.h13
-rw-r--r--include/configs/T1040QDS.h3
-rw-r--r--include/configs/T104xRDB.h3
-rw-r--r--include/configs/T208xQDS.h13
-rw-r--r--include/configs/T208xRDB.h15
-rw-r--r--include/configs/T4240EMU.h3
-rw-r--r--include/configs/T4240QDS.h13
-rw-r--r--include/configs/T4240RDB.h756
-rw-r--r--include/configs/bct-brettl2.h1
-rw-r--r--include/configs/bf518f-ezbrd.h2
-rw-r--r--include/configs/bf526-ezbrd.h2
-rw-r--r--include/configs/bf527-ezkit.h2
-rw-r--r--include/configs/bf537-minotaur.h1
-rw-r--r--include/configs/bf537-pnav.h2
-rw-r--r--include/configs/bf537-srv1.h2
-rw-r--r--include/configs/bf537-stamp.h2
-rw-r--r--include/configs/cm-bf527.h2
-rw-r--r--include/configs/cm-bf537e.h2
-rw-r--r--include/configs/cm-bf537u.h2
-rw-r--r--include/configs/corenet_ds.h16
-rw-r--r--include/configs/dnp5370.h2
-rw-r--r--include/configs/ids8313.h1
-rw-r--r--include/configs/ip04.h1
-rw-r--r--include/configs/km/kmp204x-common.h17
-rw-r--r--include/configs/p1_p2_rdb_pc.h7
-rw-r--r--include/configs/qemu-ppce500.h1
-rw-r--r--include/configs/sama5d3_xplained.h1
-rw-r--r--include/configs/sandbox.h16
-rw-r--r--include/configs/t4qds.h2
-rw-r--r--include/configs/tcm-bf518.h2
-rw-r--r--include/configs/tcm-bf537.h2
-rw-r--r--include/ext4fs.h1
-rw-r--r--include/fat.h7
-rw-r--r--include/net.h36
-rw-r--r--include/ns16550.h1
-rw-r--r--include/spartan2.h72
-rw-r--r--include/spartan3.h84
-rw-r--r--include/usb/ehci-fsl.h2
-rw-r--r--include/virtex2.h66
-rw-r--r--include/xilinx.h65
-rw-r--r--include/zynqpl.h16
50 files changed, 1243 insertions, 330 deletions
diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h
index c18e4ca..62cb1ea 100644
--- a/include/asm-generic/u-boot.h
+++ b/include/asm-generic/u-boot.h
@@ -66,7 +66,6 @@ typedef struct bd_info {
unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */
unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */
#endif
- unsigned int bi_baudrate; /* Console Baudrate */
#if defined(CONFIG_405) || \
defined(CONFIG_405GP) || \
defined(CONFIG_405EP) || \
diff --git a/include/common.h b/include/common.h
index 5fb0bb2..13e5dc7 100644
--- a/include/common.h
+++ b/include/common.h
@@ -729,9 +729,12 @@ void get_sys_info ( sys_info_t * );
#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260)
void cpu_init_f (volatile immap_t *immr);
#endif
-#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) ||defined(CONFIG_MPC86xx)
+#if defined(CONFIG_4xx) || defined(CONFIG_MCF52x2) || defined(CONFIG_MPC86xx)
void cpu_init_f (void);
#endif
+#ifdef CONFIG_MPC85xx
+ulong cpu_init_f(void);
+#endif
int cpu_init_r (void);
#if defined(CONFIG_MPC8260)
@@ -820,12 +823,10 @@ char * strmhz(char *buf, unsigned long hz);
#include <u-boot/crc.h>
/* lib/rand.c */
-#if defined(CONFIG_LIB_RAND) || defined(CONFIG_LIB_HW_RAND)
#define RAND_MAX -1U
void srand(unsigned int seed);
unsigned int rand(void);
unsigned int rand_r(unsigned int *seedp);
-#endif
/* common/console.c */
int console_init_f(void); /* Before relocation; uses the serial stuff */
diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h
index e6fb47b..b304a41 100644
--- a/include/config_fallbacks.h
+++ b/include/config_fallbacks.h
@@ -71,6 +71,10 @@
#define CONFIG_LIB_RAND
#endif
+#if defined(CONFIG_API) && defined(CONFIG_LCD)
+#define CONFIG_CMD_BMP
+#endif
+
#ifndef CONFIG_SYS_PROMPT
#define CONFIG_SYS_PROMPT "=> "
#endif
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index df371b7..1af9ba6 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -7,6 +7,9 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
/*
* B4860 QDS board configuration file
*/
@@ -115,6 +118,17 @@
#define IDT_SERDES1_ADDRESS 0x6E
#define IDT_SERDES2_ADDRESS 0x6C
+/* Voltage monitor on channel 2*/
+#define I2C_MUX_CH_VOL_MONITOR 0xa
+#define I2C_VOL_MONITOR_ADDR 0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+
+#define CONFIG_ZM7300
+#define I2C_MUX_CH_DPM 0xa
+#define I2C_DPM_ADDR 0x28
+
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_SYS_NO_FLASH
@@ -547,15 +561,15 @@ unsigned long get_board_ddr_clk(void);
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
@@ -824,8 +838,7 @@ unsigned long get_board_ddr_clk(void);
"ramdiskfile=b4860qds/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=b4860qds/b4860qds.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
/* For emulation this causes u-boot to jump to the start of the proof point
app code automatically */
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index e76a04b..7bb5d33 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -360,7 +360,7 @@ combinations. this should be removed later
#endif
/* Set up IFC registers for boot location NOR/NAND */
-#if defined(CONFIG_NAND)
+#if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index f15e162..72f5fde 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -11,6 +11,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#include "../board/freescale/common/ics307_clk.h"
#ifdef CONFIG_36BIT
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 7b63945..48ae9d4 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -11,6 +11,9 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
#include "../board/freescale/common/ics307_clk.h"
#ifdef CONFIG_36BIT
@@ -30,7 +33,7 @@
#endif
#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 7443ace..a0d7d52 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -16,6 +16,9 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
/* High Level Configuration Options */
#define CONFIG_MPC8641 1 /* MPC8641 specific */
#define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index 0f04067..110ba5f 100644
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -20,39 +20,119 @@
#ifdef CONFIG_P1011RDB
#define CONFIG_P1011
+#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
#ifdef CONFIG_P1020RDB
#define CONFIG_P1020
+#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
#ifdef CONFIG_P2010RDB
#define CONFIG_P2010
+#define CONFIG_SYS_L2_SIZE (512 << 10)
#endif
#ifdef CONFIG_P2020RDB
#define CONFIG_P2020
-#endif
-
-#ifdef CONFIG_NAND
-#define CONFIG_NAND_U_BOOT 1
-#define CONFIG_RAMBOOT_NAND 1
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
-#else
-#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
-#define CONFIG_SYS_TEXT_BASE 0xf8f82000
-#endif /* CONFIG_NAND_SPL */
+#define CONFIG_SYS_L2_SIZE (512 << 10)
#endif
#ifdef CONFIG_SDCARD
-#define CONFIG_RAMBOOT_SDCARD 1
-#define CONFIG_SYS_TEXT_BASE 0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#define CONFIG_SPL_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_SPL_MAX_SIZE (128 * 1024)
+#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS (129 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_MMC_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
#endif
#ifdef CONFIG_SPIFLASH
-#define CONFIG_RAMBOOT_SPIFLASH 1
-#define CONFIG_SYS_TEXT_BASE 0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#define CONFIG_SPL_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_SPL_MAX_SIZE (128 * 1024)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_SPI_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
+#endif
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_TPL
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_NAND_BOOT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SPL_MAX_SIZE (128 << 10)
+#define CONFIG_SPL_TEXT_BASE 0xf8f81000
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_TEXT_BASE 0xff800000
+#define CONFIG_SPL_MAX_SIZE 4096
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
+#endif /* not CONFIG_TPL_BUILD */
+
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_TPL_PAD_TO 0x20000
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
#endif
#ifndef CONFIG_SYS_TEXT_BASE
@@ -64,8 +144,12 @@
#endif
#ifndef CONFIG_SYS_MONITOR_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
+#endif
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
@@ -120,22 +204,45 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_MEMTEST_END 0x1fffffff
#define CONFIG_PANIC_HANG /* do not reset board on panic */
- /*
- * Config the L2 Cache as L2 SRAM
- */
+/*
+ * Config the L2 Cache as L2 SRAM
+*/
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
+#if defined(CONFIG_P2020RDB)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
+#else
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
+#endif
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
#else
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
+#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif /* CONFIG_TPL_BUILD */
+#endif
#endif
-#define CONFIG_SYS_L2_SIZE (512 << 10)
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-
-#define CONFIG_SYS_CCSRBAR 0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-#if defined(CONFIG_NAND_SPL)
+#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif
@@ -146,7 +253,15 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR size on P1_P2 RDBs */
+#if defined(CONFIG_P1011RDB) || defined(CONFIG_P1020RDB)
+/*
+ * P1020 and it's derivatives support max 32bit DDR width
+ * So Reduce available DDR size
+*/
+#define CONFIG_SYS_SDRAM_SIZE 512
+#else
+#define CONFIG_SYS_SDRAM_SIZE 1024
+#endif
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
@@ -201,14 +316,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
- defined(CONFIG_RAMBOOT_SPIFLASH)
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
@@ -241,21 +348,12 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
-#ifndef CONFIG_NAND_SPL
-#define CONFIG_SYS_NAND_BASE 0xffa00000
+#define CONFIG_SYS_NAND_BASE 0xff800000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
+#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
#else
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
#endif
-#else
-#define CONFIG_SYS_NAND_BASE 0xfff00000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-#endif
-#endif
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
@@ -264,15 +362,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
-/* NAND boot: 4K NAND loader config */
-#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
-#define CONFIG_SYS_NAND_U_BOOT_START (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
-
/* NAND flash config */
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
@@ -288,7 +377,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
| OR_FCM_TRLX \
| OR_FCM_EHTR)
-#ifdef CONFIG_RAMBOOT_NAND
+#ifdef CONFIG_NAND
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
@@ -323,7 +412,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#ifdef CONFIG_NAND_SPL
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif
@@ -490,33 +579,45 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
/*
* Environment
*/
-#if defined(CONFIG_SYS_RAMBOOT)
-#if defined(CONFIG_RAMBOOT_NAND)
- #define CONFIG_ENV_IS_IN_NAND 1
- #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
- #define CONFIG_ENV_OFFSET ((768*1024)+CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_RAMBOOT_SDCARD)
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 10000000
+#define CONFIG_ENV_SPI_MODE 0
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#elif defined(CONFIG_SDCARD)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_FSL_FIXED_MMC_LOCATION
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#elif defined(CONFIG_RAMBOOT_SPIFLASH)
- #define CONFIG_ENV_IS_IN_SPI_FLASH
- #define CONFIG_ENV_SPI_BUS 0
- #define CONFIG_ENV_SPI_CS 0
- #define CONFIG_ENV_SPI_MAX_HZ 10000000
- #define CONFIG_ENV_SPI_MODE 0
- #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
- #define CONFIG_ENV_SECT_SIZE 0x10000
- #define CONFIG_ENV_SIZE 0x2000
-#endif
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_OFFSET (512 * 0x800)
+#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
#else
- #define CONFIG_ENV_IS_IN_FLASH 1
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
- #define CONFIG_ENV_SIZE 0x2000
- #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#endif
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET (1024 * 1024)
+#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
+#elif defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE 0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
+
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 54e6493..16f7525 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -381,15 +381,15 @@ unsigned long get_board_sys_clk(unsigned long dummy);
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
@@ -713,8 +713,7 @@ unsigned long get_board_sys_clk(unsigned long dummy);
"ramdiskfile=p2041rdb/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=p2041rdb/p2041rdb.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
#define CONFIG_HDBOOT \
"setenv bootargs root=/dev/$bdev rw " \
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index 522653b..2215ac8 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -767,8 +767,7 @@ unsigned long get_board_ddr_clk(void);
"ramdiskfile=t1040qds/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=t1040qds/t1040qds.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
#define CONFIG_LINUX \
"setenv bootargs root=/dev/ram rw " \
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 81b4f31..e564cb7 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -779,8 +779,7 @@
"ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
"fdtaddr=c00000\0" \
"fdtfile=" __stringify(FDTFILE) "\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
#define CONFIG_LINUX \
"setenv bootargs root=/dev/ram rw " \
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 8bf0843..8dd2e49 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -505,15 +505,15 @@ unsigned long get_board_ddr_clk(void);
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
@@ -837,8 +837,7 @@ unsigned long get_board_ddr_clk(void);
"ramdiskfile=t2080qds/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=t2080qds/t2080qds.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
/*
* For emulation this causes u-boot to jump to the start of the
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 73d82ed..3a1c49c 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -461,15 +461,15 @@ unsigned long get_board_ddr_clk(void);
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
@@ -721,6 +721,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
#define CONFIG_CMD_MII
#define CONFIG_CMD_I2C
#define CONFIG_CMD_PING
@@ -750,7 +751,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/
/*
* For booting Linux, the board info and command line data
@@ -797,8 +797,7 @@ unsigned long get_board_ddr_clk(void);
"ramdiskfile=t2080rdb/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=t2080rdb/t2080rdb.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
/*
* For emulation this causes u-boot to jump to the start of the
diff --git a/include/configs/T4240EMU.h b/include/configs/T4240EMU.h
index ad5a9a6..53c69b0 100644
--- a/include/configs/T4240EMU.h
+++ b/include/configs/T4240EMU.h
@@ -128,8 +128,7 @@
"ramdiskfile=t4240emu/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=t4240emu/t4240emu.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
/*
* For emulation this causes u-boot to jump to the start of the proof point
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index e4eb30f..a770dd0 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -375,15 +375,15 @@ unsigned long get_board_ddr_clk(void);
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
@@ -572,8 +572,7 @@ unsigned long get_board_ddr_clk(void);
"ramdiskfile=t4240qds/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=t4240qds/t4240qds.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
#define CONFIG_HVBOOT \
"setenv bootargs config-addr=0x60000000; " \
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
new file mode 100644
index 0000000..183255d
--- /dev/null
+++ b/include/configs/T4240RDB.h
@@ -0,0 +1,756 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * T4240 RDB board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_T4240RDB
+#define CONFIG_PHYS_64BIT
+
+#define CONFIG_FSL_SATA_V2
+#define CONFIG_PCIE4
+
+#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg
+#endif
+
+#define CONFIG_DDR_ECC
+
+#define CONFIG_CMD_REGINFO
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500 /* BOOKE e500 family */
+#define CONFIG_E500MC /* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
+#define CONFIG_MP /* support multiple processors */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
+#endif
+
+#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_IFC /* Enable IFC Support */
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#define CONFIG_PCIE1 /* PCIE controler 1 */
+#define CONFIG_PCIE2 /* PCIE controler 2 */
+#define CONFIG_PCIE3 /* PCIE controler 3 */
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BTB /* toggle branch predition */
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+#endif
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
+
+#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+
+/*
+ * Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
+
+#define CONFIG_SYS_DCSRBAR 0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 4
+#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_FSL_DDR3
+
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE 0xe0000000
+#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 4, Base address 203000 */
+#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
+#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
+#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_E1000
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif /* CONFIG_PCI */
+
+/* SATA */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE 2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_ETHPRIME "FM1@DTSEC1"
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH "/opt/nfsroot"
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 1000000
+
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_HVBOOT \
+ "setenv bootargs config-addr=0x60000000; " \
+ "bootm 0x01000000 - 0x00f00000"
+
+#ifdef CONFIG_SYS_NO_FLASH
+#ifndef CONFIG_RAMBOOT_PBL
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+#else
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 10000000
+#define CONFIG_ENV_SPI_MODE 0
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET (512 * 1658)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE 0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_SYS_CLK_FREQ 66666666
+#define CONFIG_DDR_CLK_FREQ 133333333
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define SPD_EEPROM_ADDRESS1 0x52
+#define SPD_EEPROM_ADDRESS2 0x54
+#define SPD_EEPROM_ADDRESS3 0x56
+#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
+#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
+#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+ + 0x8000000) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
+#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
+
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
+ FTIM0_NOR_TEADC(0x5) | \
+ FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
+ FTIM1_NOR_TRAD_NOR(0x1A) |\
+ FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
+ FTIM2_NOR_TCH(0x4) | \
+ FTIM2_NOR_TWPH(0x0E) | \
+ FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3 0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
+ + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_MAX_ECCPOS 256
+#define CONFIG_SYS_NAND_MAX_OOBFREE 2
+#define CONFIG_SYS_NAND_BASE 0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+ | CSPR_MSEL_NAND /* MSEL = NAND */ \
+ | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+ | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
+ | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
+ | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
+ | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+ FTIM0_NAND_TWP(0x18) | \
+ FTIM0_NAND_TWCHT(0x07) | \
+ FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+ FTIM1_NAND_TWBE(0x39) | \
+ FTIM1_NAND_TRR(0x0e) | \
+ FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+ FTIM2_NAND_TREH(0x0a) | \
+ FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3 0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW 11
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#endif
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+
+/* I2C */
+#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
+#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
+#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
+#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
+
+#define I2C_MUX_CH_DEFAULT 0x8
+#define I2C_MUX_CH_VOL_MONITOR 0xa
+#define I2C_MUX_CH_VSC3316_FS 0xc
+#define I2C_MUX_CH_VSC3316_BS 0xd
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR 0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED 10000000
+#define CONFIG_SF_DEFAULT_MODE 0
+
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS 50
+#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS 50
+#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+#define CONFIG_SYS_PMAN
+#define CONFIG_SYS_DPAA_DCE
+#define CONFIG_SYS_DPAA_RMAN
+#define CONFIG_SYS_INTERLAKEN
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 825KB (1650 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_CORTINA
+#define CONFIG_CORTINA_FW_ADDR 0xefe00000
+#define CONFIG_CORTINA_FW_LENGTH 0x40000
+#define CONFIG_PHY_TERANETICS
+#define SGMII_PHY_ADDR1 0x0
+#define SGMII_PHY_ADDR2 0x1
+#define SGMII_PHY_ADDR3 0x2
+#define SGMII_PHY_ADDR4 0x3
+#define SGMII_PHY_ADDR5 0x4
+#define SGMII_PHY_ADDR6 0x5
+#define SGMII_PHY_ADDR7 0x6
+#define SGMII_PHY_ADDR8 0x7
+#define FM1_10GEC1_PHY_ADDR 0x10
+#define FM1_10GEC2_PHY_ADDR 0x11
+#define FM2_10GEC1_PHY_ADDR 0x12
+#define FM2_10GEC2_PHY_ADDR 0x13
+#define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
+#define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
+#define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
+#define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
+#endif
+
+
+/* SATA */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE 2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_ETHPRIME "FM1@DTSEC1"
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+#endif
+
+/*
+* USB
+*/
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#define CONFIG_HAS_FSL_DR_USB
+
+#define CONFIG_MMC
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+
+#define __USB_PHY_TYPE utmi
+
+/*
+ * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
+ * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
+ * interleaving. It can be cacheline, page, bank, superbank.
+ * See doc/README.fsl-ddr for details.
+ */
+#ifdef CONFIG_PPC_T4240
+#define CTRL_INTLV_PREFERED 3way_4KB
+#else
+#define CTRL_INTLV_PREFERED cacheline
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:" \
+ "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
+ "bank_intlv=auto;" \
+ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+ "netdev=eth0\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot && " \
+ "protect off $ubootaddr +$filesize && " \
+ "erase $ubootaddr +$filesize && " \
+ "cp.b $loadaddr $ubootaddr $filesize && " \
+ "protect on $ubootaddr +$filesize && " \
+ "cmp.b $loadaddr $ubootaddr $filesize\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=t4240rdb/t4240rdb.dtb\0" \
+ "bdev=sda3\0"
+
+#define CONFIG_HVBOOT \
+ "setenv bootargs config-addr=0x60000000; " \
+ "bootm 0x01000000 - 0x00f00000"
+
+#define CONFIG_LINUX \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "setenv ramdiskaddr 0x02000000;" \
+ "setenv fdtaddr 0x00c00000;" \
+ "setenv loadaddr 0x1000000;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT \
+ "setenv bootargs root=/dev/$bdev rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_LINUX
+
+#include <asm/fsl_secure_boot.h>
+
+#ifdef CONFIG_SECURE_BOOT
+/* Secure Boot target was not getting build for T4240 because of
+ * increased binary size. So the size is being reduced by removing USB
+ * which is anyways not used in Secure Environment.
+ */
+#undef CONFIG_CMD_USB
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/bct-brettl2.h b/include/configs/bct-brettl2.h
index 06f095c..c1eda96 100644
--- a/include/configs/bct-brettl2.h
+++ b/include/configs/bct-brettl2.h
@@ -75,6 +75,7 @@
#define CONFIG_ROOTPATH "/romfs/brettl2"
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
+#define CONFIG_LIB_RAND
#endif
diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h
index 9eb85eb..9e374c4 100644
--- a/include/configs/bf518f-ezbrd.h
+++ b/include/configs/bf518f-ezbrd.h
@@ -89,7 +89,7 @@
#define CONFIG_PHY_ADDR 3
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h
index 3065d22..972eca9 100644
--- a/include/configs/bf526-ezbrd.h
+++ b/include/configs/bf526-ezbrd.h
@@ -87,7 +87,7 @@
#define CONFIG_HOSTNAME bf526-ezbrd
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h
index 748ddb3..92c183e 100644
--- a/include/configs/bf527-ezkit.h
+++ b/include/configs/bf527-ezkit.h
@@ -85,7 +85,7 @@
#define CONFIG_HOSTNAME bf527-ezkit
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
diff --git a/include/configs/bf537-minotaur.h b/include/configs/bf537-minotaur.h
index 156eeab..3bc364c 100644
--- a/include/configs/bf537-minotaur.h
+++ b/include/configs/bf537-minotaur.h
@@ -89,6 +89,7 @@
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:42 */
+#define CONFIG_LIB_RAND
/*
* Flash Settings
diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h
index 3aa3d50..ba74a69 100644
--- a/include/configs/bf537-pnav.h
+++ b/include/configs/bf537-pnav.h
@@ -67,7 +67,7 @@
#define CONFIG_HOSTNAME bf537-pnav
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:24:21:18 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
diff --git a/include/configs/bf537-srv1.h b/include/configs/bf537-srv1.h
index e12d761..0b723cf 100644
--- a/include/configs/bf537-srv1.h
+++ b/include/configs/bf537-srv1.h
@@ -88,7 +88,7 @@
#define CONFIG_ROOTPATH "/romfs"
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:42 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index e1705ca..a302f83 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -67,7 +67,7 @@
#define CONFIG_HOSTNAME bf537-stamp
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
diff --git a/include/configs/cm-bf527.h b/include/configs/cm-bf527.h
index 384d871..8d3ae49 100644
--- a/include/configs/cm-bf527.h
+++ b/include/configs/cm-bf527.h
@@ -85,7 +85,7 @@
#define CONFIG_HOSTNAME cm-bf527
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h
index 67cf801..47967d7 100644
--- a/include/configs/cm-bf537e.h
+++ b/include/configs/cm-bf537e.h
@@ -73,7 +73,7 @@
#define CONFIG_HOSTNAME cm-bf537e
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h
index 34ce75b..88c9982 100644
--- a/include/configs/cm-bf537u.h
+++ b/include/configs/cm-bf537u.h
@@ -71,7 +71,7 @@
#define CONFIG_HOSTNAME cm-bf537u
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index db6b9be..12b3296 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -10,6 +10,9 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
#include "../board/freescale/common/ics307_clk.h"
#ifdef CONFIG_RAMBOOT_PBL
@@ -376,15 +379,15 @@
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
@@ -712,8 +715,7 @@
"ramdiskfile=p4080ds/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=p4080ds/p4080ds.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
#define CONFIG_HDBOOT \
"setenv bootargs root=/dev/$bdev rw " \
diff --git a/include/configs/dnp5370.h b/include/configs/dnp5370.h
index 4f2c742..3f1f9f3 100644
--- a/include/configs/dnp5370.h
+++ b/include/configs/dnp5370.h
@@ -55,6 +55,8 @@
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
+
+#define CONFIG_LIB_RAND
#endif
/*
diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h
index 613f7e1..c1b3b63 100644
--- a/include/configs/ids8313.h
+++ b/include/configs/ids8313.h
@@ -474,7 +474,6 @@
#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_HZ 1000
/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
diff --git a/include/configs/ip04.h b/include/configs/ip04.h
index 0efa2b7..3767502 100644
--- a/include/configs/ip04.h
+++ b/include/configs/ip04.h
@@ -77,6 +77,7 @@
#define DM9000_IO CONFIG_DM9000_BASE
#define DM9000_DATA (CONFIG_DM9000_BASE + 2)
+#define CONFIG_LIB_RAND
/*
* Flash Settings
diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h
index 418e3d1..efd9635 100644
--- a/include/configs/km/kmp204x-common.h
+++ b/include/configs/km/kmp204x-common.h
@@ -85,11 +85,7 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_ADDR_MAP
#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00800000
-#define CONFIG_SYS_ALT_MEMTEST
-#define CONFIG_PANIC_HANG /* do not reset board on panic */
+#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */
/*
* Config the L3 Cache as L3 SRAM
@@ -143,10 +139,12 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_KM_PNVRAM 0x80000
/* physical RAM MTD size [hex] */
#define CONFIG_KM_PHRAM 0x100000
-/* resereved pram area at the end of memroy [hex] */
-#define CONFIG_KM_RESERVED_PRAM 0x0
-/* enable protected RAM */
-#define CONFIG_PRAM 0
+/* reserved pram area at the end of memory [hex]
+ * u-boot reserves some memory for the MP boot page */
+#define CONFIG_KM_RESERVED_PRAM 0x1000
+/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
+ * is not valid yet, which is the case for when u-boot copies itself to RAM */
+#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10)
#define CONFIG_KM_CRAMFS_ADDR 0x2000000
#define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */
@@ -383,6 +381,7 @@ int get_scl(void);
*/
#define CONFIG_CMD_PCI
#define CONFIG_CMD_NET
+#define CONFIG_CMD_ERRATA
/* we don't need flash support */
#define CONFIG_SYS_NO_FLASH
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index e745945..185df77 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -10,6 +10,9 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
#ifdef CONFIG_36BIT
#define CONFIG_PHYS_64BIT
#endif
@@ -883,6 +886,10 @@
#endif
#endif
+#if defined(CONFIG_P1020RDB_PD)
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#endif
+
#define CONFIG_MMC
#ifdef CONFIG_MMC
diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h
index 10e014d..763a47a 100644
--- a/include/configs/qemu-ppce500.h
+++ b/include/configs/qemu-ppce500.h
@@ -19,6 +19,7 @@
#undef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xf01000 /* 15 MB */
+#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h
index 91cc7d8..41c946d 100644
--- a/include/configs/sama5d3_xplained.h
+++ b/include/configs/sama5d3_xplained.h
@@ -17,7 +17,6 @@
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_AT91FAMILY
#define CONFIG_ARCH_CPU_INIT
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index fa62cb6..6bb2546 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -140,8 +140,6 @@
#define CONFIG_CROS_EC
#define CONFIG_CMD_CROS_EC
#define CONFIG_CROS_EC_SANDBOX
-#define CONFIG_KEYBOARD
-#define CONFIG_CROS_EC_KEYB
#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_BOARD_LATE_INIT
@@ -149,7 +147,12 @@
#define CONFIG_SOUND_SANDBOX
#define CONFIG_CMD_SOUND
+#ifndef SANDBOX_NO_SDL
#define CONFIG_SANDBOX_SDL
+#endif
+
+/* LCD and keyboard require SDL support */
+#ifdef CONFIG_SANDBOX_SDL
#define CONFIG_LCD
#define CONFIG_VIDEO_SANDBOX_SDL
#define CONFIG_CMD_BMP
@@ -158,9 +161,18 @@
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define LCD_BPP LCD_COLOR16
+#define CONFIG_CROS_EC_KEYB
+#define CONFIG_KEYBOARD
+
#define CONFIG_EXTRA_ENV_SETTINGS "stdin=serial,cros-ec-keyb\0" \
"stdout=serial,lcd\0" \
"stderr=serial,lcd\0"
+#else
+
+#define CONFIG_EXTRA_ENV_SETTINGS "stdin=serial\0" \
+ "stdout=serial,lcd\0" \
+ "stderr=serial,lcd\0"
+#endif
#define CONFIG_GZIP_COMPRESSED
#define CONFIG_BZIP2
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index 36bc529..75609b9 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -10,6 +10,8 @@
#ifndef __T4QDS_H
#define __T4QDS_H
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_CMD_REGINFO
/* High Level Configuration Options */
diff --git a/include/configs/tcm-bf518.h b/include/configs/tcm-bf518.h
index 1ff34d5..a77ba69 100644
--- a/include/configs/tcm-bf518.h
+++ b/include/configs/tcm-bf518.h
@@ -68,7 +68,7 @@
#define CONFIG_HOSTNAME tcm-bf518
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h
index 370d97f..c4c1c57 100644
--- a/include/configs/tcm-bf537.h
+++ b/include/configs/tcm-bf537.h
@@ -73,7 +73,7 @@
#define CONFIG_HOSTNAME tcm-bf537
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
-
+#define CONFIG_LIB_RAND
/*
* Flash Settings
diff --git a/include/ext4fs.h b/include/ext4fs.h
index aacb147..fbbb002 100644
--- a/include/ext4fs.h
+++ b/include/ext4fs.h
@@ -133,6 +133,7 @@ int ext4fs_open(const char *filename);
int ext4fs_read(char *buf, unsigned len);
int ext4fs_mount(unsigned part_length);
void ext4fs_close(void);
+void ext4fs_reinit_global(void);
int ext4fs_ls(const char *dirname);
int ext4fs_exists(const char *filename);
void ext4fs_free_node(struct ext2fs_node *node, struct ext2fs_node *currroot);
diff --git a/include/fat.h b/include/fat.h
index c8eb7cc..81d9790 100644
--- a/include/fat.h
+++ b/include/fat.h
@@ -84,8 +84,13 @@
#define START(dent) (FAT2CPU16((dent)->start) \
+ (mydata->fatsize != 32 ? 0 : \
(FAT2CPU16((dent)->starthi) << 16)))
+#define IS_LAST_CLUST(x, fatsize) ((x) >= ((fatsize) != 32 ? \
+ ((fatsize) != 16 ? 0xff8 : 0xfff8) : \
+ 0xffffff8))
#define CHECK_CLUST(x, fatsize) ((x) <= 1 || \
- (x) >= ((fatsize) != 32 ? 0xfff0 : 0xffffff0))
+ (x) >= ((fatsize) != 32 ? \
+ ((fatsize) != 16 ? 0xff0 : 0xfff0) : \
+ 0xffffff0))
typedef struct boot_sector {
__u8 ignored[3]; /* Bootstrap code */
diff --git a/include/net.h b/include/net.h
index 0802fad..735b0b9 100644
--- a/include/net.h
+++ b/include/net.h
@@ -130,23 +130,6 @@ extern int eth_setenv_enetaddr(char *name, const uchar *enetaddr);
extern int eth_getenv_enetaddr_by_index(const char *base_name, int index,
uchar *enetaddr);
-#ifdef CONFIG_RANDOM_MACADDR
-/*
- * The u-boot policy does not allow hardcoded ethernet addresses. Under the
- * following circumstances a random generated address is allowed:
- * - in emergency cases, where you need a working network connection to set
- * the ethernet address.
- * Eg. you want a rescue boot and don't have a serial port to access the
- * CLI to set environment variables.
- *
- * In these cases, we generate a random locally administered ethernet address.
- *
- * Args:
- * enetaddr - returns 6 byte hardware address
- */
-extern void eth_random_enetaddr(uchar *enetaddr);
-#endif
-
extern int usb_eth_initialize(bd_t *bi);
extern int eth_init(bd_t *bis); /* Initialize the device */
extern int eth_send(void *packet, int length); /* Send a packet */
@@ -674,6 +657,25 @@ static inline int is_valid_ether_addr(const u8 *addr)
return !is_multicast_ether_addr(addr) && !is_zero_ether_addr(addr);
}
+/**
+ * eth_random_addr - Generate software assigned random Ethernet address
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Generate a random Ethernet address (MAC) that is not multicast
+ * and has the local assigned bit set.
+ */
+static inline void eth_random_addr(uchar *addr)
+{
+ int i;
+ unsigned int seed = get_timer(0);
+
+ for (i = 0; i < 6; i++)
+ addr[i] = rand_r(&seed);
+
+ addr[0] &= 0xfe; /* clear multicast bit */
+ addr[0] |= 0x02; /* set local assignment bit (IEEE802) */
+}
+
/* Convert an IP address to a string */
extern void ip_to_string(IPaddr_t x, char *s);
diff --git a/include/ns16550.h b/include/ns16550.h
index 51cb5b4..17f829f 100644
--- a/include/ns16550.h
+++ b/include/ns16550.h
@@ -100,6 +100,7 @@ typedef struct NS16550 *NS16550_t;
#define UART_MCR_OUT1 0x04 /* Out 1 */
#define UART_MCR_OUT2 0x08 /* Out 2 */
#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
+#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */
#define UART_MCR_DMA_EN 0x04
#define UART_MCR_TX_DFR 0x08
diff --git a/include/spartan2.h b/include/spartan2.h
index 087a27d..2aca954 100644
--- a/include/spartan2.h
+++ b/include/spartan2.h
@@ -10,37 +10,35 @@
#include <xilinx.h>
-extern int Spartan2_load(Xilinx_desc *desc, const void *image, size_t size);
-extern int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-extern int Spartan2_info(Xilinx_desc *desc);
-
/* Slave Parallel Implementation function table */
typedef struct {
- Xilinx_pre_fn pre;
- Xilinx_pgm_fn pgm;
- Xilinx_init_fn init;
- Xilinx_err_fn err;
- Xilinx_done_fn done;
- Xilinx_clk_fn clk;
- Xilinx_cs_fn cs;
- Xilinx_wr_fn wr;
- Xilinx_rdata_fn rdata;
- Xilinx_wdata_fn wdata;
- Xilinx_busy_fn busy;
- Xilinx_abort_fn abort;
- Xilinx_post_fn post;
-} Xilinx_Spartan2_Slave_Parallel_fns;
+ xilinx_pre_fn pre;
+ xilinx_pgm_fn pgm;
+ xilinx_init_fn init;
+ xilinx_err_fn err;
+ xilinx_done_fn done;
+ xilinx_clk_fn clk;
+ xilinx_cs_fn cs;
+ xilinx_wr_fn wr;
+ xilinx_rdata_fn rdata;
+ xilinx_wdata_fn wdata;
+ xilinx_busy_fn busy;
+ xilinx_abort_fn abort;
+ xilinx_post_fn post;
+} xilinx_spartan2_slave_parallel_fns;
/* Slave Serial Implementation function table */
typedef struct {
- Xilinx_pre_fn pre;
- Xilinx_pgm_fn pgm;
- Xilinx_clk_fn clk;
- Xilinx_init_fn init;
- Xilinx_done_fn done;
- Xilinx_wr_fn wr;
- Xilinx_post_fn post;
-} Xilinx_Spartan2_Slave_Serial_fns;
+ xilinx_pre_fn pre;
+ xilinx_pgm_fn pgm;
+ xilinx_clk_fn clk;
+ xilinx_init_fn init;
+ xilinx_done_fn done;
+ xilinx_wr_fn wr;
+ xilinx_post_fn post;
+} xilinx_spartan2_slave_serial_fns;
+
+extern struct xilinx_fpga_op spartan2_op;
/* Device Image Sizes
*********************************************************************/
@@ -63,36 +61,36 @@ typedef struct {
*********************************************************************/
/* Spartan-II devices */
#define XILINX_XC2S15_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S30_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S50_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S100_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S150_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S200_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie, &spartan2_op }
#define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie, &spartan2_op }
#endif /* _SPARTAN2_H_ */
diff --git a/include/spartan3.h b/include/spartan3.h
index 72e7c0d..d6d67a6 100644
--- a/include/spartan3.h
+++ b/include/spartan3.h
@@ -10,39 +10,37 @@
#include <xilinx.h>
-extern int Spartan3_load(Xilinx_desc *desc, const void *image, size_t size);
-extern int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-extern int Spartan3_info(Xilinx_desc *desc);
-
/* Slave Parallel Implementation function table */
typedef struct {
- Xilinx_pre_fn pre;
- Xilinx_pgm_fn pgm;
- Xilinx_init_fn init;
- Xilinx_err_fn err;
- Xilinx_done_fn done;
- Xilinx_clk_fn clk;
- Xilinx_cs_fn cs;
- Xilinx_wr_fn wr;
- Xilinx_rdata_fn rdata;
- Xilinx_wdata_fn wdata;
- Xilinx_busy_fn busy;
- Xilinx_abort_fn abort;
- Xilinx_post_fn post;
-} Xilinx_Spartan3_Slave_Parallel_fns;
+ xilinx_pre_fn pre;
+ xilinx_pgm_fn pgm;
+ xilinx_init_fn init;
+ xilinx_err_fn err;
+ xilinx_done_fn done;
+ xilinx_clk_fn clk;
+ xilinx_cs_fn cs;
+ xilinx_wr_fn wr;
+ xilinx_rdata_fn rdata;
+ xilinx_wdata_fn wdata;
+ xilinx_busy_fn busy;
+ xilinx_abort_fn abort;
+ xilinx_post_fn post;
+} xilinx_spartan3_slave_parallel_fns;
/* Slave Serial Implementation function table */
typedef struct {
- Xilinx_pre_fn pre;
- Xilinx_pgm_fn pgm;
- Xilinx_clk_fn clk;
- Xilinx_init_fn init;
- Xilinx_done_fn done;
- Xilinx_wr_fn wr;
- Xilinx_post_fn post;
- Xilinx_bwr_fn bwr; /* block write function */
- Xilinx_abort_fn abort;
-} Xilinx_Spartan3_Slave_Serial_fns;
+ xilinx_pre_fn pre;
+ xilinx_pgm_fn pgm;
+ xilinx_clk_fn clk;
+ xilinx_init_fn init;
+ xilinx_done_fn done;
+ xilinx_wr_fn wr;
+ xilinx_post_fn post;
+ xilinx_bwr_fn bwr; /* block write function */
+ xilinx_abort_fn abort;
+} xilinx_spartan3_slave_serial_fns;
+
+extern struct xilinx_fpga_op spartan3_op;
/* Device Image Sizes
*********************************************************************/
@@ -73,46 +71,48 @@ typedef struct {
*********************************************************************/
/* Spartan-III devices */
#define XILINX_XC3S50_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S200_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S400_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie, &spartan3_op }
/* Spartan-3E devices */
#define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie, &spartan3_op }
#define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie, \
+ &spartan3_op }
#define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie, \
+ &spartan3_op }
#define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie }
+{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie, &spartan3_op }
#endif /* _SPARTAN3_H_ */
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index c9ee1d5..dd77ad6 100644
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -11,6 +11,8 @@
#include <asm/processor.h>
+#define CONTROL_REGISTER_W1C_MASK 0x00020000 /* W1C: PHY_CLK_VALID */
+
/* Global offsets */
#define FSL_SKIP_PCI 0x100
diff --git a/include/virtex2.h b/include/virtex2.h
index 2e9a4f5..7b7825f 100644
--- a/include/virtex2.h
+++ b/include/virtex2.h
@@ -11,36 +11,34 @@
#include <xilinx.h>
-extern int Virtex2_load(Xilinx_desc *desc, const void *image, size_t size);
-extern int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-extern int Virtex2_info(Xilinx_desc *desc);
+extern struct xilinx_fpga_op virtex2_op;
/*
* Slave SelectMap Implementation function table.
*/
typedef struct {
- Xilinx_pre_fn pre;
- Xilinx_pgm_fn pgm;
- Xilinx_init_fn init;
- Xilinx_err_fn err;
- Xilinx_done_fn done;
- Xilinx_clk_fn clk;
- Xilinx_cs_fn cs;
- Xilinx_wr_fn wr;
- Xilinx_rdata_fn rdata;
- Xilinx_wdata_fn wdata;
- Xilinx_busy_fn busy;
- Xilinx_abort_fn abort;
- Xilinx_post_fn post;
-} Xilinx_Virtex2_Slave_SelectMap_fns;
+ xilinx_pre_fn pre;
+ xilinx_pgm_fn pgm;
+ xilinx_init_fn init;
+ xilinx_err_fn err;
+ xilinx_done_fn done;
+ xilinx_clk_fn clk;
+ xilinx_cs_fn cs;
+ xilinx_wr_fn wr;
+ xilinx_rdata_fn rdata;
+ xilinx_wdata_fn wdata;
+ xilinx_busy_fn busy;
+ xilinx_abort_fn abort;
+ xilinx_post_fn post;
+} xilinx_virtex2_slave_selectmap_fns;
/* Slave Serial Implementation function table */
typedef struct {
- Xilinx_pgm_fn pgm;
- Xilinx_clk_fn clk;
- Xilinx_rdata_fn rdata;
- Xilinx_wdata_fn wdata;
-} Xilinx_Virtex2_Slave_Serial_fns;
+ xilinx_pgm_fn pgm;
+ xilinx_clk_fn clk;
+ xilinx_rdata_fn rdata;
+ xilinx_wdata_fn wdata;
+} xilinx_virtex2_slave_serial_fns;
/* Device Image Sizes (in bytes)
*********************************************************************/
@@ -60,39 +58,39 @@ typedef struct {
/* Descriptor Macros
*********************************************************************/
#define XILINX_XC2V40_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V80_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V250_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V500_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, &virtex2_op }
#define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, &virtex2_op }
#endif /* _VIRTEX2_H_ */
diff --git a/include/xilinx.h b/include/xilinx.h
index 00a585e..9801267 100644
--- a/include/xilinx.h
+++ b/include/xilinx.h
@@ -12,7 +12,7 @@
/* Xilinx types
*********************************************************************/
-typedef enum { /* typedef Xilinx_iface */
+typedef enum { /* typedef xilinx_iface */
min_xilinx_iface_type, /* low range check value */
slave_serial, /* serial data and external clock */
master_serial, /* serial data w/ internal clock (not used) */
@@ -22,48 +22,55 @@ typedef enum { /* typedef Xilinx_iface */
slave_selectmap, /* slave SelectMap (virtex2) */
devcfg, /* devcfg interface (zynq) */
max_xilinx_iface_type /* insert all new types before this */
-} Xilinx_iface; /* end, typedef Xilinx_iface */
+} xilinx_iface; /* end, typedef xilinx_iface */
-typedef enum { /* typedef Xilinx_Family */
+typedef enum { /* typedef xilinx_family */
min_xilinx_type, /* low range check value */
- Xilinx_Spartan2, /* Spartan-II Family */
- Xilinx_VirtexE, /* Virtex-E Family */
- Xilinx_Virtex2, /* Virtex2 Family */
- Xilinx_Spartan3, /* Spartan-III Family */
+ xilinx_spartan2, /* Spartan-II Family */
+ xilinx_virtexE, /* Virtex-E Family */
+ xilinx_virtex2, /* Virtex2 Family */
+ xilinx_spartan3, /* Spartan-III Family */
xilinx_zynq, /* Zynq Family */
max_xilinx_type /* insert all new types before this */
-} Xilinx_Family; /* end, typedef Xilinx_Family */
+} xilinx_family; /* end, typedef xilinx_family */
-typedef struct { /* typedef Xilinx_desc */
- Xilinx_Family family; /* part type */
- Xilinx_iface iface; /* interface type */
+typedef struct { /* typedef xilinx_desc */
+ xilinx_family family; /* part type */
+ xilinx_iface iface; /* interface type */
size_t size; /* bytes of data part can accept */
void *iface_fns; /* interface function table */
int cookie; /* implementation specific cookie */
+ struct xilinx_fpga_op *operations; /* operations */
char *name; /* device name in bitstream */
-} Xilinx_desc; /* end, typedef Xilinx_desc */
+} xilinx_desc; /* end, typedef xilinx_desc */
+
+struct xilinx_fpga_op {
+ int (*load)(xilinx_desc *, const void *, size_t);
+ int (*dump)(xilinx_desc *, const void *, size_t);
+ int (*info)(xilinx_desc *);
+};
/* Generic Xilinx Functions
*********************************************************************/
-extern int xilinx_load(Xilinx_desc *desc, const void *image, size_t size);
-extern int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-extern int xilinx_info(Xilinx_desc *desc);
+int xilinx_load(xilinx_desc *desc, const void *image, size_t size);
+int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize);
+int xilinx_info(xilinx_desc *desc);
/* Board specific implementation specific function types
*********************************************************************/
-typedef int (*Xilinx_pgm_fn)( int assert_pgm, int flush, int cookie );
-typedef int (*Xilinx_init_fn)( int cookie );
-typedef int (*Xilinx_err_fn)( int cookie );
-typedef int (*Xilinx_done_fn)( int cookie );
-typedef int (*Xilinx_clk_fn)( int assert_clk, int flush, int cookie );
-typedef int (*Xilinx_cs_fn)( int assert_cs, int flush, int cookie );
-typedef int (*Xilinx_wr_fn)( int assert_write, int flush, int cookie );
-typedef int (*Xilinx_rdata_fn)( unsigned char *data, int cookie );
-typedef int (*Xilinx_wdata_fn)( unsigned char data, int flush, int cookie );
-typedef int (*Xilinx_busy_fn)( int cookie );
-typedef int (*Xilinx_abort_fn)( int cookie );
-typedef int (*Xilinx_pre_fn)( int cookie );
-typedef int (*Xilinx_post_fn)( int cookie );
-typedef int (*Xilinx_bwr_fn)( void *buf, size_t len, int flush, int cookie );
+typedef int (*xilinx_pgm_fn)(int assert_pgm, int flush, int cookie);
+typedef int (*xilinx_init_fn)(int cookie);
+typedef int (*xilinx_err_fn)(int cookie);
+typedef int (*xilinx_done_fn)(int cookie);
+typedef int (*xilinx_clk_fn)(int assert_clk, int flush, int cookie);
+typedef int (*xilinx_cs_fn)(int assert_cs, int flush, int cookie);
+typedef int (*xilinx_wr_fn)(int assert_write, int flush, int cookie);
+typedef int (*xilinx_rdata_fn)(unsigned char *data, int cookie);
+typedef int (*xilinx_wdata_fn)(unsigned char data, int flush, int cookie);
+typedef int (*xilinx_busy_fn)(int cookie);
+typedef int (*xilinx_abort_fn)(int cookie);
+typedef int (*xilinx_pre_fn)(int cookie);
+typedef int (*xilinx_post_fn)(int cookie);
+typedef int (*xilinx_bwr_fn)(void *buf, size_t len, int flush, int cookie);
#endif /* _XILINX_H_ */
diff --git a/include/zynqpl.h b/include/zynqpl.h
index c81446e..8a9ec32 100644
--- a/include/zynqpl.h
+++ b/include/zynqpl.h
@@ -12,9 +12,7 @@
#include <xilinx.h>
-extern int zynq_load(Xilinx_desc *desc, const void *image, size_t size);
-extern int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-extern int zynq_info(Xilinx_desc *desc);
+extern struct xilinx_fpga_op zynq_op;
#define XILINX_ZYNQ_7010 0x2
#define XILINX_ZYNQ_7015 0x1b
@@ -33,21 +31,21 @@ extern int zynq_info(Xilinx_desc *desc);
/* Descriptor Macros */
#define XILINX_XC7Z010_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, "7z010" }
+{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, &zynq_op, "7z010" }
#define XILINX_XC7Z015_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, "7z015" }
+{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, &zynq_op, "7z015" }
#define XILINX_XC7Z020_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, "7z020" }
+{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, &zynq_op, "7z020" }
#define XILINX_XC7Z030_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, "7z030" }
+{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, &zynq_op, "7z030" }
#define XILINX_XC7Z045_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, "7z045" }
+{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, &zynq_op, "7z045" }
#define XILINX_XC7Z100_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, "7z100" }
+{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, &zynq_op, "7z100" }
#endif /* _ZYNQPL_H_ */