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| author | Simon Glass <sjg@chromium.org> | 2015-07-02 18:16:00 -0600 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-08-05 21:06:12 -0600 |
| commit | d308c0136d8a530d4846ab08ce02e6d40614d7e7 (patch) | |
| tree | 664cbddfd13be61df58efe17ef007d664f7c52b9 /include | |
| parent | 1c88b67ec8faa33c12438cab8a5191bbab6c85e3 (diff) | |
| download | u-boot-imx-d308c0136d8a530d4846ab08ce02e6d40614d7e7.zip u-boot-imx-d308c0136d8a530d4846ab08ce02e6d40614d7e7.tar.gz u-boot-imx-d308c0136d8a530d4846ab08ce02e6d40614d7e7.tar.bz2 | |
dm: power: Add support for the S5M8767 PMIC
This PMIC is used with SoCs which need a combination of BUCKs and LDOs. The
driver supports probing and basic register access. It supports the standard
device tree binding and supports driver model. A regulator driver can be
provided also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/power/s5m8767.h | 85 |
1 files changed, 85 insertions, 0 deletions
diff --git a/include/power/s5m8767.h b/include/power/s5m8767.h new file mode 100644 index 0000000..ba88ff7 --- /dev/null +++ b/include/power/s5m8767.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __S5M8767_H_ +#define __S5M8767_H_ + +enum s5m8767_regnum { + S5M8767_BUCK1 = 0, + S5M8767_BUCK2, + S5M8767_BUCK3, + S5M8767_BUCK4, + S5M8767_BUCK5, + S5M8767_BUCK6, + S5M8767_BUCK7, + S5M8767_BUCK8, + S5M8767_BUCK9, + S5M8767_LDO1, + S5M8767_LDO2, + S5M8767_LDO3, + S5M8767_LDO4, + S5M8767_LDO5, + S5M8767_LDO6, + S5M8767_LDO7, + S5M8767_LDO8, + S5M8767_LDO9, + S5M8767_LDO10, + S5M8767_LDO11, + S5M8767_LDO12, + S5M8767_LDO13, + S5M8767_LDO14, + S5M8767_LDO15, + S5M8767_LDO16, + S5M8767_LDO17, + S5M8767_LDO18, + S5M8767_LDO19, + S5M8767_LDO20, + S5M8767_LDO21, + S5M8767_LDO22, + S5M8767_LDO23, + S5M8767_LDO24, + S5M8767_LDO25, + S5M8767_LDO26, + S5M8767_LDO27, + S5M8767_LDO28, + S5M8767_EN32KHZ_CP, + + S5M8767_NUM_OF_REGS, +}; + +struct sec_voltage_desc { + int max; + int min; + int step; +}; + +/** + * struct s5m8767_para - s5m8767 register parameters + * @param vol_addr i2c address of the given buck/ldo register + * @param vol_bitpos bit position to be set or clear within register + * @param vol_bitmask bit mask value + * @param reg_enaddr control register address, which enable the given + * given buck/ldo. + * @param reg_enbiton value to be written to buck/ldo to make it ON + * @param vol Voltage information + */ +struct s5m8767_para { + enum s5m8767_regnum regnum; + u8 vol_addr; + u8 vol_bitpos; + u8 vol_bitmask; + u8 reg_enaddr; + u8 reg_enbiton; + const struct sec_voltage_desc *vol; +}; + +/* Drivers name */ +#define S5M8767_LDO_DRIVER "s5m8767_ldo" +#define S5M8767_BUCK_DRIVER "s5m8767_buck" + +int s5m8767_enable_32khz_cp(struct udevice *dev); + +#endif /* __S5M8767_PMIC_H_ */ |