summaryrefslogtreecommitdiff
path: root/include
diff options
context:
space:
mode:
authorEnric Balletbò i Serra <eballetbo@gmail.com>2013-12-06 21:30:21 +0100
committerTom Rini <trini@ti.com>2014-01-24 11:38:39 -0500
commitc6a7fce1138596b9e91727c32da2c2faa3bb481f (patch)
treef23e8551afb72a4f07a01accbd226ccd947c33bc /include
parent70e71b61bca9c44708a449461f0dc5a51d7cf622 (diff)
downloadu-boot-imx-c6a7fce1138596b9e91727c32da2c2faa3bb481f.zip
u-boot-imx-c6a7fce1138596b9e91727c32da2c2faa3bb481f.tar.gz
u-boot-imx-c6a7fce1138596b9e91727c32da2c2faa3bb481f.tar.bz2
TI: armv7: Do not define the number DRAM banks if is already defined.
If CONFIG_NR_DRAM_BANKS is not defined, we say (for simplicity) that we have 1 bank, but for some boards should be interesting that we can define CONFIG_NR_DRAM_BANKS. To handle this possibility just define the number of DRAM banks if is not already defined. This is useful for some OMAP3 boards where the DRAM initialitzation is only at u-boot level. Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Diffstat (limited to 'include')
-rw-r--r--include/configs/ti_armv7_common.h10
1 files changed, 7 insertions, 3 deletions
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index f4e42ef..69d69a5 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -45,11 +45,15 @@
#define CONFIG_BOOTDELAY 1
/*
- * DDR information. We say (for simplicity) that we have 1 bank,
- * always, even when we have more. We always start at 0x80000000,
- * and we place the initial stack pointer in our SRAM.
+ * DDR information. If the CONFIG_NR_DRAM_BANKS is not defined,
+ * we say (for simplicity) that we have 1 bank, always, even when
+ * we have more. We always start at 0x80000000, and we place the
+ * initial stack pointer in our SRAM. Otherwise, we can define
+ * CONFIG_NR_DRAM_BANKS before including this file.
*/
+#ifndef CONFIG_NR_DRAM_BANKS
#define CONFIG_NR_DRAM_BANKS 1
+#endif
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
GENERATED_GBL_DATA_SIZE)