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| author | Peng Fan <Peng.Fan@freescale.com> | 2015-08-07 16:43:45 +0800 |
|---|---|---|
| committer | Przemyslaw Marczak <p.marczak@samsung.com> | 2015-08-12 11:04:58 +0200 |
| commit | 8fa46350a4c7dca7710362f6c871098557b934ad (patch) | |
| tree | 5f5e338cd06583b60e79a30cd26688fbbef9ca3c /include | |
| parent | 3e91a6d0d6cd78feb64996e694b6f8f00e456f27 (diff) | |
| download | u-boot-imx-8fa46350a4c7dca7710362f6c871098557b934ad.zip u-boot-imx-8fa46350a4c7dca7710362f6c871098557b934ad.tar.gz u-boot-imx-8fa46350a4c7dca7710362f6c871098557b934ad.tar.bz2 | |
power: regulator: add pfuze100 support
1. Add new regulator driver pfuze100.
* Introduce struct pfuze100_regulator_desc for maintaining info
for one regulator.
2. Add new Kconfig entry DM_REGULATOR_PFUZE100 for pfuze100.
3. This driver intends to support PF100, PF200 and PF3000.
4. Add related macro definition in pfuze header file.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/power/pfuze100_pmic.h | 24 |
1 files changed, 20 insertions, 4 deletions
diff --git a/include/power/pfuze100_pmic.h b/include/power/pfuze100_pmic.h index cb10605..138132a 100644 --- a/include/power/pfuze100_pmic.h +++ b/include/power/pfuze100_pmic.h @@ -57,6 +57,13 @@ enum { PMIC_NUM_OF_REGS = 0x7f, }; +/* Registor offset based on VOLT register */ +#define PFUZE100_VOL_OFFSET 0 +#define PFUZE100_STBY_OFFSET 1 +#define PFUZE100_OFF_OFFSET 2 +#define PFUZE100_MODE_OFFSET 3 +#define PFUZE100_CONF_OFFSET 4 + /* * Buck Regulators */ @@ -133,6 +140,9 @@ enum { #define SW1x_STBY_MASK 0x3f #define SW1x_OFF_MASK 0x3f +#define SW_MODE_MASK 0xf +#define SW_MODE_SHIFT 0 + #define SW1xCONF_DVSSPEED_MASK 0xc0 #define SW1xCONF_DVSSPEED_2US 0x00 #define SW1xCONF_DVSSPEED_4US 0x40 @@ -181,7 +191,12 @@ enum { #define LDO_VOL_MASK 0xf #define LDO_EN (1 << 4) +#define LDO_MODE_SHIFT 4 +#define LDO_MODE_MASK (1 << 4) +#define LDO_MODE_OFF 0 +#define LDO_MODE_ON 1 +#define VREFDDRCON_EN (1 << 4) /* * Boost Regulator */ @@ -194,10 +209,11 @@ enum { #define SWBST_VOL_MASK 0x3 #define SWBST_MODE_MASK 0xC -#define SWBST_MODE_OFF (0 << 2) -#define SWBST_MODE_PFM (1 << 2) -#define SWBST_MODE_AUTO (2 << 2) -#define SWBST_MODE_APS (3 << 2) +#define SWBST_MODE_SHIFT 0x2 +#define SWBST_MODE_OFF 0 +#define SWBST_MODE_PFM 1 +#define SWBST_MODE_AUTO 2 +#define SWBST_MODE_APS 3 /* * Regulator Mode Control |