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| author | York Sun <yorksun@freescale.com> | 2015-11-04 09:53:10 -0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-11-30 09:11:11 -0800 |
| commit | 61bd2f75f5eaf645e2c90fe2294cba37f7d8627f (patch) | |
| tree | 1915b86c9f0ac16bb7bcc867f9412530de4588eb /include | |
| parent | 7023100971c96b043b0aee669c45d1fcb3e8557b (diff) | |
| download | u-boot-imx-61bd2f75f5eaf645e2c90fe2294cba37f7d8627f.zip u-boot-imx-61bd2f75f5eaf645e2c90fe2294cba37f7d8627f.tar.gz u-boot-imx-61bd2f75f5eaf645e2c90fe2294cba37f7d8627f.tar.bz2 | |
drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3
Freescale LSCH3 platforms use two DDR controlers interleaving mode out of
reset. It can be configured to disable one controller. To support this
operation, the driver needs to detect and skip the disabled controller.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/fsl_ddr.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h index 1ac092b..9aaf6b3 100644 --- a/include/fsl_ddr.h +++ b/include/fsl_ddr.h @@ -131,6 +131,7 @@ void board_add_ram_info(int use_default); /* processor specific function */ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, unsigned int ctrl_num, int step); +void remove_unused_controllers(fsl_ddr_info_t *info); /* board specific function */ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, |