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| author | Gabriel Huau <contact@huau-gabriel.fr> | 2015-05-25 22:27:37 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-06-04 03:32:08 -0600 |
| commit | 5318f18d2c002f505054b90bb95ba7c53532eedf (patch) | |
| tree | c9e25f8c9fc57dbeba19b617f421b6f1ba7ca8d1 /include | |
| parent | afbbd413a3ef8a45155fcd083814ba645b09fcc7 (diff) | |
| download | u-boot-imx-5318f18d2c002f505054b90bb95ba7c53532eedf.zip u-boot-imx-5318f18d2c002f505054b90bb95ba7c53532eedf.tar.gz u-boot-imx-5318f18d2c002f505054b90bb95ba7c53532eedf.tar.bz2 | |
x86: gpio: add pinctrl support from the device tree
Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.
Change-Id: I1668886062655f83700d0e7bbbe3ad09b19ee975
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/gpio/x86-gpio.h | 31 | ||||
| -rw-r--r-- | include/fdtdec.h | 1 |
2 files changed, 32 insertions, 0 deletions
diff --git a/include/dt-bindings/gpio/x86-gpio.h b/include/dt-bindings/gpio/x86-gpio.h new file mode 100644 index 0000000..7f1de30 --- /dev/null +++ b/include/dt-bindings/gpio/x86-gpio.h @@ -0,0 +1,31 @@ +/* + * This header provides constants for binding intel,x86-pinctrl. + */ + +#ifndef _DT_BINDINGS_GPIO_X86_GPIO_H +#define _DT_BINDINGS_GPIO_X86_GPIO_H + +#include <dt-bindings/gpio/gpio.h> + +#define GPIO_MODE_NATIVE 0 +#define GPIO_MODE_GPIO 1 + +#define GPIO_MODE_FUNC0 0 +#define GPIO_MODE_FUNC1 1 +#define GPIO_MODE_FUNC2 2 +#define GPIO_MODE_FUNC3 3 +#define GPIO_MODE_FUNC4 4 +#define GPIO_MODE_FUNC5 5 +#define GPIO_MODE_FUNC6 6 + +#define PIN_INPUT 0 +#define PIN_OUTPUT 1 + +#define PIN_INPUT_NOPULL 0 +#define PIN_INPUT_PULLUP 1 +#define PIN_INPUT_PULLDOWN 2 + +#define PULL_STR_2K 0 +#define PULL_STR_20K 2 + +#endif diff --git a/include/fdtdec.h b/include/fdtdec.h index 64c7fa1..4fb8a2a 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -176,6 +176,7 @@ enum fdt_compat_id { COMPAT_AMS_AS3722, /* AMS AS3722 PMIC */ COMPAT_INTEL_ICH_SPI, /* Intel ICH7/9 SPI controller */ COMPAT_INTEL_QRK_MRC, /* Intel Quark MRC */ + COMPAT_INTEL_X86_PINCTRL, /* Intel ICH7/9 pin control */ COMPAT_SOCIONEXT_XHCI, /* Socionext UniPhier xHCI */ COMPAT_INTEL_PCH, /* Intel PCH */ COMPAT_INTEL_IRQ_ROUTER, /* Intel Interrupt Router */ |