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| author | Peng Fan <peng.fan@nxp.com> | 2016-04-12 16:11:54 +0800 |
|---|---|---|
| committer | Peng Fan <peng.fan@nxp.com> | 2016-04-13 13:03:20 +0800 |
| commit | 67c19ad1a21780783efbcf1899cb6fdd7726ead7 (patch) | |
| tree | e5a519de708097dcf3cc387df161a2b90a60cf6e /include | |
| parent | 3f5962277e5ea5ebb99b35ab6a8fb4fecf1ba62b (diff) | |
| download | u-boot-imx-67c19ad1a21780783efbcf1899cb6fdd7726ead7.zip u-boot-imx-67c19ad1a21780783efbcf1899cb6fdd7726ead7.tar.gz u-boot-imx-67c19ad1a21780783efbcf1899cb6fdd7726ead7.tar.bz2 | |
MLK-12616-11 imx: mx6ull: add mx6ull arm2 board support
Support mx6ull ddr3 arm2 board.
DDR script version 1.1. Passed memtester on 3 boards.
Take mx6ul 14x14 ddr3 arm2 as reference.
Note:
LCD/NAND/ECSPI not tested, need hardware rework.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 584050b98cf070bb608b652e89659ff20c47efba)
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/mx6ull_ddr3_arm2.h | 69 |
1 files changed, 69 insertions, 0 deletions
diff --git a/include/configs/mx6ull_ddr3_arm2.h b/include/configs/mx6ull_ddr3_arm2.h new file mode 100644 index 0000000..6d4801a --- /dev/null +++ b/include/configs/mx6ull_ddr3_arm2.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6UL 14x14 DDR3 ARM2. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __MX6ULL_DDR3_ARM2_CONFIG_H +#define __MX6ULL_DDR3_ARM2_CONFIG_H + +#define CONFIG_DEFAULT_FDT_FILE "imx6ull-ddr3-arm2.dtb" + +#ifdef CONFIG_SYS_BOOT_QSPI +#define CONFIG_SYS_USE_QSPI +#define CONFIG_ENV_IS_IN_SPI_FLASH +#elif defined CONFIG_SYS_BOOT_SPINOR +#define CONFIG_SYS_USE_SPINOR +#define CONFIG_ENV_IS_IN_SPI_FLASH +#elif defined CONFIG_SYS_BOOT_NAND +#define CONFIG_SYS_USE_NAND +#define CONFIG_ENV_IS_IN_NAND +#else +#define CONFIG_ENV_IS_IN_MMC +#endif + +#define CONFIG_VIDEO +#define CONFIG_FSL_USDHC +#define CONFIG_BOOTARGS_CMA_SIZE "" + +#include "mx6ul_arm2.h" + +#define PHYS_SDRAM_SIZE SZ_1G + +#ifdef CONFIG_SYS_USE_SPINOR +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#define CONFIG_SF_DEFAULT_CS 0 +#endif + +#ifdef CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_ENET_DEV 1 + +#if (CONFIG_FEC_ENET_DEV == 0) +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_FEC_XCV_TYPE RMII +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE ENET2_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x2 +#define CONFIG_FEC_XCV_TYPE MII100 +#endif +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_FEC_DMA_MINALIGN 64 +#endif + +#endif |