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authorStefan Roese <sr@denx.de>2007-07-31 08:37:01 +0200
committerStefan Roese <sr@denx.de>2007-07-31 08:37:01 +0200
commitea9f6bce383cc9fbcdee28b5836109b1a6dba574 (patch)
treed9059c7f3842f92c0bcf047b86fab4c44863ea78 /include
parent27a528fb41433c4c1e2b5d6bd3fd8d78606fc724 (diff)
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ppc4xx: Update 440EPx lwmon5 board support
- Clear ECC status regs after ECC POST test - Set dcbz for ECC generation with caches enabled as default - Code cleanup Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include')
-rw-r--r--include/configs/lwmon5.h1
-rw-r--r--include/ppc440.h13
2 files changed, 13 insertions, 1 deletions
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index b09b478..5ebe440 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -140,7 +140,6 @@
/* POST support */
#define CONFIG_POST (CFG_POST_ECC)
-
#endif
/*-----------------------------------------------------------------------
diff --git a/include/ppc440.h b/include/ppc440.h
index 93c10f1..38809f3 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -3354,6 +3354,19 @@ typedef struct {
unsigned long pciClkSync; /* PCI clock is synchronous */
} PPC440_SYS_INFO;
+static inline u32 get_mcsr(void)
+{
+ u32 val;
+
+ asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
+ return val;
+}
+
+static inline void set_mcsr(u32 val)
+{
+ asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
+}
+
#endif /* _ASMLANGUAGE */
#define RESET_VECTOR 0xfffffffc