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authorPeter Tyser <ptyser@xes-inc.com>2009-07-17 10:14:45 -0500
committerKumar Gala <galak@kernel.crashing.org>2009-07-22 09:43:47 -0500
commite7ee23ec1788d8cf269a4cf6b9cd3722cbc7d592 (patch)
treed849696bd6a8c4f4f561381bbec53b5c82f5dacf /include
parentf6155c6fbb1d85f517b7c160570f0995ef14c43f (diff)
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86xx: Rename ccsr_ddr's sdram_mode_1, sdram_cfg_1 fields
Rename sdram_mode_1 to sdram_mode and sdram_cfg_1 to sdram_cfg to match the 86xx user's manual and other Freescale architectures Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include')
-rw-r--r--include/asm-ppc/immap_86xx.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h
index a839834..fdfc654 100644
--- a/include/asm-ppc/immap_86xx.h
+++ b/include/asm-ppc/immap_86xx.h
@@ -114,9 +114,9 @@ typedef struct ccsr_ddr {
uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
- uint sdram_cfg_1; /* 0x2110 - DDR SDRAM Control Configuration 1 */
+ uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration 1 */
uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */
- uint sdram_mode_1; /* 0x2118 - DDR SDRAM Mode Configuration 1 */
+ uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration 1 */
uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */
uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */
uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */