Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx

4 files changed, 20 insertions, 23 deletions

diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h
index 229a513..002435e 100644
--- a/include/configs/CATcenter.h
+++ b/include/configs/CATcenter.h
@@ -105,6 +105,7 @@
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 
+#define CONFIG_PPC4xx_EMAC
 #undef CONFIG_EXT_PHY
 #define CONFIG_NET_MULTI	1
 
@@ -398,6 +399,7 @@
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
@@ -410,16 +412,6 @@
 					/* last 4 bits of the address	*/
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
-					/* have only 8kB, 16kB is save here	*/
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* ...			*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
 /*
  * Init Memory Controller:
  *
@@ -570,17 +562,6 @@
 #define		DIMM_READ_ADDR 0xAB
 #define		DIMM_WRITE_ADDR 0xAA
 
-#define CPC0_PLLMR0  (CNTRL_DCR_BASE+0x0)  /* PLL mode 0 register		*/
-#define CPC0_BOOT    (CNTRL_DCR_BASE+0x1)  /* Chip Clock Status register	*/
-#define CPC0_CR1     (CNTRL_DCR_BASE+0x2)  /* Chip Control 1 register		*/
-#define CPC0_EPRCSR  (CNTRL_DCR_BASE+0x3)  /* EMAC PHY Rcv Clk Src register	*/
-#define CPC0_PLLMR1  (CNTRL_DCR_BASE+0x4)  /* PLL mode 1 register		*/
-#define CPC0_UCR     (CNTRL_DCR_BASE+0x5)  /* UART Control register		*/
-#define CPC0_SRR     (CNTRL_DCR_BASE+0x6)  /* Soft Reset register		*/
-#define CPC0_JTAGID  (CNTRL_DCR_BASE+0x7)  /* JTAG ID register			*/
-#define CPC0_SPARE   (CNTRL_DCR_BASE+0x8)  /* Spare DCR				*/
-#define CPC0_PCI     (CNTRL_DCR_BASE+0x9)  /* PCI Control register		*/
-
 /* Defines for CPC0_PLLMR1 Register fields */
 #define PLL_ACTIVE		0x80000000
 #define CPC0_PLLMR1_SSCS	0x80000000
diff --git a/include/configs/acadia.h b/include/configs/acadia.h
index bd3388f..8b01c70 100644
--- a/include/configs/acadia.h
+++ b/include/configs/acadia.h
@@ -120,7 +120,13 @@
 #define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #else
-#define	CONFIG_SYS_NO_FLASH		1	/* No NOR on Acadia when NAND-booting	*/
+/*
+ * No NOR-flash on Acadia when NAND-booting. We need to undef the
+ * NOR device-tree fixup code as well, since flash_info is not defined
+ * in this case.
+ */
+#define	CONFIG_SYS_NO_FLASH		1
+#undef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
 #endif
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 871ef45..fd94929 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -79,7 +79,7 @@ void ft_pci_setup(void *blob, bd_t *bd);
 void set_working_fdt_addr(void *addr);
 int fdt_resize(void *blob);
 
-int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size);
+int fdt_fixup_nor_flash_size(void *blob);
 
 void fdt_fixup_mtdparts(void *fdt, void *node_info, int node_info_size);
 void fdt_del_node_and_alias(void *blob, const char *alias);
diff --git a/include/ppc4xx.h b/include/ppc4xx.h
index ee30a4c..5238d04 100644
--- a/include/ppc4xx.h
+++ b/include/ppc4xx.h
@@ -99,6 +99,16 @@
 
 #endif /* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/
 
+/*
+ * Define ns16550 register offset for all PPC4xx SoC's. Some
+ * mostly FPGA based PPC4xx implementations use a different
+ * offset. So let's give them a chance to define their offset
+ * in the board config header.
+ */
+#if !defined(CONFIG_SYS_NS16550_REG_SIZE)
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#endif
+
 #if defined(CONFIG_440)
 #include <ppc440.h>
 #else