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authorStephen Warren <swarren@nvidia.com>2013-02-26 12:28:28 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-03-13 22:24:14 +0100
commitc44bb3a30f5a1332176edce1a91c0e2cf666ee8f (patch)
tree8d2728b07687ed98d87976b4f300059770258de1 /include
parent0678587fb6f517d40c461f1d43fe7a6ff430f168 (diff)
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ARM: tegra: enable some CPU errata workarounds
Tegra20 has a Cortex A9 r1p1, and Tegra30 has a Cortex A9 r2p9. As such, some CPU errata exist, and must be worked around. These must be worked around in the bootloader, since in general, the kernel (especially a multi-platform kernel) needs to support being launched in non-secure mode (normal world), and hence may not be able to write to the CP15 register to enable these workarounds. Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'include')
-rw-r--r--include/configs/tegra20-common.h6
-rw-r--r--include/configs/tegra30-common.h6
2 files changed, 12 insertions, 0 deletions
diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
index 33e5f52..186e023 100644
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra20-common.h
@@ -26,6 +26,12 @@
#include "tegra-common.h"
/*
+ * Errata configuration
+ */
+#define CONFIG_ARM_ERRATA_742230
+#define CONFIG_ARM_ERRATA_751472
+
+/*
* NS16550 Configuration
*/
#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h
index 04517e1..f6c07c6 100644
--- a/include/configs/tegra30-common.h
+++ b/include/configs/tegra30-common.h
@@ -26,6 +26,12 @@
#include "tegra-common.h"
/*
+ * Errata configuration
+ */
+#define CONFIG_ARM_ERRATA_743622
+#define CONFIG_ARM_ERRATA_751472
+
+/*
* NS16550 Configuration
*/
#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */