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authorYork Sun <yorksun@freescale.com>2014-03-28 15:07:27 -0700
committerYork Sun <yorksun@freescale.com>2014-04-22 17:58:48 -0700
commitc3678b0937a0543280067fd8e08e6e2d278d90e2 (patch)
tree166623230c6ec5a618c800b4cbc52d56e101984b /include
parent22cbf964345e502afa29087c343db309831ab111 (diff)
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powerpc/mpc85xx: Add workaround for erratum A007212
Erratum A007212 for DDR is about a runaway condition for DDR PLL oscilliator. Please refer to erratum document for detail. For this workaround to work, DDR PLL needs to be disabled in RCW. However, u-boot needs to know the expected PLL ratio. We put the ratio in a reserved field RCW[18:23]. U-boot will skip this workaround if DDR PLL ratio is set, or the reserved field is not set. Workaround for erratum A007212 applies to selected versions of B4/T4 SoCs. It is safe to apply the workaround to all versions. It is helpful for upgrading SoC without changing u-boot. In case DDR PLL is disabled by RCW (part of the erratum workaround), we need this u-boot workround to bring up DDR clock. Signed-off-by: York Sun <yorksun@freescale.com>
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