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author <m8@hekate.semihalf.com>2005-08-11 15:56:59 +0200
committer <m8@hekate.semihalf.com>2005-08-11 15:56:59 +0200
commit5a27f84855f3db8a6317389c034f8f507444185f (patch)
treec3fb532152ac9dc503fa37b473b067b4cb702746 /include
parentadac376ef2fc3d44764dd32c205cb4ad03dfbe9e (diff)
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O2DNT FRAM write delay disabled.
Diffstat (limited to 'include')
-rw-r--r--include/configs/o2dnt.h15
1 files changed, 13 insertions, 2 deletions
diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h
index 6d388f3..12a732d 100644
--- a/include/configs/o2dnt.h
+++ b/include/configs/o2dnt.h
@@ -150,12 +150,23 @@
#define CFG_I2C_SLAVE 0x7F
/*
- * EEPROM configuration
+ * EEPROM configuration:
+ *
+ * O2DNT board is equiped with Ramtron FRAM device FM24CL16
+ * 16 Kib Ferroelectric Nonvolatile serial RAM memory
+ * organized as 2048 x 8 bits and addressable as eight I2C devices
+ * 0x50 ... 0x57 each 256 bytes in size
+ *
*/
#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_BITS 3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
+/*
+ * There is no write delay with FRAM, write operations are performed at bus
+ * speed. Thus, no status polling or write delay is needed.
+ */
+/*#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70*/
+
/*
* Flash configuration