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authorKumar Gala <galak@kernel.crashing.org>2008-04-29 10:27:08 -0500
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2008-04-29 11:44:29 -0500
commit45239cf4152109caa925145ccd433529902df887 (patch)
treecbeedce4c8e289bf2da8f6a4afa3677f57578ccd /include
parentef7d30b14394e4c4a153118f5845760cadada02a (diff)
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85xx/86xx: Rename ext_refrec to timing_cfg_3 to match docs
All the 85xx and 86xx UM describe the register as timing_cfg_3 not as ext_refrec. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include')
-rw-r--r--include/asm-ppc/immap_85xx.h2
-rw-r--r--include/asm-ppc/immap_86xx.h2
-rw-r--r--include/configs/MPC8610HPCD.h2
-rw-r--r--include/configs/sbc8641d.h2
4 files changed, 4 insertions, 4 deletions
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index da97cd4..2d07625 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -92,7 +92,7 @@ typedef struct ccsr_ddr {
uint cs2_config_2; /* 0x20c8 - DDR Chip Select Configuration 2 */
uint cs3_config_2; /* 0x20cc - DDR Chip Select Configuration 2 */
char res5[48];
- uint ext_refrec; /* 0x2100 - DDR SDRAM Extended Refresh Recovery */
+ uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */
uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h
index 4287cf4..0b78c94 100644
--- a/include/asm-ppc/immap_86xx.h
+++ b/include/asm-ppc/immap_86xx.h
@@ -109,7 +109,7 @@ typedef struct ccsr_ddr {
uint cs4_config; /* 0x2090 - DDR Chip Select Configuration */
uint cs5_config; /* 0x2094 - DDR Chip Select Configuration */
char res7[104];
- uint ext_refrec; /* 0x2100 - DDR SDRAM extended refresh recovery */
+ uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */
uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 9e70198..585411c 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -114,7 +114,7 @@
#if 0 /* TODO */
#define CFG_DDR_CS0_BNDS 0x0000000F
#define CFG_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
-#define CFG_DDR_EXT_REFRESH 0x00000000
+#define CFG_DDR_TIMING_3 0x00000000
#define CFG_DDR_TIMING_0 0x00260802
#define CFG_DDR_TIMING_1 0x3935d322
#define CFG_DDR_TIMING_2 0x14904cc8
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 18cedff..20da73e 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -136,7 +136,7 @@
#define CFG_DDR_CS1_CONFIG 0x00000000
#define CFG_DDR_CS2_CONFIG 0x00000000
#define CFG_DDR_CS3_CONFIG 0x00000000
- #define CFG_DDR_EXT_REFRESH 0x00000000
+ #define CFG_DDR_TIMING_3 0x00000000
#define CFG_DDR_TIMING_0 0x00220802
#define CFG_DDR_TIMING_1 0x38377322
#define CFG_DDR_TIMING_2 0x002040c7