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authorHaiying Wang <Haiying.Wang@freescale.com>2008-09-24 11:42:12 -0500
committerWolfgang Denk <wd@denx.de>2008-10-18 21:54:00 +0200
commit41410eee472b0f42e03a77f961bbc55ef58f3c01 (patch)
tree696428e03aefc4030f0623d278f2d21b59f36f16 /include
parent69710092172409cfcc43b84cd71287f428a4e319 (diff)
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Change UEC PHY interface to RGMII on MPC8568MDS
Change UEC phy interface from GMII to RGMII on MPC8568MDS board Because on MPC8568MDS, GMII interface is only recommended for 1000Mbps speed, but RGMII interface can work at 10/100/1000Mbps, and RGMII interface works more stable. Now both UEC1 and UEC2 can work properly under u-boot. It is also in consistent with the kernel setting for 8568 UEC phy interface. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Diffstat (limited to 'include')
-rw-r--r--include/configs/MPC8568MDS.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 80697a5..076137a 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -362,7 +362,7 @@ extern unsigned long get_clock_freq(void);
#define CFG_UEC1_TX_CLK QE_CLK16
#define CFG_UEC1_ETH_TYPE GIGA_ETH
#define CFG_UEC1_PHY_ADDR 7
-#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII
+#define CFG_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID
#endif
#define CONFIG_UEC_ETH2 /* GETH2 */
@@ -373,7 +373,7 @@ extern unsigned long get_clock_freq(void);
#define CFG_UEC2_TX_CLK QE_CLK16
#define CFG_UEC2_ETH_TYPE GIGA_ETH
#define CFG_UEC2_PHY_ADDR 1
-#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII
+#define CFG_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID
#endif
#endif /* CONFIG_QE */