summaryrefslogtreecommitdiff
path: root/include
diff options
context:
space:
mode:
authorAubrey.Li <aubrey.adi@gmail.com>2007-03-09 13:38:44 +0800
committerAubrey.Li <aubrey.adi@gmail.com>2007-03-09 13:38:44 +0800
commit3f0606ad0b5639f7f22848fe5b4574e754d0470f (patch)
tree3cb4fd316134b6a176607ad61739720aeb971a5a /include
parenteb92f613556800f7483666db09d9a237ad911d4a (diff)
downloadu-boot-imx-3f0606ad0b5639f7f22848fe5b4574e754d0470f.zip
u-boot-imx-3f0606ad0b5639f7f22848fe5b4574e754d0470f.tar.gz
u-boot-imx-3f0606ad0b5639f7f22848fe5b4574e754d0470f.tar.bz2
[Blackfin]PATCH-1/2]: Remove obsolete blackfin port and add bf533 platform support
Diffstat (limited to 'include')
-rw-r--r--include/asm-blackfin/arch-bf533/anomaly.h172
-rw-r--r--include/asm-blackfin/arch-bf533/bf533_serial.h (renamed from include/asm-blackfin/cpu/bf533_serial.h)1
-rw-r--r--include/asm-blackfin/arch-bf533/bf5xx_rtc.h (renamed from include/asm-blackfin/cpu/bf533_rtc.h)0
-rw-r--r--include/asm-blackfin/arch-bf533/cdefBF531.h (renamed from include/asm-blackfin/cpu/cdefBF531.h)2
-rw-r--r--include/asm-blackfin/arch-bf533/cdefBF532.h (renamed from include/asm-blackfin/cpu/cdefBF532.h)4
-rw-r--r--include/asm-blackfin/arch-bf533/cdefBF533.h (renamed from include/asm-blackfin/cpu/cdefBF533.h)2
-rw-r--r--include/asm-blackfin/arch-bf533/cplbtab.h482
-rw-r--r--include/asm-blackfin/arch-bf533/defBF531.h (renamed from include/asm-blackfin/cpu/defBF531.h)0
-rw-r--r--include/asm-blackfin/arch-bf533/defBF532.h (renamed from include/asm-blackfin/cpu/defBF532.h)146
-rw-r--r--include/asm-blackfin/arch-bf533/defBF533.h (renamed from include/asm-blackfin/cpu/defBF533.h)0
-rw-r--r--include/asm-blackfin/arch-bf533/defBF533_extn.h (renamed from include/asm-blackfin/cpu/defBF533_extn.h)5
-rw-r--r--include/asm-blackfin/arch-bf533/irq.h (renamed from include/asm-blackfin/cpu/bf533_irq.h)0
-rw-r--r--include/asm-blackfin/arch-common/bf53x_rtc.h46
-rw-r--r--include/asm-blackfin/arch-common/cdefBF5xx.h40
-rw-r--r--include/asm-blackfin/arch-common/cdef_LPBlackfin.h (renamed from include/asm-blackfin/cpu/cdef_LPBlackfin.h)70
-rw-r--r--include/asm-blackfin/arch-common/def_LPBlackfin.h (renamed from include/asm-blackfin/cpu/def_LPBlackfin.h)4
-rw-r--r--include/asm-blackfin/bitops.h42
-rw-r--r--include/asm-blackfin/blackfin.h20
-rw-r--r--include/asm-blackfin/cplb.h38
-rw-r--r--include/asm-blackfin/cplbtab.h572
-rw-r--r--include/asm-blackfin/cpu/cdefBF53x.h32
-rw-r--r--include/asm-blackfin/delay.h6
-rw-r--r--include/asm-blackfin/entry.h6
-rw-r--r--include/asm-blackfin/global_data.h13
-rw-r--r--include/asm-blackfin/hw_irq.h10
-rw-r--r--include/asm-blackfin/io-kernel.h9
-rw-r--r--include/asm-blackfin/io.h15
-rw-r--r--include/asm-blackfin/irq.h6
-rw-r--r--include/asm-blackfin/machdep.h3
-rw-r--r--include/asm-blackfin/mem_init.h38
-rw-r--r--include/asm-blackfin/page.h5
-rw-r--r--include/asm-blackfin/processor.h3
-rw-r--r--include/asm-blackfin/setup.h3
-rw-r--r--include/asm-blackfin/string.h9
-rw-r--r--include/asm-blackfin/u-boot.h2
-rw-r--r--include/asm-blackfin/uaccess.h10
-rw-r--r--include/configs/bf533-ezkit.h228
-rw-r--r--include/configs/bf533-stamp.h475
-rw-r--r--include/configs/ezkit533.h188
-rw-r--r--include/configs/stamp.h333
40 files changed, 1707 insertions, 1333 deletions
diff --git a/include/asm-blackfin/arch-bf533/anomaly.h b/include/asm-blackfin/arch-bf533/anomaly.h
new file mode 100644
index 0000000..0e5f919
--- /dev/null
+++ b/include/asm-blackfin/arch-bf533/anomaly.h
@@ -0,0 +1,172 @@
+/*
+ * File: include/asm-blackfin/arch-bf533/anomaly.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ *
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+/* This file shoule be up to date with:
+ * - Revision U, May 17, 2006; ADSP-BF533 Blackfin Processor Anomaly List
+ * - Revision Y, May 17, 2006; ADSP-BF532 Blackfin Processor Anomaly List
+ * - Revision T, May 17, 2006; ADSP-BF531 Blackfin Processor Anomaly List
+ */
+
+#ifndef _MACH_ANOMALY_H_
+#define _MACH_ANOMALY_H_
+
+/* We do not support 0.1 or 0.2 silicon - sorry */
+#if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2))
+#error Kernel will not work on BF533 Version 0.1 or 0.2
+#endif
+
+/* Issues that are common to 0.5, 0.4, and 0.3 silicon */
+#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
+#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
+ slot1 and store of a P register in slot 2 is not
+ supported */
+#define ANOMALY_05000105 /* Watchpoint Status Register (WPSTAT) bits are set on
+ every corresponding match */
+#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
+ Channel DMA stops */
+#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
+ registers. */
+#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
+ upper bits*/
+#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */
+#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
+ syncs */
+#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not
+ functional */
+#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable
+ state */
+#define ANOMALY_05000229 /* SPI Slave Boot Mode modifies registers */
+#define ANOMALY_05000272 /* Certain data cache write through modes fail for
+ VDDint <=0.9V */
+#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
+#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
+ an edge is detected may clear interrupt */
+#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
+ DMA system instability */
+#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
+ not restored */
+#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
+ control */
+#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
+ killed in a particular stage*/
+#endif
+
+/* These issues only occur on 0.3 or 0.4 BF533 */
+#if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
+#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not
+ updated at the same time. */
+#define ANOMALY_05000158 /* Boot fails when data cache enabled: Data from a Data
+ Cache Fill can be corrupted after or during
+ Instruction DMA if certain core stalls exist */
+#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General
+ Purpose TX or RX modes */
+#define ANOMALY_05000198 /* Failing SYSTEM MMR accesses when stalled by
+ preceding memory read */
+#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during
+ inactive channels in certain conditions */
+#define ANOMALY_05000202 /* Possible infinite stall with specific dual dag
+ situation */
+#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */
+#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */
+#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect
+ data*/
+#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate
+ Differences in certain Conditions */
+#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */
+#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to
+ hardware reset */
+#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or
+ IDLE around a Change of Control causes
+ unpredictable results */
+#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the
+ shadow of a conditional branch */
+#define ANOMALY_05000246 /* Data CPLB's should prevent spurious hardware
+ errors */
+#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
+#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
+ interrupt not functional */
+#define ANOMALY_05000257 /* An interrupt or exception during short Hardware
+ loops may cause the instruction fetch unit to
+ malfunction */
+#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
+ the ICPLB Data registers differ */
+#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
+#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
+#define ANOMALY_05000262 /* Stores to data cache may be lost */
+#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
+#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
+ instruction will cause an infinite stall in the
+ second to last instruction in a hardware loop */
+#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
+ SPORT external receive and transmit clocks. */
+#define ANOMALY_05000269 /* High I/O activity causes the output voltage of the
+ internal voltage regulator (VDDint) to increase. */
+#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
+ internal voltage regulator (VDDint) to decrease */
+#endif
+
+/* These issues are only on 0.4 silicon */
+#if (defined(CONFIG_BF_REV_0_4))
+#define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */
+#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
+ (TDM) */
+#endif
+
+/* These issues are only on 0.3 silicon */
+#if defined(CONFIG_BF_REV_0_3)
+#define ANOMALY_05000183 /* Timer Pin limitations for PPI TX Modes with
+ External Frame Syncs */
+#define ANOMALY_05000189 /* False Protection Exceptions caused by Speculative
+ Instruction or Data Fetches, or by Fetches at the
+ boundary of reserved memory space */
+#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs
+ when polarity setting is changed */
+#define ANOMALY_05000194 /* Sport Restarting in specific modes may cause data
+ corruption */
+#define ANOMALY_05000199 /* DMA current address shows wrong value during carry
+ fix */
+#define ANOMALY_05000201 /* Receive frame sync not ignored during active
+ frames in sport MCM */
+#define ANOMALY_05000203 /* Specific sequence that can cause DMA error or DMA
+ stopping */
+#if defined(CONFIG_BF533)
+#define ANOMALY_05000204 /* Incorrect data read with write-through cache and
+ allocate cache lines on reads only mode */
+#endif /* CONFIG_BF533 */
+#define ANOMALY_05000207 /* Recovery from "brown-out" condition */
+#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain
+ instructions */
+#define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame
+ Sync Transmit Mode */
+#define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */
+#endif
+
+#endif /* _MACH_ANOMALY_H_ */
diff --git a/include/asm-blackfin/cpu/bf533_serial.h b/include/asm-blackfin/arch-bf533/bf533_serial.h
index d5e162a..ce58863 100644
--- a/include/asm-blackfin/cpu/bf533_serial.h
+++ b/include/asm-blackfin/arch-bf533/bf533_serial.h
@@ -22,7 +22,6 @@
* MA 02111-1307 USA
*/
-
#ifndef _BF533_SERIAL_H_
#define _BF533_SERIAL_H_
diff --git a/include/asm-blackfin/cpu/bf533_rtc.h b/include/asm-blackfin/arch-bf533/bf5xx_rtc.h
index bc09922..bc09922 100644
--- a/include/asm-blackfin/cpu/bf533_rtc.h
+++ b/include/asm-blackfin/arch-bf533/bf5xx_rtc.h
diff --git a/include/asm-blackfin/cpu/cdefBF531.h b/include/asm-blackfin/arch-bf533/cdefBF531.h
index 68d841d..3877db8 100644
--- a/include/asm-blackfin/cpu/cdefBF531.h
+++ b/include/asm-blackfin/arch-bf533/cdefBF531.h
@@ -19,6 +19,6 @@
#ifndef _CDEFBF531_H
#define _CDEFBF531_H
-#include <cdefBF532.h>
+#include <asm/arch-bf533/cdefBF532.h>
#endif /* _CDEFBF531_H */
diff --git a/include/asm-blackfin/cpu/cdefBF532.h b/include/asm-blackfin/arch-bf533/cdefBF532.h
index a4d422f..bca1ed1 100644
--- a/include/asm-blackfin/cpu/cdefBF532.h
+++ b/include/asm-blackfin/arch-bf533/cdefBF532.h
@@ -26,10 +26,10 @@
*/
/* include all Core registers and bit definitions */
-#include <asm/cpu/defBF532.h>
+#include <asm/arch-bf533/defBF532.h>
/* include core specific register pointer definitions */
-#include <asm/cpu/cdef_LPBlackfin.h>
+#include <asm/arch-common/cdef_LPBlackfin.h>
/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
#define pPLL_CTL ((volatile unsigned short *)PLL_CTL)
diff --git a/include/asm-blackfin/cpu/cdefBF533.h b/include/asm-blackfin/arch-bf533/cdefBF533.h
index 8c751e6..c72bac9 100644
--- a/include/asm-blackfin/cpu/cdefBF533.h
+++ b/include/asm-blackfin/arch-bf533/cdefBF533.h
@@ -19,6 +19,6 @@
#ifndef _CDEFBF533_H
#define _CDEFBF533_H
-#include <asm/cpu/cdefBF532.h>
+#include <asm/arch-bf533/cdefBF532.h>
#endif /* _CDEFBF533_H */
diff --git a/include/asm-blackfin/arch-bf533/cplbtab.h b/include/asm-blackfin/arch-bf533/cplbtab.h
new file mode 100644
index 0000000..89f0325
--- /dev/null
+++ b/include/asm-blackfin/arch-bf533/cplbtab.h
@@ -0,0 +1,482 @@
+/*This file is subject to the terms and conditions of the GNU General Public
+ * License.
+ *
+ * Blackfin BF533/2.6 support : LG Soft India
+ * Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd
+ * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's
+ * shouldn't be victimized. cplbmgr.S search logic is corrected
+ * to findout the appropriate victim.
+ * 2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC
+ * : LG Soft India
+ */
+#include <config.h>
+
+#ifndef __ARCH_BFINNOMMU_CPLBTAB_H
+#define __ARCH_BFINNOMMU_CPLBTAB_H
+
+/*************************************************************************
+ * ICPLB TABLE
+ *************************************************************************/
+
+.data
+/* This table is configurable */
+ .align 4;
+
+/* Data Attibutes*/
+
+#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
+#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
+
+/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
+
+#define ANOMALY_05000158 0x200
+#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
+#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
+#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
+
+#else /*Write Through */
+#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
+#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
+#endif
+
+.align 4;
+.global _ipdt_table _ipdt_table:.byte4 0x00000000;
+.byte4(SDRAM_IKERNEL); /*SDRAM_Page0 */
+.byte4 0x00400000;
+.byte4(SDRAM_IKERNEL); /*SDRAM_Page1 */
+.byte4 0x00800000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page2 */
+.byte4 0x00C00000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page3 */
+.byte4 0x01000000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page4 */
+.byte4 0x01400000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page5 */
+.byte4 0x01800000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page6 */
+.byte4 0x01C00000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page7 */
+#ifndef CONFIG_EZKIT /*STAMP Memory regions */
+.byte4 0x02000000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page8 */
+.byte4 0x02400000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page9 */
+.byte4 0x02800000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page10 */
+.byte4 0x02C00000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page11 */
+.byte4 0x03000000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page12 */
+.byte4 0x03400000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page13 */
+.byte4 0x03800000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page14 */
+.byte4 0x03C00000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page15 */
+#endif
+.byte4 0x20000000;
+.byte4(SDRAM_EBIU); /* Async Memory Bank 2 (Secnd) */
+
+#ifdef CONFIG_STAMP
+.byte4 0x04000000;
+.byte4(SDRAM_IGENERIC);
+.byte4 0x04400000;
+.byte4(SDRAM_IGENERIC);
+.byte4 0x04800000;
+.byte4(SDRAM_IGENERIC);
+.byte4 0x04C00000;
+.byte4(SDRAM_IGENERIC);
+.byte4 0x05000000;
+.byte4(SDRAM_IGENERIC);
+.byte4 0x05400000;
+.byte4(SDRAM_IGENERIC);
+.byte4 0x05800000;
+.byte4(SDRAM_IGENERIC);
+.byte4 0x05C00000;
+.byte4(SDRAM_IGENERIC);
+.byte4 0x06000000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page25 */
+.byte4 0x06400000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page26 */
+.byte4 0x06800000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page27 */
+.byte4 0x06C00000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page28 */
+.byte4 0x07000000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page29 */
+.byte4 0x07400000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page30 */
+.byte4 0x07800000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page31 */
+.byte4 0x07C00000;
+.byte4(SDRAM_IKERNEL); /*SDRAM_Page32 */
+#endif
+.byte4 0xffffffff; /* end of section - termination */
+
+/**********************************************************************
+ * PAGE DESCRIPTOR TABLE
+ *
+ **********************************************************************/
+
+/* Till here we are discussing about the static memory management model.
+ * However, the operating envoronments commonly define more CPLB
+ * descriptors to cover the entire addressable memory than will fit into
+ * the available on-chip 16 CPLB MMRs. When this happens, the below table
+ * will be used which will hold all the potentially required CPLB descriptors
+ *
+ * This is how Page descriptor Table is implemented in uClinux/Blackfin.
+ */
+.global _dpdt_table _dpdt_table:.byte4 0x00000000;
+.byte4(SDRAM_DKERNEL); /*SDRAM_Page0 */
+.byte4 0x00400000;
+.byte4(SDRAM_DKERNEL); /*SDRAM_Page1 */
+.byte4 0x00800000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page2 */
+.byte4 0x00C00000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page3 */
+.byte4 0x01000000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page4 */
+.byte4 0x01400000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page5 */
+.byte4 0x01800000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page6 */
+.byte4 0x01C00000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page7 */
+
+#ifndef CONFIG_EZKIT
+.byte4 0x02000000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page8 */
+.byte4 0x02400000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page9 */
+.byte4 0x02800000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page10 */
+.byte4 0x02C00000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page11 */
+.byte4 0x03000000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page12 */
+.byte4 0x03400000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page13 */
+.byte4 0x03800000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page14 */
+.byte4 0x03C00000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page15 */
+#endif
+
+#ifdef CONFIG_STAMP
+.byte4 0x04000000;
+.byte4(SDRAM_DGENERIC);
+.byte4 0x04400000;
+.byte4(SDRAM_DGENERIC);
+.byte4 0x04800000;
+.byte4(SDRAM_DGENERIC);
+.byte4 0x04C00000;
+.byte4(SDRAM_DGENERIC);
+.byte4 0x05000000;
+.byte4(SDRAM_DGENERIC);
+.byte4 0x05400000;
+.byte4(SDRAM_DGENERIC);
+.byte4 0x05800000;
+.byte4(SDRAM_DGENERIC);
+.byte4 0x05C00000;
+.byte4(SDRAM_DGENERIC);
+.byte4 0x06000000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page25 */
+.byte4 0x06400000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page26 */
+.byte4 0x06800000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page27 */
+.byte4 0x06C00000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page28 */
+.byte4 0x07000000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page29 */
+.byte4 0x07400000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page30 */
+.byte4 0x07800000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page31 */
+.byte4 0x07C00000;
+.byte4(SDRAM_DKERNEL); /*SDRAM_Page32 */
+#endif
+
+.byte4 0x20000000;
+.byte4(SDRAM_EBIU); /* Async Memory Bank 0 (Prim A) */
+
+#if (BFIN_CPU == ADSP_BF533)
+.byte4 0xFF800000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF801000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF802000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF803000;
+.byte4(L1_DMEMORY);
+#endif
+.byte4 0xFF804000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF805000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF806000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF807000;
+.byte4(L1_DMEMORY);
+#if (BFIN_CPU == ADSP_BF533)
+.byte4 0xFF900000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF901000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF902000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF903000;
+.byte4(L1_DMEMORY);
+#endif
+#if ((BFIN_CPU == ADSP_BF532) || (BFIN_CPU == ADSP_BF533))
+.byte4 0xFF904000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF905000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF906000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF907000;
+.byte4(L1_DMEMORY);
+#endif
+.byte4 0xFFB00000;
+.byte4(L1_DMEMORY);
+
+.byte4 0xffffffff; /*end of section - termination */
+
+#ifdef CONFIG_CPLB_INFO
+.global _ipdt_swapcount_table; /* swapin count first, then swapout count */
+_ipdt_swapcount_table:
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 10 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 20 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 30 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 40 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 50 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 60 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 70 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 80 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 90 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 100 */
+
+.global _dpdt_swapcount_table; /* swapin count first, then swapout count */
+_dpdt_swapcount_table:
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 10 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 20 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 30 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 40 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 50 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 60 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 70 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 80 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 80 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 100 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 110 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 120 */
+#endif
+
+#endif /*__ARCH_BFINNOMMU_CPLBTAB_H*/
diff --git a/include/asm-blackfin/cpu/defBF531.h b/include/asm-blackfin/arch-bf533/defBF531.h
index 6c7cd5a..6c7cd5a 100644
--- a/include/asm-blackfin/cpu/defBF531.h
+++ b/include/asm-blackfin/arch-bf533/defBF531.h
diff --git a/include/asm-blackfin/cpu/defBF532.h b/include/asm-blackfin/arch-bf533/defBF532.h
index 26a5fe6..312ff2b 100644
--- a/include/asm-blackfin/cpu/defBF532.h
+++ b/include/asm-blackfin/arch-bf533/defBF532.h
@@ -28,7 +28,7 @@
*/
/* include all Core registers and bit definitions */
-#include <asm/cpu/def_LPBlackfin.h>
+#include <asm/arch-common/def_LPBlackfin.h>
/* Helper macros
* usage:
@@ -51,7 +51,7 @@
#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
-#define CHIPID 0xFFC00014 /* Chip ID register (32-bit) */
+#define CHIPID 0xFFC00014 /* Chip ID register (32-bit) */
#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
#define SYSCR 0xFFC00104 /* System Configuration register */
@@ -88,7 +88,7 @@
#define UART_LCR 0xFFC0040C /* Line Control Register */
#define UART_MCR 0xFFC00410 /* Modem Control Register */
#define UART_LSR 0xFFC00414 /* Line Status Register */
-/* #define UART_MSR 0xFFC00418 */ /* Modem Status Register (UNUSED in ADSP-BF532) */
+/* #define UART_MSR 0xFFC00418 *//* Modem Status Register (UNUSED in ADSP-BF532) */
#define UART_SCR 0xFFC0041C /* SCR Scratch Register */
#define UART_GCTL 0xFFC00424 /* Global Control Register */
@@ -405,7 +405,7 @@
#define BYPASS 0x00000100 /* Bypass the PLL */
/* PLL_DIV Masks */
-#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
+#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */
#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */
@@ -420,7 +420,7 @@
*/
/* SIC_IAR0 Masks */
-#define P0_IVG(x) ((x)-7) /* Peripheral #0 assigned IVG #x */
+#define P0_IVG(x) ((x)-7) /* Peripheral #0 assigned IVG #x */
#define P1_IVG(x) ((x)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
#define P2_IVG(x) ((x)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
#define P3_IVG(x) ((x)-7) << 0xC /* Peripheral #3 assigned IVG #x */
@@ -430,7 +430,7 @@
#define P7_IVG(x) ((x)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
/* SIC_IAR1 Masks */
-#define P8_IVG(x) ((x)-7) /* Peripheral #8 assigned IVG #x */
+#define P8_IVG(x) ((x)-7) /* Peripheral #8 assigned IVG #x */
#define P9_IVG(x) ((x)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
#define P10_IVG(x) ((x)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
#define P11_IVG(x) ((x)-7) << 0xC /* Peripheral #11 assigned IVG #x */
@@ -440,7 +440,7 @@
#define P15_IVG(x) ((x)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
/* SIC_IAR2 Masks */
-#define P16_IVG(x) ((x)-7) /* Peripheral #16 assigned IVG #x */
+#define P16_IVG(x) ((x)-7) /* Peripheral #16 assigned IVG #x */
#define P17_IVG(x) ((x)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
#define P18_IVG(x) ((x)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
#define P19_IVG(x) ((x)-7) << 0xC /* Peripheral #19 assigned IVG #x */
@@ -486,25 +486,25 @@
#define RTDAY 0xFFFE0000 /* Real-Time Clock Days */
/* RTC_ICTL register */
-#define SWIE 0x0001 /* Stopwatch Interrupt Enable */
-#define AIE 0x0002 /* Alarm Interrupt Enable */
-#define SIE 0x0004 /* Seconds (1 Hz) Interrupt Enable */
-#define MIE 0x0008 /* Minutes Interrupt Enable */
-#define HIE 0x0010 /* Hours Interrupt Enable */
-#define DIE 0x0020 /* 24 Hours (Days) Interrupt Enable */
-#define DAIE 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
-#define WCIE 0x8000 /* Write Complete Interrupt Enable */
+#define SWIE 0x0001 /* Stopwatch Interrupt Enable */
+#define AIE 0x0002 /* Alarm Interrupt Enable */
+#define SIE 0x0004 /* Seconds (1 Hz) Interrupt Enable */
+#define MIE 0x0008 /* Minutes Interrupt Enable */
+#define HIE 0x0010 /* Hours Interrupt Enable */
+#define DIE 0x0020 /* 24 Hours (Days) Interrupt Enable */
+#define DAIE 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
+#define WCIE 0x8000 /* Write Complete Interrupt Enable */
/* RTC_ISTAT register */
-#define SWEF 0x0001 /* Stopwatch Event Flag */
-#define AEF 0x0002 /* Alarm Event Flag */
-#define SEF 0x0004 /* Seconds (1 Hz) Event Flag */
-#define MEF 0x0008 /* Minutes Event Flag */
-#define HEF 0x0010 /* Hours Event Flag */
-#define DEF 0x0020 /* 24 Hours (Days) Event Flag */
-#define DAEF 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Event Flag */
-#define WPS 0x4000 /* Write Pending Status (RO) */
-#define WCOM 0x8000 /* Write Complete */
+#define SWEF 0x0001 /* Stopwatch Event Flag */
+#define AEF 0x0002 /* Alarm Event Flag */
+#define SEF 0x0004 /* Seconds (1 Hz) Event Flag */
+#define MEF 0x0008 /* Minutes Event Flag */
+#define HEF 0x0010 /* Hours Event Flag */
+#define DEF 0x0020 /* 24 Hours (Days) Event Flag */
+#define DAEF 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Event Flag */
+#define WPS 0x4000 /* Write Pending Status (RO) */
+#define WCOM 0x8000 /* Write Complete */
/* RTC_FAST Mask (RTC_PREN Mask) */
#define ENABLE_PRESCALE 0x00000001 /* Enable prescaler so RTC runs at 1 Hz */
@@ -588,50 +588,50 @@
* SERIAL PORT MASKS
*/
/* SPORTx_TCR1 Masks */
-#define TSPEN 0x0001 /* TX enable */
-#define ITCLK 0x0002 /* Internal TX Clock Select */
-#define TDTYPE 0x000C /* TX Data Formatting Select */
-#define TLSBIT 0x0010 /* TX Bit Order */
-#define ITFS 0x0200 /* Internal TX Frame Sync Select */
-#define TFSR 0x0400 /* TX Frame Sync Required Select */
-#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
-#define LTFS 0x1000 /* Low TX Frame Sync Select */
-#define LATFS 0x2000 /* Late TX Frame Sync Select */
-#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
+#define TSPEN 0x0001 /* TX enable */
+#define ITCLK 0x0002 /* Internal TX Clock Select */
+#define TDTYPE 0x000C /* TX Data Formatting Select */
+#define TLSBIT 0x0010 /* TX Bit Order */
+#define ITFS 0x0200 /* Internal TX Frame Sync Select */
+#define TFSR 0x0400 /* TX Frame Sync Required Select */
+#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
+#define LTFS 0x1000 /* Low TX Frame Sync Select */
+#define LATFS 0x2000 /* Late TX Frame Sync Select */
+#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
/* SPORTx_TCR2 Masks */
-#define SLEN 0x001F /*TX Word Length */
-#define TXSE 0x0100 /*TX Secondary Enable */
-#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
-#define TRFST 0x0400 /*TX Right-First Data Order */
+#define SLEN 0x001F /*TX Word Length */
+#define TXSE 0x0100 /*TX Secondary Enable */
+#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
+#define TRFST 0x0400 /*TX Right-First Data Order */
/* SPORTx_RCR1 Masks */
-#define RSPEN 0x0001 /* RX enable */
-#define IRCLK 0x0002 /* Internal RX Clock Select */
-#define RDTYPE 0x000C /* RX Data Formatting Select */
-#define RULAW 0x0008 /* u-Law enable */
-#define RALAW 0x000C /* A-Law enable */
-#define RLSBIT 0x0010 /* RX Bit Order */
-#define IRFS 0x0200 /* Internal RX Frame Sync Select */
-#define RFSR 0x0400 /* RX Frame Sync Required Select */
-#define LRFS 0x1000 /* Low RX Frame Sync Select */
-#define LARFS 0x2000 /* Late RX Frame Sync Select */
-#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
+#define RSPEN 0x0001 /* RX enable */
+#define IRCLK 0x0002 /* Internal RX Clock Select */
+#define RDTYPE 0x000C /* RX Data Formatting Select */
+#define RULAW 0x0008 /* u-Law enable */
+#define RALAW 0x000C /* A-Law enable */
+#define RLSBIT 0x0010 /* RX Bit Order */
+#define IRFS 0x0200 /* Internal RX Frame Sync Select */
+#define RFSR 0x0400 /* RX Frame Sync Required Select */
+#define LRFS 0x1000 /* Low RX Frame Sync Select */
+#define LARFS 0x2000 /* Late RX Frame Sync Select */
+#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
/* SPORTx_RCR2 Masks */
-#define SLEN 0x001F /* RX Word Length */
-#define RXSE 0x0100 /* RX Secondary Enable */
-#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
-#define RRFST 0x0400 /* Right-First Data Order */
+#define SLEN 0x001F /* RX Word Length */
+#define RXSE 0x0100 /* RX Secondary Enable */
+#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
+#define RRFST 0x0400 /* Right-First Data Order */
/* SPORTx_STAT Masks */
-#define RXNE 0x0001 /* RX FIFO Not Empty Status */
-#define RUVF 0x0002 /* RX Underflow Status */
-#define ROVF 0x0004 /* RX Overflow Status */
-#define TXF 0x0008 /* TX FIFO Full Status */
-#define TUVF 0x0010 /* TX Underflow Status */
-#define TOVF 0x0020 /* TX Overflow Status */
-#define TXHRE 0x0040 /* TX Hold Register Empty */
+#define RXNE 0x0001 /* RX FIFO Not Empty Status */
+#define RUVF 0x0002 /* RX Underflow Status */
+#define ROVF 0x0004 /* RX Overflow Status */
+#define TXF 0x0008 /* TX FIFO Full Status */
+#define TUVF 0x0010 /* TX Underflow Status */
+#define TOVF 0x0020 /* TX Overflow Status */
+#define TXHRE 0x0040 /* TX Hold Register Empty */
/* SPORTx_MCMC1 Masks */
#define WSIZE 0x0000F000 /* Multichannel Window Size Field */
@@ -660,7 +660,7 @@
#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */
#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */
#define DLENGTH 0x00003800 /* PPI Data Length */
-#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */
+#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */
#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
#define POL 0x0000C000 /* PPI Signal Polarities */
@@ -689,12 +689,12 @@
#define NDSIZE 0x00000900 /* Next Descriptor Size */
#define FLOW 0x00007000 /* Flow Control */
-#define DMAEN_P 0 /* Channel Enable */
-#define WNR_P 1 /* Channel Direction (W/R*) */
-#define DMA2D_P 4 /* 2D/1D* Mode */
-#define RESTART_P 5 /* Restart */
-#define DI_SEL_P 6 /* Data Interrupt Select */
-#define DI_EN_P 7 /* Data Interrupt Enable */
+#define DMAEN_P 0 /* Channel Enable */
+#define WNR_P 1 /* Channel Direction (W/R*) */
+#define DMA2D_P 4 /* 2D/1D* Mode */
+#define RESTART_P 5 /* Restart */
+#define DI_SEL_P 6 /* Data Interrupt Select */
+#define DI_EN_P 7 /* Data Interrupt Enable */
/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
#define DMA_DONE 0x00000001 /* DMA Done Indicator */
@@ -702,14 +702,14 @@
#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */
#define DMA_RUN 0x00000008 /* DMA Running Indicator */
-#define DMA_DONE_P 0 /* DMA Done Indicator */
-#define DMA_ERR_P 1 /* DMA Error Indicator */
-#define DFETCH_P 2 /* Descriptor Fetch Indicator */
-#define DMA_RUN_P 3 /* DMA Running Indicator */
+#define DMA_DONE_P 0 /* DMA Done Indicator */
+#define DMA_ERR_P 1 /* DMA Error Indicator */
+#define DFETCH_P 2 /* Descriptor Fetch Indicator */
+#define DMA_RUN_P 3 /* DMA Running Indicator */
/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
#define CTYPE 0x00000040 /* DMA Channel Type Indicator */
-#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */
+#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */
#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */
#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */
#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */
@@ -1156,4 +1156,4 @@
#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
#define BGSTAT 0x00000020 /* Bus granted */
-#endif /* _DEF_BF532_H */
+#endif /* _DEF_BF532_H */
diff --git a/include/asm-blackfin/cpu/defBF533.h b/include/asm-blackfin/arch-bf533/defBF533.h
index 90e50af..90e50af 100644
--- a/include/asm-blackfin/cpu/defBF533.h
+++ b/include/asm-blackfin/arch-bf533/defBF533.h
diff --git a/include/asm-blackfin/cpu/defBF533_extn.h b/include/asm-blackfin/arch-bf533/defBF533_extn.h
index a9a1c7c..045e8e4 100644
--- a/include/asm-blackfin/cpu/defBF533_extn.h
+++ b/include/asm-blackfin/arch-bf533/defBF533_extn.h
@@ -19,9 +19,10 @@
#ifndef _DEF_BF533_EXTN_H
#define _DEF_BF533_EXTN_H
-#define OFFSET_( x ) ((x) & 0x0000FFFF) /* define macro for offset */
+/* define macro for offset */
+#define OFFSET_( x ) ((x) & 0x0000FFFF)
/* Delay inserted for PLL transition */
-#define DELAY 0x1000
+#define PLL_DELAY 0x1000
#define L1_ISRAM 0xFFA00000
#define L1_ISRAM_END 0xFFA10000
diff --git a/include/asm-blackfin/cpu/bf533_irq.h b/include/asm-blackfin/arch-bf533/irq.h
index 9c5230d..9c5230d 100644
--- a/include/asm-blackfin/cpu/bf533_irq.h
+++ b/include/asm-blackfin/arch-bf533/irq.h
diff --git a/include/asm-blackfin/arch-common/bf53x_rtc.h b/include/asm-blackfin/arch-common/bf53x_rtc.h
new file mode 100644
index 0000000..bc09922
--- /dev/null
+++ b/include/asm-blackfin/arch-common/bf53x_rtc.h
@@ -0,0 +1,46 @@
+/*
+ * U-boot - bf533_rtc.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BF533_RTC_H_
+#define _BF533_RTC_H_
+
+void rtc_init(void);
+void wait_for_complete(void);
+void rtc_reset(void);
+
+#define MIN_TO_SECS(_x_) (60 * _x_)
+#define HRS_TO_SECS(_x_) (60 * 60 * _x_)
+#define DAYS_TO_SECS(_x_) (24 * 60 * 60 * _x_)
+
+#define NUM_SECS_IN_DAY (24 * 3600)
+#define NUM_SECS_IN_HOUR (3600)
+#define NUM_SECS_IN_MIN (60)
+
+/* Shift values for RTC_STAT register */
+#define DAY_BITS_OFF 17
+#define HOUR_BITS_OFF 12
+#define MIN_BITS_OFF 6
+#define SEC_BITS_OFF 0
+
+#endif
diff --git a/include/asm-blackfin/arch-common/cdefBF5xx.h b/include/asm-blackfin/arch-common/cdefBF5xx.h
new file mode 100644
index 0000000..aec70ce
--- /dev/null
+++ b/include/asm-blackfin/arch-common/cdefBF5xx.h
@@ -0,0 +1,40 @@
+/************************************************************************
+ *
+ * cdefBF53x.h
+ *
+ * (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved.
+ *
+ ************************************************************************/
+
+#ifndef _CDEFBF53x_H
+#define _CDEFBF53x_H
+
+#if defined(__ADSPBF531__)
+ #include <asm/arch-bf533/cdefBF531.h>
+#elif defined(__ADSPBF532__)
+ #include <asm/arch-bf533/cdefBF532.h>
+#elif defined(__ADSPBF533__)
+ #include <asm/arch-bf533/cdefBF533.h>
+ #include <asm/arch-bf533/defBF533_extn.h>
+ #include <asm/arch-bf533/bf533_serial.h>
+#elif defined(__ADSPBF537__)
+ #include <asm/arch-bf537/cdefBF537.h>
+ #include <asm/arch-bf537/defBF537_extn.h>
+ #include <asm/arch-bf537/bf537_serial.h>
+#elif defined(__ADSPBF561__)
+ #include <asm/arch-bf561/cdefBF561.h>
+ #include <asm/arch-bf561/defBF561_extn.h>
+ #include <asm/arch-bf561/bf561_serial.h>
+#elif defined(__ADSPBF535__)
+ #include <asm/cpu/cdefBF5d35.h>
+#elif defined(__AD6532__)
+ #include <asm/cpu/cdefAD6532.h>
+#else
+ #if defined(__ADSPLPBLACKFIN__)
+ #include <asm/arch-bf533/cdefBF532.h>
+ #else
+ #include <asm/arch-bf533/cdefBF535.h>
+ #endif
+#endif
+
+#endif /* _CDEFBF53x_H */
diff --git a/include/asm-blackfin/cpu/cdef_LPBlackfin.h b/include/asm-blackfin/arch-common/cdef_LPBlackfin.h
index e6471cb..f82ccbe 100644
--- a/include/asm-blackfin/cpu/cdef_LPBlackfin.h
+++ b/include/asm-blackfin/arch-common/cdef_LPBlackfin.h
@@ -1,38 +1,27 @@
-/*
- * cdef_LPBlackfin.h
- *
- * This file is subject to the terms and conditions of the GNU Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Non-GPL License also available as part of VisualDSP++
+/************************************************************************
*
- * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
- *
- * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ * cdef_LPBlackfin.h
*
- * This file under source code control, please send bugs or changes to:
- * dsptools.support@analog.com
+ * (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved.
*
- */
+ ************************************************************************/
#ifndef _CDEF_LPBLACKFIN_H
#define _CDEF_LPBLACKFIN_H
-/*
- * #if !defined(__ADSPLPBLACKFIN__)
- * #warning cdef_LPBlackfin.h should only be included for 532 compatible chips.
- * #endif
- */
-#include <asm/cpu/def_LPBlackfin.h>
+#if !defined(__ADSPLPBLACKFIN__)
+#warning cdef_LPBlackfin.h should only be included for 532 compatible chips.
+#endif
+#include <asm/arch-common/def_LPBlackfin.h>
-/* Cache & SRAM Memory */
+// Cache & SRAM Memory
#define pSRAM_BASE_ADDRESS ((volatile void **)SRAM_BASE_ADDRESS)
#define pDMEM_CONTROL ((volatile unsigned long *)DMEM_CONTROL)
#define pDCPLB_STATUS ((volatile unsigned long *)DCPLB_STATUS)
#define pDCPLB_FAULT_ADDR ((volatile void **)DCPLB_FAULT_ADDR)
-
-/* #define MMR_TIMEOUT 0xFFE00010 */ /* Memory-Mapped Register Timeout Register */
+/*
+#define MMR_TIMEOUT 0xFFE00010 // Memory-Mapped Register Timeout Register
+*/
#define pDCPLB_ADDR0 ((volatile void **)DCPLB_ADDR0)
#define pDCPLB_ADDR1 ((volatile void **)DCPLB_ADDR1)
#define pDCPLB_ADDR2 ((volatile void **)DCPLB_ADDR2)
@@ -66,15 +55,15 @@
#define pDCPLB_DATA14 ((volatile unsigned long *)DCPLB_DATA14)
#define pDCPLB_DATA15 ((volatile unsigned long *)DCPLB_DATA15)
#define pDTEST_COMMAND ((volatile unsigned long *)DTEST_COMMAND)
-
-/* #define DTEST_INDEX 0xFFE00304 */ /* Data Test Index Register */
+/*
+#define DTEST_INDEX 0xFFE00304 // Data Test Index Register
+*/
#define pDTEST_DATA0 ((volatile unsigned long *)DTEST_DATA0)
#define pDTEST_DATA1 ((volatile unsigned long *)DTEST_DATA1)
-
/*
- * # define DTEST_DATA2 0xFFE00408 Data Test Data Register
- * #define DTEST_DATA3 0xFFE0040C Data Test Data Register
- */
+#define DTEST_DATA2 0xFFE00408 // Data Test Data Register
+#define DTEST_DATA3 0xFFE0040C // Data Test Data Register
+*/
#define pIMEM_CONTROL ((volatile unsigned long *)IMEM_CONTROL)
#define pICPLB_STATUS ((volatile unsigned long *)ICPLB_STATUS)
#define pICPLB_FAULT_ADDR ((volatile void **)ICPLB_FAULT_ADDR)
@@ -111,12 +100,13 @@
#define pICPLB_DATA14 ((volatile unsigned long *)ICPLB_DATA14)
#define pICPLB_DATA15 ((volatile unsigned long *)ICPLB_DATA15)
#define pITEST_COMMAND ((volatile unsigned long *)ITEST_COMMAND)
-
-/* #define ITEST_INDEX 0xFFE01304 */ /* Instruction Test Index Register */
+/*
+#define ITEST_INDEX 0xFFE01304 // Instruction Test Index Register
+*/
#define pITEST_DATA0 ((volatile unsigned long *)ITEST_DATA0)
#define pITEST_DATA1 ((volatile unsigned long *)ITEST_DATA1)
-/* Event/Interrupt Registers */
+// Event/Interrupt Registers
#define pEVT0 ((volatile void **)EVT0)
#define pEVT1 ((volatile void **)EVT1)
#define pEVT2 ((volatile void **)EVT2)
@@ -137,24 +127,24 @@
#define pIPEND ((volatile unsigned long *)IPEND)
#define pILAT ((volatile unsigned long *)ILAT)
-/* Core Timer Registers */
+// Core Timer Registers
#define pTCNTL ((volatile unsigned long *)TCNTL)
#define pTPERIOD ((volatile unsigned long *)TPERIOD)
#define pTSCALE ((volatile unsigned long *)TSCALE)
#define pTCOUNT ((volatile unsigned long *)TCOUNT)
-/* Debug/MP/Emulation Registers */
+// Debug/MP/Emulation Registers
#define pDSPID ((volatile unsigned long *)DSPID)
#define pDBGCTL ((volatile unsigned long *)DBGCTL)
#define pDBGSTAT ((volatile unsigned long *)DBGSTAT)
#define pEMUDAT ((volatile unsigned long *)EMUDAT)
-/* Trace Buffer Registers */
+// Trace Buffer Registers
#define pTBUFCTL ((volatile unsigned long *)TBUFCTL)
#define pTBUFSTAT ((volatile unsigned long *)TBUFSTAT)
#define pTBUF ((volatile void **)TBUF)
-/* Watch Point Control Registers */
+// Watch Point Control Registers
#define pWPIACTL ((volatile unsigned long *)WPIACTL)
#define pWPIA0 ((volatile void **)WPIA0)
#define pWPIA1 ((volatile void **)WPIA1)
@@ -175,11 +165,13 @@
#define pWPDACNT1 ((volatile unsigned long *)WPDACNT1)
#define pWPSTAT ((volatile unsigned long *)WPSTAT)
-/* Performance Monitor Registers */
+// Performance Monitor Registers
#define pPFCTL ((volatile unsigned long *)PFCTL)
#define pPFCNTR0 ((volatile unsigned long *)PFCNTR0)
#define pPFCNTR1 ((volatile unsigned long *)PFCNTR1)
-/* #define IPRIO 0xFFE02110 */ /* Core Interrupt Priority Register */
+/*
+#define IPRIO 0xFFE02110 // Core Interrupt Priority Register
+*/
-#endif /* _CDEF_LPBLACKFIN_H */
+#endif /* _CDEF_LPBLACKFIN_H */
diff --git a/include/asm-blackfin/cpu/def_LPBlackfin.h b/include/asm-blackfin/arch-common/def_LPBlackfin.h
index 9ac78c8..ebeeea0 100644
--- a/include/asm-blackfin/cpu/def_LPBlackfin.h
+++ b/include/asm-blackfin/arch-common/def_LPBlackfin.h
@@ -92,13 +92,13 @@
/* ** Masks */
/* Exception cause */
-#define SEQSTAT_EXCAUSE MK_BMSK_(SEQSTAT_EXCAUSE0_P ) | \
+#define SEQSTAT_EXCAUSE ( MK_BMSK_(SEQSTAT_EXCAUSE0_P ) | \
MK_BMSK_(SEQSTAT_EXCAUSE1_P ) | \
MK_BMSK_(SEQSTAT_EXCAUSE2_P ) | \
MK_BMSK_(SEQSTAT_EXCAUSE3_P ) | \
MK_BMSK_(SEQSTAT_EXCAUSE4_P ) | \
MK_BMSK_(SEQSTAT_EXCAUSE5_P ) | \
- 0
+ 0 )
/* Indicates whether the last reset was a software reset (=1) */
#define SEQSTAT_SFTRESET MK_BMSK_(SEQSTAT_SFTRESET_P )
diff --git a/include/asm-blackfin/bitops.h b/include/asm-blackfin/bitops.h
index 65d2c25..7766c4a 100644
--- a/include/asm-blackfin/bitops.h
+++ b/include/asm-blackfin/bitops.h
@@ -59,7 +59,7 @@ static __inline__ unsigned long ffz(unsigned long word)
static __inline__ void set_bit(int nr, volatile void *addr)
{
- int *a = (int *) addr;
+ int *a = (int *)addr;
int mask;
unsigned long flags;
@@ -72,7 +72,7 @@ static __inline__ void set_bit(int nr, volatile void *addr)
static __inline__ void __set_bit(int nr, volatile void *addr)
{
- int *a = (int *) addr;
+ int *a = (int *)addr;
int mask;
a += nr >> 5;
@@ -88,7 +88,7 @@ static __inline__ void __set_bit(int nr, volatile void *addr)
static __inline__ void clear_bit(int nr, volatile void *addr)
{
- int *a = (int *) addr;
+ int *a = (int *)addr;
int mask;
unsigned long flags;
@@ -102,7 +102,7 @@ static __inline__ void clear_bit(int nr, volatile void *addr)
static __inline__ void change_bit(int nr, volatile void *addr)
{
int mask, flags;
- unsigned long *ADDR = (unsigned long *) addr;
+ unsigned long *ADDR = (unsigned long *)addr;
ADDR += nr >> 5;
mask = 1 << (nr & 31);
@@ -114,7 +114,7 @@ static __inline__ void change_bit(int nr, volatile void *addr)
static __inline__ void __change_bit(int nr, volatile void *addr)
{
int mask;
- unsigned long *ADDR = (unsigned long *) addr;
+ unsigned long *ADDR = (unsigned long *)addr;
ADDR += nr >> 5;
mask = 1 << (nr & 31);
@@ -124,7 +124,7 @@ static __inline__ void __change_bit(int nr, volatile void *addr)
static __inline__ int test_and_set_bit(int nr, volatile void *addr)
{
int mask, retval;
- volatile unsigned int *a = (volatile unsigned int *) addr;
+ volatile unsigned int *a = (volatile unsigned int *)addr;
unsigned long flags;
a += nr >> 5;
@@ -140,7 +140,7 @@ static __inline__ int test_and_set_bit(int nr, volatile void *addr)
static __inline__ int __test_and_set_bit(int nr, volatile void *addr)
{
int mask, retval;
- volatile unsigned int *a = (volatile unsigned int *) addr;
+ volatile unsigned int *a = (volatile unsigned int *)addr;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
@@ -152,7 +152,7 @@ static __inline__ int __test_and_set_bit(int nr, volatile void *addr)
static __inline__ int test_and_clear_bit(int nr, volatile void *addr)
{
int mask, retval;
- volatile unsigned int *a = (volatile unsigned int *) addr;
+ volatile unsigned int *a = (volatile unsigned int *)addr;
unsigned long flags;
a += nr >> 5;
@@ -168,7 +168,7 @@ static __inline__ int test_and_clear_bit(int nr, volatile void *addr)
static __inline__ int __test_and_clear_bit(int nr, volatile void *addr)
{
int mask, retval;
- volatile unsigned int *a = (volatile unsigned int *) addr;
+ volatile unsigned int *a = (volatile unsigned int *)addr;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
@@ -180,7 +180,7 @@ static __inline__ int __test_and_clear_bit(int nr, volatile void *addr)
static __inline__ int test_and_change_bit(int nr, volatile void *addr)
{
int mask, retval;
- volatile unsigned int *a = (volatile unsigned int *) addr;
+ volatile unsigned int *a = (volatile unsigned int *)addr;
unsigned long flags;
a += nr >> 5;
@@ -196,7 +196,7 @@ static __inline__ int test_and_change_bit(int nr, volatile void *addr)
static __inline__ int __test_and_change_bit(int nr, volatile void *addr)
{
int mask, retval;
- volatile unsigned int *a = (volatile unsigned int *) addr;
+ volatile unsigned int *a = (volatile unsigned int *)addr;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
@@ -208,16 +208,15 @@ static __inline__ int __test_and_change_bit(int nr, volatile void *addr)
/*
* This routine doesn't need to be atomic.
*/
-static __inline__ int __constant_test_bit(int nr,
- const volatile void *addr)
+static __inline__ int __constant_test_bit(int nr, const volatile void *addr)
{
return ((1UL << (nr & 31)) &
- (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
+ (((const volatile unsigned int *)addr)[nr >> 5])) != 0;
}
static __inline__ int __test_bit(int nr, volatile void *addr)
{
- int *a = (int *) addr;
+ int *a = (int *)addr;
int mask;
a += nr >> 5;
@@ -235,7 +234,7 @@ static __inline__ int __test_bit(int nr, volatile void *addr)
static __inline__ int find_next_zero_bit(void *addr, int size, int offset)
{
- unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
+ unsigned long *p = ((unsigned long *)addr) + (offset >> 5);
unsigned long result = offset & ~31UL;
unsigned long tmp;
@@ -290,7 +289,7 @@ static __inline__ int ext2_set_bit(int nr, volatile void *addr)
{
int mask, retval;
unsigned long flags;
- volatile unsigned char *ADDR = (unsigned char *) addr;
+ volatile unsigned char *ADDR = (unsigned char *)addr;
ADDR += nr >> 3;
mask = 1 << (nr & 0x07);
@@ -305,7 +304,7 @@ static __inline__ int ext2_clear_bit(int nr, volatile void *addr)
{
int mask, retval;
unsigned long flags;
- volatile unsigned char *ADDR = (unsigned char *) addr;
+ volatile unsigned char *ADDR = (unsigned char *)addr;
ADDR += nr >> 3;
mask = 1 << (nr & 0x07);
@@ -319,7 +318,7 @@ static __inline__ int ext2_clear_bit(int nr, volatile void *addr)
static __inline__ int ext2_test_bit(int nr, const volatile void *addr)
{
int mask;
- const volatile unsigned char *ADDR = (const unsigned char *) addr;
+ const volatile unsigned char *ADDR = (const unsigned char *)addr;
ADDR += nr >> 3;
mask = 1 << (nr & 0x07);
@@ -331,10 +330,9 @@ static __inline__ int ext2_test_bit(int nr, const volatile void *addr)
static __inline__ unsigned long ext2_find_next_zero_bit(void *addr,
unsigned long size,
- unsigned long
- offset)
+ unsigned long offset)
{
- unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
+ unsigned long *p = ((unsigned long *)addr) + (offset >> 5);
unsigned long result = offset & ~31UL;
unsigned long tmp;
diff --git a/include/asm-blackfin/blackfin.h b/include/asm-blackfin/blackfin.h
index fbdbf30..0ec9207 100644
--- a/include/asm-blackfin/blackfin.h
+++ b/include/asm-blackfin/blackfin.h
@@ -25,22 +25,16 @@
#ifndef _BLACKFIN_H_
#define _BLACKFIN_H_
-#include <asm/cpu/defBF533.h>
-#include <asm/cpu/bf533_serial.h>
+#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY))
+# ifdef SHARED_RESOURCES
+# include <asm/shared_resources.h>
+# endif
-#ifndef __ASSEMBLY__
-#ifndef ASSEMBLY
+# include <linux/types.h>
-#ifdef SHARED_RESOURCES
- #include <asm/shared_resources.h>
+extern u_long get_sclk(void);
#endif
-#include <asm/cpu/cdefBF53x.h>
-#endif
-#endif
-
-#include <asm/cpu/defBF533.h>
-#include <asm/cpu/defBF533_extn.h>
-#include <asm/cpu/bf533_serial.h>
+#include <asm/arch-common/cdefBF5xx.h>
#endif
diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h
index 7715f64..dd695e1 100644
--- a/include/asm-blackfin/cplb.h
+++ b/include/asm-blackfin/cplb.h
@@ -7,14 +7,15 @@
************************************************************************/
/* Defines necessary for cplb initialisation routines. */
-
#ifndef _CPLB_H
#define _CPLB_H
+#define CONFIG_BLKFIN_WT
+
#define CPLB_ENABLE_ICACHE_P 0
#define CPLB_ENABLE_DCACHE_P 1
#define CPLB_ENABLE_DCACHE2_P 2
-#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated!*/
+#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */
#define CPLB_ENABLE_ICPLBS_P 4
#define CPLB_ENABLE_DCPLBS_P 5
@@ -45,4 +46,35 @@
#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID
#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL
-#endif /* _CPLB_H */
+/* Data Attibutes*/
+
+#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
+#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
+
+/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
+
+#define ANOMALY_05000158 0x200
+
+#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
+#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
+#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
+
+#else /*Write Through */
+#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
+#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
+#endif
+
+#if defined(CONFIG_BF561)
+#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 2) /* SDRAM +L1 + ASYNC_Memory */
+#else
+#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 1 + 3) /* SDRAM + L1 + ASYNC_Memory */
+#endif
+#endif /* _CPLB_H */
diff --git a/include/asm-blackfin/cplbtab.h b/include/asm-blackfin/cplbtab.h
deleted file mode 100644
index ab7d989..0000000
--- a/include/asm-blackfin/cplbtab.h
+++ /dev/null
@@ -1,572 +0,0 @@
-/*This file is subject to the terms and conditions of the GNU General Public
- * License.
- *
- * Blackfin BF533/2.6 support : LG Soft India
- * Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd
- * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's
- * shouldn't be victimized. cplbmgr.S search logic is corrected
- * to findout the appropriate victim.
- * 2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC
- * : LG Soft India
- */
-#include <config.h>
-
-#ifndef __ARCH_BFINNOMMU_CPLBTAB_H
-#define __ARCH_BFINNOMMU_CPLBTAB_H
-
-/*************************************************************************
- * ICPLB TABLE
- *************************************************************************/
-
-.data
-
-/* This table is configurable */
-
-.align 4;
-
-/* Data Attibutes*/
-
-#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
-#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
-#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
-#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
-
-/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
-
-#define ANOMALY_05000158 0x200
-#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
- #define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
- #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
- #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
- #define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
- #define SDRAM_EBIU (PAGE_SIZE_1MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
-
-#else /*Write Through*/
- #define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
- #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
- #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
- #define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
- #define SDRAM_EBIU (PAGE_SIZE_1MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
-#endif
-
-.global icplb_table
-icplb_table:
-.byte4 0xFFA00000;
-.byte4 (L1_IMEMORY);
-.byte4 0x00000000;
-.byte4 (SDRAM_IKERNEL); /*SDRAM_Page1*/
-.byte4 0x00400000;
-.byte4 (SDRAM_IKERNEL); /*SDRAM_Page1*/
-.byte4 0x07C00000;
-.byte4 (SDRAM_IKERNEL); /*SDRAM_Page14*/
-.byte4 0x00800000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page2*/
-.byte4 0x00C00000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page2*/
-.byte4 0x01000000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page4*/
-.byte4 0x01400000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page5*/
-.byte4 0x01800000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page6*/
-.byte4 0x01C00000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page7*/
-#ifndef CONFIG_EZKIT /*STAMP Memory regions*/
-.byte4 0x02000000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page8*/
-.byte4 0x02400000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page9*/
-.byte4 0x02800000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page10*/
-.byte4 0x02C00000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page11*/
-.byte4 0x03000000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page12*/
-.byte4 0x03400000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page13*/
-#endif
-.byte4 0xffffffff; /* end of section - termination*/
-
-.align 4;
-.global ipdt_table
-ipdt_table:
-#ifdef CONFIG_CPLB_INFO
-.byte4 0x00000000;
-.byte4 (SDRAM_IKERNEL); /*SDRAM_Page0*/
-.byte4 0x00400000;
-.byte4 (SDRAM_IKERNEL); /*SDRAM_Page1*/
-#endif
-.byte4 0x00800000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page2*/
-.byte4 0x00C00000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page3*/
-.byte4 0x01000000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page4*/
-.byte4 0x01400000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page5*/
-.byte4 0x01800000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page6*/
-.byte4 0x01C00000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page7*/
-#ifndef CONFIG_EZKIT /*STAMP Memory regions*/
-.byte4 0x02000000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page8*/
-.byte4 0x02400000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page9*/
-.byte4 0x02800000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page10*/
-.byte4 0x02C00000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page11*/
-.byte4 0x03000000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page12*/
-.byte4 0x03400000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page13*/
-.byte4 0x03800000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page14*/
-.byte4 0x03C00000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page15*/
-#endif
-.byte4 0x20200000;
-.byte4 (SDRAM_EBIU); /* Async Memory Bank 2 (Secnd)*/
-.byte4 0x20100000;
-.byte4 (SDRAM_EBIU); /* Async Memory Bank 1 (Prim B)*/
-.byte4 0x20000000;
-.byte4 (SDRAM_EBIU); /* Async Memory Bank 0 (Prim A)*/
-.byte4 0x20300000; /*Fix for Network*/
-.byte4 (SDRAM_EBIU); /*Async Memory bank 3*/
-
-#ifdef CONFIG_STAMP
-.byte4 0x04000000;
-.byte4 (SDRAM_IGENERIC);
-.byte4 0x04400000;
-.byte4 (SDRAM_IGENERIC);
-.byte4 0x04800000;
-.byte4 (SDRAM_IGENERIC);
-.byte4 0x04C00000;
-.byte4 (SDRAM_IGENERIC);
-.byte4 0x05000000;
-.byte4 (SDRAM_IGENERIC);
-.byte4 0x05400000;
-.byte4 (SDRAM_IGENERIC);
-.byte4 0x05800000;
-.byte4 (SDRAM_IGENERIC);
-.byte4 0x05C00000;
-.byte4 (SDRAM_IGENERIC);
-.byte4 0x06000000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page25*/
-.byte4 0x06400000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page26*/
-.byte4 0x06800000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page27*/
-.byte4 0x06C00000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page28*/
-.byte4 0x07000000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page29*/
-.byte4 0x07400000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page30*/
-.byte4 0x07800000;
-.byte4 (SDRAM_IGENERIC); /*SDRAM_Page31*/
-#ifdef CONFIG_CPLB_INFO
-.byte4 0x07C00000;
-.byte4 (SDRAM_IKERNEL); /*SDRAM_Page32*/
-#endif
-#endif
-.byte4 0xffffffff; /* end of section - termination*/
-
-/*********************************************************************
- * DCPLB TABLE
- ********************************************************************/
-
-.global dcplb_table
-dcplb_table:
-.byte4 0x00000000;
-.byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/
-.byte4 0x00400000;
-.byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/
-.byte4 0x07C00000;
-.byte4 (SDRAM_DKERNEL); /*SDRAM_Page15*/
-.byte4 0x00800000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page2*/
-.byte4 0x00C00000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page3*/
-.byte4 0x01000000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page4*/
-.byte4 0x01400000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page5*/
-.byte4 0x01800000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page6*/
-.byte4 0x01C00000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page7*/
-#ifndef CONFIG_EZKIT
-.byte4 0x02000000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page8*/
-.byte4 0x02400000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page9*/
-.byte4 0x02800000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page10*/
-.byte4 0x02C00000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page11*/
-.byte4 0x03000000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page12*/
-.byte4 0x03400000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page13*/
-.byte4 0x03800000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page14*/
-#endif
-.byte4 0xffffffff; /*end of section - termination*/
-
-/**********************************************************************
- * PAGE DESCRIPTOR TABLE
- *
- **********************************************************************/
-
-/* Till here we are discussing about the static memory management model.
- * However, the operating envoronments commonly define more CPLB
- * descriptors to cover the entire addressable memory than will fit into
- * the available on-chip 16 CPLB MMRs. When this happens, the below table
- * will be used which will hold all the potentially required CPLB descriptors
- *
- * This is how Page descriptor Table is implemented in uClinux/Blackfin.
- */
-.global dpdt_table
-dpdt_table:
-#ifdef CONFIG_CPLB_INFO
-.byte4 0x00000000;
-.byte4 (SDRAM_DKERNEL); /*SDRAM_Page0*/
-.byte4 0x00400000;
-.byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/
-#endif
-.byte4 0x00800000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page2*/
-.byte4 0x00C00000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page3*/
-.byte4 0x01000000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page4*/
-.byte4 0x01400000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page5*/
-.byte4 0x01800000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page6*/
-.byte4 0x01C00000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page7*/
-
-#ifndef CONFIG_EZKIT
-.byte4 0x02000000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page8*/
-.byte4 0x02400000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page9*/
-.byte4 0x02800000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page10*/
-.byte4 0x02C00000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page11*/
-.byte4 0x03000000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page12*/
-.byte4 0x03400000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page13*/
-.byte4 0x03800000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page14*/
-.byte4 0x03C00000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page15*/
-#endif
-.byte4 0x20200000;
-.byte4 (SDRAM_EBIU); /* Async Memory Bank 2 (Secnd)*/
-.byte4 0x20100000;
-.byte4 (SDRAM_EBIU); /* Async Memory Bank 1 (Prim B)*/
-.byte4 0x20000000;
-.byte4 (SDRAM_EBIU); /* Async Memory Bank 0 (Prim A)*/
-.byte4 0x20300000; /*Fix for Network*/
-.byte4 (SDRAM_EBIU); /*Async Memory bank 3*/
-
-#ifdef CONFIG_STAMP
-.byte4 0x04000000;
-.byte4 (SDRAM_DGENERIC);
-.byte4 0x04400000;
-.byte4 (SDRAM_DGENERIC);
-.byte4 0x04800000;
-.byte4 (SDRAM_DGENERIC);
-.byte4 0x04C00000;
-.byte4 (SDRAM_DGENERIC);
-.byte4 0x05000000;
-.byte4 (SDRAM_DGENERIC);
-.byte4 0x05400000;
-.byte4 (SDRAM_DGENERIC);
-.byte4 0x05800000;
-.byte4 (SDRAM_DGENERIC);
-.byte4 0x05C00000;
-.byte4 (SDRAM_DGENERIC);
-.byte4 0x06000000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page25*/
-.byte4 0x06400000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page26*/
-.byte4 0x06800000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page27*/
-.byte4 0x06C00000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page28*/
-.byte4 0x07000000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page29*/
-.byte4 0x07400000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page30*/
-.byte4 0x07800000;
-.byte4 (SDRAM_DGENERIC); /*SDRAM_Page31*/
-#ifdef CONFIG_CPLB_INFO
-.byte4 0x07C00000;
-.byte4 (SDRAM_DKERNEL); /*SDRAM_Page32*/
-#endif
-#endif
-
-.byte4 0xFF900000;
-.byte4 (L1_DMEMORY);
-.byte4 0xFF901000;
-.byte4 (L1_DMEMORY);
-.byte4 0xFF902000;
-.byte4 (L1_DMEMORY);
-.byte4 0xFF903000;
-.byte4 (L1_DMEMORY);
-.byte4 0xFF904000;
-.byte4 (L1_DMEMORY);
-.byte4 0xFF905000;
-.byte4 (L1_DMEMORY);
-.byte4 0xFF906000;
-.byte4 (L1_DMEMORY);
-.byte4 0xFF907000;
-.byte4 (L1_DMEMORY);
-.byte4 0xFF800000;
-.byte4 (L1_DMEMORY);
-.byte4 0xFF801000;
-.byte4 (L1_DMEMORY);
-.byte4 0xFF802000;
-.byte4 (L1_DMEMORY);
-.byte4 0xFF803000;
-.byte4 (L1_DMEMORY);
-
-.byte4 0xffffffff; /*end of section - termination*/
-
-#ifdef CONFIG_CPLB_INFO
-.global ipdt_swapcount_table; /* swapin count first, then swapout count*/
-ipdt_swapcount_table:
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 10 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 20 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 30 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 40 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 50 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 60 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 70 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 80 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 90 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 100 */
-
-.global dpdt_swapcount_table; /* swapin count first, then swapout count*/
-dpdt_swapcount_table:
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 10 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 20 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 30 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 40 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 50 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 60 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 70 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 80 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 80 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 100 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 110 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 120 */
-
-#endif
-
-#endif /*__ARCH_BFINNOMMU_CPLBTAB_H*/
diff --git a/include/asm-blackfin/cpu/cdefBF53x.h b/include/asm-blackfin/cpu/cdefBF53x.h
deleted file mode 100644
index db4eaa9..0000000
--- a/include/asm-blackfin/cpu/cdefBF53x.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/************************************************************************
- *
- * cdefBF53x.h
- *
- * (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved.
- *
- ************************************************************************/
-
-#ifndef _CDEFBF53x_H
-#define _CDEFBF53x_H
-
-#if defined(__ADSPBF531__)
- #include <asm/cpu/cdefBF531.h>
-#elif defined(__ADSPBF532__)
- #include <asm/cpu/cdefBF532.h>
-#elif defined(__ADSPBF533__)
- #include <asm/cpu/cdefBF533.h>
-#elif defined(__ADSPBF561__)
- #include <asm/cpu/cdefBF561.h>
-#elif defined(__ADSPBF535__)
- #include <asm/cpu/cdefBF535.h>
-#elif defined(__AD6532__)
- #include <sam/cpu/cdefAD6532.h>
-#else
- #if defined(__ADSPLPBLACKFIN__)
- #include <asm/cpu/cdefBF532.h>
- #else
- #include <asm/cpu/cdefBF535.h>
- #endif
-#endif
-
-#endif /* _CDEFBF53x_H */
diff --git a/include/asm-blackfin/delay.h b/include/asm-blackfin/delay.h
index dbb7388..0c01e9f 100644
--- a/include/asm-blackfin/delay.h
+++ b/include/asm-blackfin/delay.h
@@ -35,9 +35,9 @@
extern __inline__ void __delay(unsigned long loops)
{
__asm__ __volatile__("1:\t%0 += -1;\n\t"
- "cc = %0 == 0;\n\t"
- "if ! cc jump 1b;\n":"=d"(loops)
- :"0"(loops));
+ "cc = %0 == 0;\n\t"
+ "if ! cc jump 1b;\n":"=d"(loops)
+ :"0"(loops));
}
/*
diff --git a/include/asm-blackfin/entry.h b/include/asm-blackfin/entry.h
index 607a5b8..b64d406 100644
--- a/include/asm-blackfin/entry.h
+++ b/include/asm-blackfin/entry.h
@@ -370,16 +370,12 @@
#define STR1(X) #X
#if defined(NEW_PT_REGS)
-
#define PT_OFF_ORIG_R0 208
#define PT_OFF_SR 8
-
#else
-
#define PT_OFF_ORIG_R0 0x54
#define PT_OFF_SR 0x38 /* seqstat in pt_regs */
-
-#endif
#endif
#endif
+#endif
diff --git a/include/asm-blackfin/global_data.h b/include/asm-blackfin/global_data.h
index 56a12f0..1c73853 100644
--- a/include/asm-blackfin/global_data.h
+++ b/include/asm-blackfin/global_data.h
@@ -45,11 +45,16 @@ typedef struct global_data {
unsigned long board_type;
unsigned long baudrate;
unsigned long have_console; /* serial_init() was called */
- unsigned long ram_size; /* RAM size */
+ unsigned long ram_size; /* RAM size */
unsigned long reloc_off; /* Relocation Offset */
- unsigned long env_addr; /* Address of Environment struct */
+ unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Checksum of Environment valid? */
- void **jt; /* jump table */
+#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
+ unsigned long post_log_word; /* Record POST activities */
+ unsigned long post_init_f_time; /* When post_init_f started */
+#endif
+
+ void **jt; /* jump table */
} gd_t;
/*
@@ -59,6 +64,6 @@ typedef struct global_data {
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
#define GD_FLG_SILENT 0x00004 /* Silent mode */
-#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("P5")
+#define DECLARE_GLOBAL_DATA_PTR register gd_t * volatile gd asm ("P5")
#endif
diff --git a/include/asm-blackfin/hw_irq.h b/include/asm-blackfin/hw_irq.h
index 1ee050e..baa3e0c 100644
--- a/include/asm-blackfin/hw_irq.h
+++ b/include/asm-blackfin/hw_irq.h
@@ -30,8 +30,14 @@
#include <linux/config.h>
#ifdef CONFIG_EZKIT533
-#include <asm/board/bf533_irq.h>
+#include <asm/arch-bf533/irq.h>
+#endif
+#ifdef CONFIG_EZKIT561
+#include <asm/arch-bf561/irq.h>
#endif
#ifdef CONFIG_STAMP
-#include <asm/board/bf533_irq.h>
+#include <asm/arch-bf533/irq.h>
+#endif
+#ifdef CONFIG_BF537
+#include <asm/arch-bf537/irq.h>
#endif
diff --git a/include/asm-blackfin/io-kernel.h b/include/asm-blackfin/io-kernel.h
index 0b0572f..3c087c3 100644
--- a/include/asm-blackfin/io-kernel.h
+++ b/include/asm-blackfin/io-kernel.h
@@ -87,7 +87,8 @@
#define IOMAP_WRITETHROUGH 3
#ifndef __ASSEMBLY__
-extern void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag);
+extern void *__ioremap(unsigned long physaddr, unsigned long size,
+ int cacheflag);
extern void __iounmap(void *addr, unsigned long size);
extern inline void *ioremap(unsigned long physaddr, unsigned long size)
{
@@ -97,11 +98,13 @@ extern inline void *ioremap_nocache(unsigned long physaddr, unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
}
-extern inline void *ioremap_writethrough(unsigned long physaddr, unsigned long size)
+extern inline void *ioremap_writethrough(unsigned long physaddr,
+ unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
}
-extern inline void *ioremap_fullcache(unsigned long physaddr, unsigned long size)
+extern inline void *ioremap_fullcache(unsigned long physaddr,
+ unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
}
diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h
index fc27194..6bab6e7 100644
--- a/include/asm-blackfin/io.h
+++ b/include/asm-blackfin/io.h
@@ -25,11 +25,6 @@
#ifndef _BLACKFIN_IO_H
#define _BLACKFIN_IO_H
-static inline void sync(void)
-{
- __asm__ __volatile__ asm("ssync" : : : "memory");
-}
-
#ifdef __KERNEL__
#include <linux/config.h>
@@ -38,7 +33,11 @@ static inline void sync(void)
extern void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words);
extern void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words);
extern unsigned char cf_inb(volatile unsigned char *addr);
-extern void cf_outb(unsigned char val, volatile unsigned char* addr);
+extern void cf_outb(unsigned char val, volatile unsigned char *addr);
+
+static inline void sync(void)
+{
+}
/*
* These are for ISA/PCI shared memory _only_ and should never be used
@@ -51,7 +50,6 @@ extern void cf_outb(unsigned char val, volatile unsigned char* addr);
* memory location directly.
*/
-
#define readb(addr) ({ unsigned char __v = (*(volatile unsigned char *) (addr));asm("ssync;"); __v; })
#define readw(addr) ({ unsigned short __v = (*(volatile unsigned short *) (addr)); asm("ssync;");__v; })
#define readl(addr) ({ unsigned int __v = (*(volatile unsigned int *) (addr));asm("ssync;"); __v; })
@@ -100,8 +98,7 @@ extern inline void *ioremap(unsigned long physaddr, unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
}
-extern inline void *ioremap_nocache(unsigned long physaddr,
- unsigned long size)
+extern inline void *ioremap_nocache(unsigned long physaddr, unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
}
diff --git a/include/asm-blackfin/irq.h b/include/asm-blackfin/irq.h
index 5fbc5a3..aede742 100644
--- a/include/asm-blackfin/irq.h
+++ b/include/asm-blackfin/irq.h
@@ -39,7 +39,7 @@
#define _BLACKFIN_IRQ_H_
#include <linux/config.h>
-#include <asm/cpu/bf533_irq.h>
+#include <asm/hw_irq.h>
/*
* On the Blackfin, the interrupt structure allows remmapping of the hardware
@@ -85,8 +85,8 @@ static __inline__ int irq_cannonicalize(int irq)
extern void (*mach_enable_irq) (unsigned int);
extern void (*mach_disable_irq) (unsigned int);
extern int sys_request_irq(unsigned int,
- void (*)(int, void *, struct pt_regs *),
- unsigned long, const char *, void *);
+ void (*)(int, void *, struct pt_regs *),
+ unsigned long, const char *, void *);
extern void sys_free_irq(unsigned int, void *);
/*
diff --git a/include/asm-blackfin/machdep.h b/include/asm-blackfin/machdep.h
index 0a43ba1..4fea74c 100644
--- a/include/asm-blackfin/machdep.h
+++ b/include/asm-blackfin/machdep.h
@@ -39,7 +39,8 @@ struct hwclk_time;
struct gendisk;
struct buffer_head;
-extern void (*mach_sched_init) (void (*handler) (int, void *, struct pt_regs *));
+extern
+ void (*mach_sched_init) (void (*handler) (int, void *, struct pt_regs *));
/* machine dependent keyboard functions */
extern int (*mach_keyb_init) (void);
diff --git a/include/asm-blackfin/mem_init.h b/include/asm-blackfin/mem_init.h
index 1a13d90..a9baacd 100644
--- a/include/asm-blackfin/mem_init.h
+++ b/include/asm-blackfin/mem_init.h
@@ -22,7 +22,13 @@
* MA 02111-1307 USA
*/
-#if ( CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E )
+#if (CONFIG_MEM_MT48LC16M16A2TG_75 || \
+ CONFIG_MEM_MT48LC64M4A2FB_7E || \
+ CONFIG_MEM_MT48LC16M8A2TG_75 || \
+ CONFIG_MEM_MT48LC8M16A2TG_7E || \
+ CONFIG_MEM_MT48LC8M32B2B5_7 || \
+ CONFIG_MEM_MT48LC32M8A2_75)
+
#if ( CONFIG_SCLK_HZ > 119402985 )
#define SDRAM_tRP TRP_2
#define SDRAM_tRP_num 2
@@ -66,7 +72,7 @@
#if ( CONFIG_SCLK_HZ > 59701493 ) && ( CONFIG_SCLK_HZ <= 66666667 )
#define SDRAM_tRP TRP_1
#define SDRAM_tRP_num 1
- #define SDRAM_tRAS TRAS_4
+ #define SDRAM_tRAS TRAS_3
#define SDRAM_tRAS_num 3
#define SDRAM_tRCD TRCD_1
#define SDRAM_tWR TWR_2
@@ -111,6 +117,34 @@
#define SDRAM_CL CL_2
#endif
+#if (CONFIG_MEM_MT48LC16M8A2TG_75)
+ /*SDRAM INFORMATION: */
+ #define SDRAM_Tref 64 /* Refresh period in milliseconds */
+ #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
+ #define SDRAM_CL CL_3
+#endif
+
+#if (CONFIG_MEM_MT48LC32M8A2_75)
+ /*SDRAM INFORMATION: */
+#define SDRAM_Tref 64 /* Refresh period in milliseconds */
+#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
+#define SDRAM_CL CL_3
+#endif
+
+#if (CONFIG_MEM_MT48LC8M16A2TG_7E)
+ /*SDRAM INFORMATION: */
+ #define SDRAM_Tref 64 /* Refresh period in milliseconds */
+ #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
+ #define SDRAM_CL CL_2
+#endif
+
+#if (CONFIG_MEM_MT48LC8M32B2B5_7)
+ /*SDRAM INFORMATION: */
+ #define SDRAM_Tref 64 /* Refresh period in milliseconds */
+ #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
+ #define SDRAM_CL CL_3
+#endif
+
#if ( CONFIG_MEM_SIZE == 128 )
#define SDRAM_SIZE EBSZ_128
#endif
diff --git a/include/asm-blackfin/page.h b/include/asm-blackfin/page.h
index 406ece5..d59828c 100644
--- a/include/asm-blackfin/page.h
+++ b/include/asm-blackfin/page.h
@@ -112,11 +112,6 @@ extern __inline__ int get_order(unsigned long size)
#define virt_to_page(addr) (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT))
#define VALID_PAGE(page) ((page - mem_map) < max_mapnr)
-#define BUG() do { \
- \
- while (1); /* dead-loop */ \
-} while (0)
-
#define PAGE_BUG(page) do { \
BUG(); \
} while (0)
diff --git a/include/asm-blackfin/processor.h b/include/asm-blackfin/processor.h
index 19bd720..df49bed 100644
--- a/include/asm-blackfin/processor.h
+++ b/include/asm-blackfin/processor.h
@@ -126,8 +126,7 @@ static inline void release_thread(struct task_struct *dead_task)
{
}
-extern int kernel_thread(int (*fn) (void *), void *arg,
- unsigned long flags);
+extern int kernel_thread(int (*fn) (void *), void *arg, unsigned long flags);
#define copy_segments(tsk, mm) do { } while (0)
#define release_segments(mm) do { } while (0)
diff --git a/include/asm-blackfin/setup.h b/include/asm-blackfin/setup.h
index 6ce9688..a3c1715 100644
--- a/include/asm-blackfin/setup.h
+++ b/include/asm-blackfin/setup.h
@@ -75,12 +75,13 @@ extern unsigned long vme_brdtype;
extern int blackfin_num_memory; /* # of memory blocks found (and used) */
extern int blackfin_realnum_memory; /* real # of memory blocks found */
-extern struct mem_info blackfin_memory[NUM_MEMINFO]; /* memory description */
struct mem_info {
unsigned long addr; /* physical address of memory chunk */
unsigned long size; /* length of memory chunk (in bytes) */
};
+
+extern struct mem_info blackfin_memory[NUM_MEMINFO]; /* memory description */
#endif
#endif
diff --git a/include/asm-blackfin/string.h b/include/asm-blackfin/string.h
index ffd81d6..aac6bc9 100644
--- a/include/asm-blackfin/string.h
+++ b/include/asm-blackfin/string.h
@@ -31,21 +31,26 @@
#include <asm/setup.h>
#include <asm/page.h>
-#include <asm/cpu/defBF533.h>
+#include <config.h>
+#include <asm/blackfin.h>
#define __HAVE_ARCH_STRCPY
#define __HAVE_ARCH_STRNCPY
#define __HAVE_ARCH_STRCMP
#define __HAVE_ARCH_STRNCMP
#define __HAVE_ARCH_MEMCPY
+#define __HAVE_ARCH_MEMCMP
+#define __HAVE_ARCH_MEMSET
+#define __HAVE_ARCH_MEMMOVE
extern char *strcpy(char *dest, const char *src);
extern char *strncpy(char *dest, const char *src, size_t n);
extern int strcmp(const char *cs, const char *ct);
extern int strncmp(const char *cs, const char *ct, size_t count);
-extern void * memcpy(void * dest,const void *src,size_t count);
+extern void *memcpy(void *dest, const void *src, size_t count);
extern void *memset(void *s, int c, size_t count);
extern int memcmp(const void *, const void *, __kernel_size_t);
+extern void *memmove(void *dest, const void *src, size_t count);
#else /* KERNEL */
diff --git a/include/asm-blackfin/u-boot.h b/include/asm-blackfin/u-boot.h
index ec39338..e1a435a 100644
--- a/include/asm-blackfin/u-boot.h
+++ b/include/asm-blackfin/u-boot.h
@@ -29,7 +29,7 @@
#define _U_BOOT_H_ 1
typedef struct bd_info {
- int bi_baudrate; /* serial console baudrate */
+ int bi_baudrate; /* serial console baudrate */
unsigned long bi_ip_addr; /* IP Address */
unsigned char bi_enetaddr[6]; /* Ethernet adress */
unsigned long bi_arch_number; /* unique id for this board */
diff --git a/include/asm-blackfin/uaccess.h b/include/asm-blackfin/uaccess.h
index 8578166..61e2bfe 100644
--- a/include/asm-blackfin/uaccess.h
+++ b/include/asm-blackfin/uaccess.h
@@ -41,11 +41,10 @@
/* We let the MMU do all checking */
static inline int access_ok(int type, const void *addr, unsigned long size)
{
- return ((unsigned long) addr < 0x10f00000); /* need final decision - Tony */
+ return ((unsigned long)addr < 0x10f00000); /* need final decision - Tony */
}
-static inline int verify_area(int type, const void *addr,
- unsigned long size)
+static inline int verify_area(int type, const void *addr, unsigned long size)
{
return access_ok(type, addr, size) ? 0 : -EFAULT;
}
@@ -173,12 +172,11 @@ static inline int bad_user_access_length(void)
* Copy a null terminated string from userspace.
*/
-static inline long strncpy_from_user(char *dst, const char *src,
- long count)
+static inline long strncpy_from_user(char *dst, const char *src, long count)
{
char *tmp;
strncpy(dst, src, count);
- for (tmp = dst; *tmp && count > 0; tmp++, count--);
+ for (tmp = dst; *tmp && count > 0; tmp++, count--) ;
return (tmp - dst); /* DAVIDM should we count a NUL ? check getname */
}
diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h
new file mode 100644
index 0000000..7afc1a1
--- /dev/null
+++ b/include/configs/bf533-ezkit.h
@@ -0,0 +1,228 @@
+/*
+ * U-boot - Configuration file for BF533 EZKIT board
+ */
+
+#ifndef __CONFIG_EZKIT533_H__
+#define __CONFIG_EZKIT533_H__
+
+#define CONFIG_BAUDRATE 57600
+#define CONFIG_STAMP 1
+
+#define CONFIG_BOOTDELAY 5
+#define CFG_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */
+
+#define CFG_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_LOADADDR 0x01000000 /* default load address */
+#define CONFIG_BOOTCOMMAND "tftp $(loadaddr) linux"
+//#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"
+
+#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_SMC91111_BASE 0x20310300
+
+#if 0
+#define CONFIG_MII
+#define CFG_DISCOVER_PHY
+#endif
+
+#define CONFIG_RTC_BFIN 1
+#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
+
+/*
+ * Boot Mode Set
+ * Blackfin can support several boot modes
+ */
+#define BF533_BYPASS_BOOT 0x0001 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */
+#define BF533_PARA_BOOT 0x0002 /* Bootmode 1: Boot from 8-bit or 16-bit flash */
+#define BF533_SPI_BOOT 0x0004 /* Bootmode 3: Boot from SPI flash */
+/* Define the boot mode */
+#define BFIN_BOOT_MODE BF533_BYPASS_BOOT
+//#define BFIN_BOOT_MODE BF533_SPI_BOOT
+
+#define CONFIG_PANIC_HANG 1
+
+#define ADSP_BF531 0x31
+#define ADSP_BF532 0x32
+#define ADSP_BF533 0x33
+#define BFIN_CPU ADSP_BF533
+
+/* This sets the default state of the cache on U-Boot's boot */
+#define CONFIG_ICACHE_ON
+#define CONFIG_DCACHE_ON
+
+/* Define where the uboot will be loaded by on-chip boot rom */
+#define APP_ENTRY 0x00001000
+
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 27000000
+/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
+/* 1=CLKIN/2 */
+#define CONFIG_CLKIN_HALF 0
+/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
+/* 1=bypass PLL */
+#define CONFIG_PLL_BYPASS 0
+/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
+/* Values can range from 1-64 */
+#define CONFIG_VCO_MULT 22
+/* CONFIG_CCLK_DIV controls what the core clock divider is */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 5
+/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
+/* Values can range from 2-65535 */
+/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
+#define CONFIG_SPI_BAUD 2
+#define CONFIG_SPI_BAUD_INITBLOCK 4
+
+#if ( CONFIG_CLKIN_HALF == 0 )
+#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
+#else
+#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
+#endif
+
+#if (CONFIG_PLL_BYPASS == 0)
+#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
+#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
+#else
+#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
+#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
+#endif
+
+#define CONFIG_MEM_SIZE 32 /* 128, 64, 32, 16 */
+#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */
+#define CONFIG_MEM_MT48LC16M16A2TG_75 1
+
+#define CONFIG_LOADS_ECHO 1
+
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_PING | \
+ CFG_CMD_ELF | \
+ CFG_CMD_I2C | \
+ CFG_CMD_JFFS2 | \
+ CFG_CMD_DATE)
+#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off console=ttyBF0,57600"
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CFG_PROMPT "ezkit> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
+#define CFG_MEMTEST_END ( (CONFIG_MEM_SIZE - 1) * 1024 * 1024) /* 1 ... 31 MB in DRAM */
+#define CFG_LOAD_ADDR 0x01000000 /* default load address */
+#define CFG_HZ 1000 /* decrementer freq: 10 ms ticks */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024)
+#define CFG_FLASH_BASE 0x20000000
+
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+#define CFG_GBL_DATA_SIZE 0x4000
+#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
+#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
+
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CFG_FLASH0_BASE 0x20000000
+#define CFG_FLASH1_BASE 0x20200000
+#define CFG_FLASH2_BASE 0x20280000
+#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 40 /* max number of sectors on one chip */
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR 0x20020000
+#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */
+
+/* JFFS Partition offset set */
+#define CFG_JFFS2_FIRST_BANK 0
+#define CFG_JFFS2_NUM_BANKS 1
+/* 512k reserved for u-boot */
+#define CFG_JFFS2_FIRST_SECTOR 11
+
+
+/*
+ * Stack sizes
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+
+#define POLL_MODE 1
+#define FLASH_TOT_SECT 40
+#define FLASH_SIZE 0x220000
+#define CFG_FLASH_SIZE 0x220000
+
+/*
+ * Initialize PSD4256 registers for using I2C
+ */
+#define CONFIG_MISC_INIT_R
+
+/*
+ * I2C settings
+ * By default PF1 is used as SDA and PF0 as SCL on the Stamp board
+ */
+#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PF_SCL PF0
+#define PF_SDA PF1
+
+#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;")
+#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
+#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
+#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
+#define I2C_SDA(bit) if(bit) { \
+ *pFIO_FLAG_S = PF_SDA; \
+ asm("ssync;"); \
+ } \
+ else { \
+ *pFIO_FLAG_C = PF_SDA; \
+ asm("ssync;"); \
+ }
+#define I2C_SCL(bit) if(bit) { \
+ *pFIO_FLAG_S = PF_SCL; \
+ asm("ssync;"); \
+ } \
+ else { \
+ *pFIO_FLAG_C = PF_SCL; \
+ asm("ssync;"); \
+ }
+#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
+
+#define CFG_I2C_SPEED 50000
+#define CFG_I2C_SLAVE 0xFE
+
+#define CFG_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */
+
+/* 0xFF, 0x7BB07BB0, 0x22547BB0 */
+/* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
+#define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \
+ ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN)
+#define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \
+ B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN)
+*/
+#define AMGCTLVAL 0xFF
+#define AMBCTL0VAL 0x7BB07BB0
+#define AMBCTL1VAL 0xFFC27BB0
+
+#define CONFIG_VDSP 1
+
+#ifdef CONFIG_VDSP
+#define ET_EXEC_VDSP 0x8
+#define SHT_STRTAB_VDSP 0x1
+#define ELFSHDRSIZE_VDSP 0x2C
+#define VDSP_ENTRY_ADDR 0xFFA00000
+#endif
+
+#endif
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
new file mode 100644
index 0000000..353a43c
--- /dev/null
+++ b/include/configs/bf533-stamp.h
@@ -0,0 +1,475 @@
+/*
+ * U-boot - Configuration file for BF533 STAMP board
+ */
+
+#ifndef __CONFIG_STAMP_H__
+#define __CONFIG_STAMP_H__
+
+#define CONFIG_STAMP 1
+#define CONFIG_RTC_BFIN 1
+#define CONFIG_BF533 1
+/*
+ * Boot Mode Set
+ * Blackfin can support several boot modes
+ */
+#define BF533_BYPASS_BOOT 0x0001 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */
+#define BF533_PARA_BOOT 0x0002 /* Bootmode 1: Boot from 8-bit or 16-bit flash */
+#define BF533_SPI_BOOT 0x0004 /* Bootmode 3: Boot from SPI flash */
+/* Define the boot mode */
+#define BFIN_BOOT_MODE BF533_BYPASS_BOOT
+//#define BFIN_BOOT_MODE BF533_SPI_BOOT
+
+#define CONFIG_PANIC_HANG 1
+
+#define ADSP_BF531 0x31
+#define ADSP_BF532 0x32
+#define ADSP_BF533 0x33
+#define BFIN_CPU ADSP_BF533
+
+/* This sets the default state of the cache on U-Boot's boot */
+#define CONFIG_ICACHE_ON
+#define CONFIG_DCACHE_ON
+
+/* Define where the uboot will be loaded by on-chip boot rom */
+#define APP_ENTRY 0x00001000
+
+/*
+ * Stringize definitions - needed for environmental settings
+ */
+#define STRINGIZE2(x) #x
+#define STRINGIZE(x) STRINGIZE2(x)
+
+/*
+ * Board settings
+ *
+ */
+#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_SMC91111_BASE 0x20300300
+
+/* FLASH/ETHERNET uses the same address range */
+#define SHARED_RESOURCES 1
+
+/* Is I2C bit-banged? */
+#define CONFIG_SOFT_I2C 1
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PF_SCL PF3
+#define PF_SDA PF2
+
+/*
+ * Video splash screen support
+ */
+#define CONFIG_VIDEO 0
+
+#define CONFIG_VDSP 1
+
+/*
+ * Clock settings
+ *
+ */
+
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 11059200
+/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
+/* 1=CLKIN/2 */
+#define CONFIG_CLKIN_HALF 0
+/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
+/* 1=bypass PLL */
+#define CONFIG_PLL_BYPASS 0
+/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
+/* Values can range from 1-64 */
+#define CONFIG_VCO_MULT 36
+/* CONFIG_CCLK_DIV controls what the core clock divider is */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 5
+/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
+/* Values can range from 2-65535 */
+/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
+#define CONFIG_SPI_BAUD 2
+
+#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
+#define CONFIG_SPI_BAUD_INITBLOCK 4
+#endif
+
+
+/*
+ * Network settings
+ *
+ */
+
+#if (CONFIG_DRIVER_SMC91111)
+#if 0
+#define CONFIG_MII
+#endif
+
+/* network support */
+#define CONFIG_IPADDR 192.168.0.15
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_SERVERIP 192.168.0.2
+#define CONFIG_HOSTNAME STAMP
+#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs
+
+/* To remove hardcoding and enable MAC storage in EEPROM */
+/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
+#endif /* CONFIG_DRIVER_SMC91111 */
+
+/*
+ * Flash settings
+ *
+ */
+
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CFG_FLASH_CFI_AMD_RESET
+
+#define CFG_FLASH_BASE 0x20000000
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
+
+#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR 0x20004000
+#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
+#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
+#define CFG_ENV_IS_IN_EEPROM 1
+#define CFG_ENV_OFFSET 0x4000
+#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x12A) /* 0x12A is the length of LDR file header */
+#endif
+
+#define CFG_ENV_SIZE 0x2000
+#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
+#define ENV_IS_EMBEDDED
+
+#define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */
+#define CFG_FLASH_ERASEBLOCK_TOUT 5000 /* Timeout for Block Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
+
+/* JFFS Partition offset set */
+#define CFG_JFFS2_FIRST_BANK 0
+#define CFG_JFFS2_NUM_BANKS 1
+/* 512k reserved for u-boot */
+#define CFG_JFFS2_FIRST_SECTOR 11
+
+/*
+ * following timeouts shall be used once the
+ * Flash real protection is enabled
+ */
+#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
+#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
+
+/*
+ * SDRAM settings & memory map
+ *
+ */
+
+#define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */
+#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */
+#define CONFIG_MEM_MT48LC64M4A2FB_7E 1
+
+#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
+#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
+#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
+#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
+#endif
+
+#define CFG_SDRAM_BASE 0x00000000
+
+#define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 *1024)
+#define CFG_MEMTEST_END (CFG_MAX_RAM_SIZE - 0x80000 - 1)
+#define CONFIG_LOADADDR 0x01000000
+
+#define CFG_LOAD_ADDR CONFIG_LOADADDR
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CFG_GBL_DATA_SIZE 0x4000 /* Reserve 16k for Global Data */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+
+#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - 0x40000)
+#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
+#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
+
+/* Check to make sure everything fits in SDRAM */
+#if ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) > CFG_MAX_RAM_SIZE)
+ #error Memory Map does not fit into configuration
+#endif
+
+#if ( CONFIG_CLKIN_HALF == 0 )
+#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
+#else
+#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
+#endif
+
+#if (CONFIG_PLL_BYPASS == 0)
+#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
+#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
+#else
+#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
+#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
+#endif
+
+#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
+#if (CONFIG_SCLK_HZ / (2*CONFIG_SPI_BAUD) > 20000000)
+#define CONFIG_SPI_FLASH_FAST_READ 1 /* Needed if SPI_CLK > 20 MHz */
+#else
+#undef CONFIG_SPI_FLASH_FAST_READ
+#endif
+#endif
+/*
+ * Command settings
+ *
+ */
+
+#define CFG_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING 1
+
+#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
+#define CFG_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */
+#endif
+ /* configuration lookup from the BOOTP/DHCP server, */
+ /* but not try to load any image using TFTP */
+
+#define CONFIG_BOOTDELAY 5
+#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
+#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
+#define CONFIG_BOOTCOMMAND "run ramboot"
+#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
+#define CONFIG_BOOTCOMMAND "eeprom read 0x1000000 0x100000 0x180000;icache on;dcache on;bootm 0x1000000"
+#endif
+
+#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
+
+#if (CONFIG_DRIVER_SMC91111)
+#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \
+ CFG_CMD_PING | \
+ CFG_CMD_ELF | \
+ CFG_CMD_CACHE | \
+ CFG_CMD_JFFS2 | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_DATE)
+
+#else
+#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \
+ CFG_CMD_ELF | \
+ CFG_CMD_CACHE | \
+ CFG_CMD_JFFS2 | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_DATE)
+
+#endif
+
+#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
+#if (CONFIG_DRIVER_SMC91111)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
+ "$(rootpath) console=ttyBF0,57600\0" \
+ "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
+ "$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
+ "ramboot=tftpboot $(loadaddr) linux; " \
+ "run ramargs;run addip;bootelf\0" \
+ "nfsboot=tftpboot $(loadaddr) linux; " \
+ "run nfsargs;run addip;bootelf\0" \
+ "flashboot=bootm 0x20100000\0" \
+ "update=tftpboot $(loadaddr) u-boot.bin; " \
+ "protect off 0x20000000 0x2003FFFF; erase 0x20000000 0x2003FFFF;" \
+ "cp.b $(loadaddr) 0x20000000 $(filesize)\0" \
+ ""
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
+ "flashboot=bootm 0x20100000\0" \
+ ""
+#endif
+
+#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
+ "$(rootpath) console=ttyBF0,57600\0" \
+ "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
+ "$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
+ "ramboot=tftpboot $(loadaddr) linux; " \
+ "run ramargs;run addip;bootelf\0" \
+ "nfsboot=tftpboot $(loadaddr) linux; " \
+ "run nfsargs;run addip;bootelf\0" \
+ "flashboot=bootm 0x20100000\0" \
+ "update=tftpboot $(loadaddr) u-boot.ldr;" \
+ "eeprom write $(loadaddr) 0x0 $(filesize);\0"\
+ ""
+#endif
+
+#ifdef CONFIG_SOFT_I2C
+#if (!CONFIG_SOFT_I2C)
+#undef CONFIG_SOFT_I2C
+#endif
+#endif
+
+#if (CONFIG_SOFT_I2C)
+#define CONFIG_COMMANDS2 CFG_CMD_I2C
+#else
+#define CONFIG_COMMANDS2 0
+#endif /* CONFIG_SOFT_I2C */
+
+#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
+#define CONFIG_COMMANDS ( CONFIG_COMMANDS1 | CONFIG_COMMANDS2 | CFG_CMD_DHCP)
+#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
+#define CONFIG_COMMANDS ( CONFIG_COMMANDS1 | CONFIG_COMMANDS2)
+#endif
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Console settings
+ *
+ */
+
+#define CONFIG_BAUDRATE 57600
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
+#if (BFIN_CPU == ADSP_BF531)
+#define CFG_PROMPT "serial_bf531> " /* Monitor Command Prompt */
+#elif (BFIN_CPU == ADSP_BF532)
+#define CFG_PROMPT "serial_bf532> " /* Monitor Command Prompt */
+#else
+#define CFG_PROMPT "serial_bf533> " /* Monitor Command Prompt */
+#endif
+#else
+#if (BFIN_CPU == ADSP_BF531)
+#define CFG_PROMPT "bf531> " /* Monitor Command Prompt */
+#elif (BFIN_CPU == ADSP_BF532)
+#define CFG_PROMPT "bf532> " /* Monitor Command Prompt */
+#else
+#define CFG_PROMPT "bf533> " /* Monitor Command Prompt */
+#endif
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_LOADS_ECHO 1
+
+/*
+ * I2C settings
+ * By default PF2 is used as SDA and PF3 as SCL on the Stamp board
+ */
+#if (CONFIG_SOFT_I2C)
+
+#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;")
+#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
+#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
+#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
+#define I2C_SDA(bit) if(bit) { \
+ *pFIO_FLAG_S = PF_SDA; \
+ asm("ssync;"); \
+ } \
+ else { \
+ *pFIO_FLAG_C = PF_SDA; \
+ asm("ssync;"); \
+ }
+#define I2C_SCL(bit) if(bit) { \
+ *pFIO_FLAG_S = PF_SCL; \
+ asm("ssync;"); \
+ } \
+ else { \
+ *pFIO_FLAG_C = PF_SCL; \
+ asm("ssync;"); \
+ }
+#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
+
+#define CFG_I2C_SPEED 50000
+#define CFG_I2C_SLAVE 0xFE
+#endif /* CONFIG_SOFT_I2C */
+
+/*
+ * Compact Flash settings
+ */
+
+/* Enabled below option for CF support */
+/* #define CONFIG_STAMP_CF 1 */
+
+#if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE)
+
+#define CONFIG_MISC_INIT_R 1
+#define CONFIG_DOS_PARTITION 1
+/*
+ * IDE/ATA stuff
+ */
+#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
+#undef CONFIG_IDE_LED /* no led for ide supported */
+#undef CONFIG_IDE_RESET /* no reset for ide supported */
+
+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
+#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define CFG_ATA_BASE_ADDR 0x20200000
+#define CFG_ATA_IDE0_OFFSET 0x0000
+
+#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
+#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
+#define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */
+
+#define CFG_ATA_STRIDE 2
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CFG_HZ 1000 /* 1ms time tick */
+
+#define CFG_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */
+
+#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
+
+#define CONFIG_SPI
+
+#ifdef CONFIG_VIDEO
+#if (CONFIG_VIDEO)
+#define CONFIG_SPLASH_SCREEN 1
+#define CONFIG_SILENT_CONSOLE 1
+#else
+#undef CONFIG_VIDEO
+#endif
+#endif
+
+/*
+ * FLASH organization and environment definitions
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/* 0xFF, 0xBBC3BBc3, 0x99B39983 */
+/*#define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
+#define AMBCTL0VAL (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \
+ B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN)
+#define AMBCTL1VAL (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \
+ B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN)
+*/
+#define AMGCTLVAL 0xFF
+#define AMBCTL0VAL 0xBBC3BBC3
+#define AMBCTL1VAL 0x99B39983
+#define CF_AMBCTL1VAL 0x99B3ffc2
+
+#ifdef CONFIG_VDSP
+#define ET_EXEC_VDSP 0x8
+#define SHT_STRTAB_VDSP 0x1
+#define ELFSHDRSIZE_VDSP 0x2C
+#define VDSP_ENTRY_ADDR 0xFFA00000
+#endif
+
+
+#endif
diff --git a/include/configs/ezkit533.h b/include/configs/ezkit533.h
deleted file mode 100644
index 5eda673..0000000
--- a/include/configs/ezkit533.h
+++ /dev/null
@@ -1,188 +0,0 @@
-#ifndef __CONFIG_EZKIT533_H__
-#define __CONFIG_EZKIT533_H__
-
-#define CFG_LONGHELP 1
-#define CONFIG_BAUDRATE 57600
-#define CONFIG_STAMP 1
-#define CONFIG_BOOTDELAY 5
-
-#define CONFIG_DRIVER_SMC91111 1
-#define CONFIG_SMC91111_BASE 0x20310300
-#if 0
-#define CONFIG_MII
-#define CFG_DISCOVER_PHY
-#endif
-
-#define CONFIG_RTC_BF533 1
-#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
-
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 27000000
-/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
-/* 1=CLKIN/2 */
-#define CONFIG_CLKIN_HALF 0
-/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
-/* 1=bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
-/* Values can range from 1-64 */
-#define CONFIG_VCO_MULT 22
-/* CONFIG_CCLK_DIV controls what the core clock divider is */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 5
-
-#if ( CONFIG_CLKIN_HALF == 0 )
-#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
-#else
-#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
-#endif
-
-#if (CONFIG_PLL_BYPASS == 0)
-#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
-#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
-#else
-#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
-#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
-#endif
-
-#define CONFIG_MEM_SIZE 32 /* 128, 64, 32, 16 */
-#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */
-#define CONFIG_MEM_MT48LC16M16A2TG_75 1
-
-#define CONFIG_LOADS_ECHO 1
-
-
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_PING | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_DATE)
-#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off"
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CFG_PROMPT "ezkit> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
-#define CFG_MEMTEST_END 0x01F00000 /* 1 ... 31 MB in DRAM */
-#define CFG_LOAD_ADDR 0x01000000 /* default load address */
-#define CFG_HZ 1000 /* decrementer freq: 10 ms ticks */
-#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#define CFG_SDRAM_BASE 0x00000000
-#define CFG_MAX_RAM_SIZE 0x02000000
-#define CFG_FLASH_BASE 0x20000000
-
-#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
-#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
-#define CFG_GBL_DATA_SIZE 0x4000
-#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
-#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
-
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-#define CFG_FLASH0_BASE 0x20000000
-#define CFG_FLASH1_BASE 0x20200000
-#define CFG_FLASH2_BASE 0x20280000
-#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 40 /* max number of sectors on one chip */
-
-#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_ADDR 0x20020000
-#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */
-
-/* JFFS Partition offset set */
-#define CFG_JFFS2_FIRST_BANK 0
-#define CFG_JFFS2_NUM_BANKS 1
-/* 512k reserved for u-boot */
-#define CFG_JFFS2_FIRST_SECTOR 11
-
-
-/*
- * Stack sizes
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-
-#define POLL_MODE 1
-#define FLASH_TOT_SECT 40
-#define FLASH_SIZE 0x220000
-#define CFG_FLASH_SIZE 0x220000
-
-/*
- * Initialize PSD4256 registers for using I2C
- */
-#define CONFIG_MISC_INIT_R
-
-/*
- * I2C settings
- * By default PF1 is used as SDA and PF0 as SCL on the Stamp board
- */
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PF_SCL PF0
-#define PF_SDA PF1
-
-#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;")
-#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
-#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
-#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
-#define I2C_SDA(bit) if(bit) { \
- *pFIO_FLAG_S = PF_SDA; \
- asm("ssync;"); \
- } \
- else { \
- *pFIO_FLAG_C = PF_SDA; \
- asm("ssync;"); \
- }
-#define I2C_SCL(bit) if(bit) { \
- *pFIO_FLAG_S = PF_SCL; \
- asm("ssync;"); \
- } \
- else { \
- *pFIO_FLAG_C = PF_SCL; \
- asm("ssync;"); \
- }
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-
-#define CFG_I2C_SPEED 50000
-#define CFG_I2C_SLAVE 0xFE
-
-
-#define __ADSPLPBLACKFIN__ 1
-#define __ADSPBF533__ 1
-
-/* 0xFF, 0x7BB07BB0, 0x22547BB0 */
-/* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
-#define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \
- ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN)
-#define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \
- B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN)
-*/
-#define AMGCTLVAL 0xFF
-#define AMBCTL0VAL 0x7BB07BB0
-#define AMBCTL1VAL 0xFFC27BB0
-
-#define CONFIG_VDSP 1
-
-#ifdef CONFIG_VDSP
-#define ET_EXEC_VDSP 0x8
-#define SHT_STRTAB_VDSP 0x1
-#define ELFSHDRSIZE_VDSP 0x2C
-#define VDSP_ENTRY_ADDR 0xFFA00000
-#endif
-
-#endif
diff --git a/include/configs/stamp.h b/include/configs/stamp.h
deleted file mode 100644
index 248ca70..0000000
--- a/include/configs/stamp.h
+++ /dev/null
@@ -1,333 +0,0 @@
-/*
- * U-boot - stamp.h Configuration file for STAMP board
- * having BF533 processor
- *
- * Copyright (c) 2005 blackfin.uclinux.org
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_STAMP_H__
-#define __CONFIG_STAMP_H__
-
-/*
- * Board settings
- *
- */
-
-#define __ADSPLPBLACKFIN__ 1
-#define __ADSPBF533__ 1
-#define CONFIG_STAMP 1
-#define CONFIG_RTC_BF533 1
-
-/* FLASH/ETHERNET uses the same address range */
-#define SHARED_RESOURCES 1
-
-#define CONFIG_VDSP 1
-
-/*
- * Clock settings
- *
- */
-
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 11059200
-/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
-/* 1=CLKIN/2 */
-#define CONFIG_CLKIN_HALF 0
-/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
-/* 1=bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
-/* Values can range from 1-64 */
-#define CONFIG_VCO_MULT 45
-/* CONFIG_CCLK_DIV controls what the core clock divider is */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 6
-
-/*
- * Network Settings
- */
-/* network support */
-#define CONFIG_IPADDR 192.168.0.15
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_GATEWAYIP 192.168.0.1
-#define CONFIG_SERVERIP 192.168.0.2
-#define CONFIG_HOSTNAME STAMP
-#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs
-
-/* To remove hardcoding and enable MAC storage in EEPROM */
-/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
-
-/*
- * Command settings
- *
- */
-
-#define CFG_LONGHELP 1
-
-#define CONFIG_BOOTDELAY 5
-#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
-#define CONFIG_BOOTCOMMAND "run ramboot"
-#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
-
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_PING | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_CACHE | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_DATE)
-#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "ramargs=setenv bootargs root=/dev/mtdblock0 rw\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):eth0:off\0" \
- "ramboot=tftpboot 0x1000000 linux;" \
- "run ramargs;run addip;bootelf\0" \
- "nfsboot=tftpboot 0x1000000 linux;" \
- "run nfsargs;run addip;bootelf\0" \
- "flashboot=bootm 0x20100000\0" \
- ""
-
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Console settings
- *
- */
-
-#define CONFIG_BAUDRATE 57600
-#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
-#define CFG_PROMPT "stamp>" /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_LOADS_ECHO 1
-
-/*
- * Network settings
- *
- */
-
-#define CONFIG_DRIVER_SMC91111 1
-#define CONFIG_SMC91111_BASE 0x20300300
-/* To remove hardcoding and enable MAC storage in EEPROM */
-/* #define HARDCODE_MAC 1 */
-
-/*
- * Flash settings
- *
- */
-
-#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CFG_FLASH_CFI_AMD_RESET
-
-#define CFG_ENV_IS_IN_FLASH 1
-
-#define CFG_FLASH_BASE 0x20000000
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
-
-#define CFG_ENV_ADDR 0x20020000
-#define CFG_ENV_SIZE 0x10000
-#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */
-
-#define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */
-#define CFG_FLASH_ERASEBLOCK_TOUT 5000 /* Timeout for Block Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
-
-/* JFFS Partition offset set */
-#define CFG_JFFS2_FIRST_BANK 0
-#define CFG_JFFS2_NUM_BANKS 1
-/* 512k reserved for u-boot */
-#define CFG_JFFS2_FIRST_SECTOR 11
-
-/*
- * following timeouts shall be used once the
- * Flash real protection is enabled
- */
-#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
-#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
-
-/*
- * I2C settings
- * By default PF2 is used as SDA and PF3 as SCL on the Stamp board
- */
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PF_SCL PF3
-#define PF_SDA PF2
-
-#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;")
-#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
-#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
-#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
-#define I2C_SDA(bit) if(bit) { \
- *pFIO_FLAG_S = PF_SDA; \
- asm("ssync;"); \
- } \
- else { \
- *pFIO_FLAG_C = PF_SDA; \
- asm("ssync;"); \
- }
-#define I2C_SCL(bit) if(bit) { \
- *pFIO_FLAG_S = PF_SCL; \
- asm("ssync;"); \
- } \
- else { \
- *pFIO_FLAG_C = PF_SCL; \
- asm("ssync;"); \
- }
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-
-#define CFG_I2C_SPEED 50000
-#define CFG_I2C_SLAVE 0xFE
-
-/*
- * Compact Flash settings
- */
-
-/* Enabled below option for CF support */
-/* #define CONFIG_STAMP_CF 1 */
-
-#if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE)
-
-#define CONFIG_MISC_INIT_R 1
-#define CONFIG_DOS_PARTITION 1
-
-/*
- * IDE/ATA stuff
- */
-#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
-#undef CONFIG_IDE_LED /* no led for ide supported */
-#undef CONFIG_IDE_RESET /* no reset for ide supported */
-
-#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
-#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
-
-#define CFG_ATA_BASE_ADDR 0x20200000
-#define CFG_ATA_IDE0_OFFSET 0x0000
-
-#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
-#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
-#define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */
-
-#define CFG_ATA_STRIDE 2
-#endif
-
-/*
- * SDRAM settings
- *
- */
-
-#define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */
-#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */
-#define CONFIG_MEM_MT48LC64M4A2FB_7E 1
-
-#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
-#define CFG_MEMTEST_END 0x07EFFFFF /* 1 ... 127 MB in DRAM */
-#define CFG_LOAD_ADDR 0x01000000 /* default load address */
-
-#define CFG_SDRAM_BASE 0x00000000
-#define CFG_MAX_RAM_SIZE 0x08000000
-
-#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
-
-#if ( CONFIG_CLKIN_HALF == 0 )
-#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
-#else
-#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
-#endif
-
-#if (CONFIG_PLL_BYPASS == 0)
-#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
-#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
-#else
-#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
-#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_HZ 1000 /* 1ms time tick */
-
-#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
-#define CFG_GBL_DATA_SIZE 0x4000
-#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
-#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
-
-#define CFG_LARGE_IMAGE_LEN 0x4000000 /* Large Image Length, set to 64 Meg */
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
-
-/*
- * Stack sizes
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-
-/*
- * FLASH organization and environment definitions
- */
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/* 0xFF, 0xBBC3BBc3, 0x99B39983 */
-/*#define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
-#define AMBCTL0VAL (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \
- B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN)
-#define AMBCTL1VAL (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \
- B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN)
-*/
-#define AMGCTLVAL 0xFF
-#define AMBCTL0VAL 0xBBC3BBC3
-#define AMBCTL1VAL 0x99B39983
-#define CF_AMBCTL1VAL 0x99B3ffc2
-
-#ifdef CONFIG_VDSP
-#define ET_EXEC_VDSP 0x8
-#define SHT_STRTAB_VDSP 0x1
-#define ELFSHDRSIZE_VDSP 0x2C
-#define VDSP_ENTRY_ADDR 0xFFA00000
-#endif
-
-#endif