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authorSteve Sakoman <steve@sakoman.com>2010-06-08 13:07:46 -0700
committerSandeep Paulraj <s-paulraj@ti.com>2010-07-05 20:00:15 -0400
commit3e76d62a664bb258f686be7f4517e19badfefea5 (patch)
tree391cb7e8ae14fe2cf3ce85fb483e61f8cf1ea022 /include
parent938717cee195159950cc4e3b16f4e4f7148421a2 (diff)
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ARMV7: Add support for TI OMAP4430 SDP
OMAP4430 SDP is a reference board based on OMAP4430, an ARMV7 Cortex A9 CPU This patch adds basic support for booting the board. It includes i2c and mmc support. It assumes U-boot is loaded to SDRAM with the help of another small bootloader (x-load) running from SRAM. U-boot currently relies on x-load for clock, mux, and SDRAM initialization Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Steve Sakoman <steve@sakoman.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Diffstat (limited to 'include')
-rw-r--r--include/configs/omap4_sdp4430.h221
1 files changed, 221 insertions, 0 deletions
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
new file mode 100644
index 0000000..8121554
--- /dev/null
+++ b/include/configs/omap4_sdp4430.h
@@ -0,0 +1,221 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated.
+ * Aneesh V <aneesh@ti.com>
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * Configuration settings for the TI SDP4430 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP44XX 1 /* which is a 44XX */
+#define CONFIG_OMAP4430 1 /* which is in a 4430 */
+#define CONFIG_4430SDP 1 /* working with SDP */
+
+/* Get CPU defs */
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap4.h>
+
+/* Display CPU and Board Info */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+/* Keep L2 Cache Disabled */
+#define CONFIG_L2_OFF 1
+
+/* Clock Defines */
+#define V_OSCK 38400000 /* Clock output from T2 */
+#define V_SCLK V_OSCK
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_REVISION_TAG 1
+
+/*
+ * Size of malloc() pool
+ * Total Size Environment - 256k
+ * Malloc - add 256k
+ */
+#define CONFIG_ENV_SIZE (256 << 10)
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
+ /* initial data */
+/* Vector Base */
+#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * serial port - NS16550 compatible
+ */
+#define V_NS16550_CLK 48000000
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 UART3_BASE
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+
+/* I2C */
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_BUS 0
+#define CONFIG_SYS_I2C_BUS_SELECT 1
+#define CONFIG_DRIVER_OMAP34XX_I2C 1
+#define CONFIG_I2C_MULTI_BUS 1
+
+/* MMC */
+#define CONFIG_MMC 1
+#define CONFIG_OMAP3_MMC 1
+#define CONFIG_SYS_MMC_SET_DEV 1
+#define CONFIG_DOS_PARTITION 1
+
+/* Flash */
+#define CONFIG_SYS_NO_FLASH 1
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+/* Enabled commands */
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+
+/* Disabled commands */
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_IMLS /* List all found images */
+
+/*
+ * Enabling relocation of u-boot by default
+ * Relocation can be skipped if u-boot is copied to the TEXT_BASE
+ */
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Environment setup
+ */
+
+/* allow overwriting serial config and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x82000000\0" \
+ "console=ttyS2,115200n8\0" \
+ "mmcdev=1\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext3 rootwait\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
+ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+ "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
+ "source ${loadaddr}\0" \
+ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+ "mmcboot=echo Booting from mmc${mmcdev} ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmc init ${mmcdev}; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "else run nandboot; " \
+ "fi; " \
+ "fi; " \
+ "fi"
+
+#define CONFIG_AUTO_COMPLETE 1
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "OMAP4430 SDP # "
+#define CONFIG_SYS_CBSIZE 256
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+/*
+ * memtest setup
+ */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (32 << 20))
+
+/* Default load address */
+#define CONFIG_SYS_LOAD_ADDR 0x80000000
+
+/* Use General purpose timer 1 */
+#define CONFIG_SYS_TIMERBASE GPT1_BASE
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */
+#endif
+
+/*
+ * SDRAM Memory Map
+ * Even though we use two CS all the memory
+ * is mapped to one contiguous block
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+
+#endif /* __CONFIG_H */