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authorAneesh V <aneesh@ti.com>2011-06-16 23:30:47 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2011-07-04 10:55:25 +0200
commit2c451f7831208741d0ff7ca6046cffcd9ee49def (patch)
treeec885d6ce9bc97eca3128e83e9af35c5b063ffe1 /include
parent4c93da7c392737f2036130c240e2b4bea773d703 (diff)
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armv7: cache maintenance operations for armv7
- Add a framework for layered cache maintenance - separate out SOC specific outer cache maintenance from maintenance of caches known to CPU - Add generic ARMv7 cache maintenance operations that affect all caches known to ARMv7 CPUs. For instance in Cortex-A8 these opertions will affect both L1 and L2 caches. In Cortex-A9 these will affect only L1 cache - D-cache operations supported: - Invalidate entire D-cache - Invalidate D-cache range - Flush(clean & invalidate) entire D-cache - Flush D-cache range - I-cache operations supported: - Invalidate entire I-cache - Add maintenance functions for TLB, branch predictor array etc. - Enable -march=armv7-a so that armv7 assembly instructions can be used Signed-off-by: Aneesh V <aneesh@ti.com>
Diffstat (limited to 'include')
-rw-r--r--include/common.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/include/common.h b/include/common.h
index 1e21b7a..2c8513a 100644
--- a/include/common.h
+++ b/include/common.h
@@ -413,6 +413,7 @@ void icache_disable(void);
int dcache_status (void);
void dcache_enable (void);
void dcache_disable(void);
+void mmu_disable(void);
void relocate_code (ulong, gd_t *, ulong) __attribute__ ((noreturn));
ulong get_endaddr (void);
void trap_init (ulong);
@@ -611,9 +612,11 @@ ulong video_setmem (ulong);
/* arch/$(ARCH)/lib/cache.c */
void flush_cache (unsigned long, unsigned long);
+void flush_dcache_all(void);
void flush_dcache_range(unsigned long start, unsigned long stop);
void invalidate_dcache_range(unsigned long start, unsigned long stop);
-
+void invalidate_dcache_all(void);
+void invalidate_icache_all(void);
/* arch/$(ARCH)/lib/ticks.S */
unsigned long long get_ticks(void);