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| author | Wolfgang Denk <wd@denx.de> | 2008-11-02 16:14:22 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-11-02 16:14:22 +0100 |
| commit | 3cbd823116ea8b7c654e275a8c2fca87cd1f5dc5 (patch) | |
| tree | 8cda4daa32f477368ab3690cdfc879c610ef1b03 /include | |
| parent | 3ec53148eb68ddfb0c3311fb4c06cd2bd0ef3eeb (diff) | |
| download | u-boot-imx-3cbd823116ea8b7c654e275a8c2fca87cd1f5dc5.zip u-boot-imx-3cbd823116ea8b7c654e275a8c2fca87cd1f5dc5.tar.gz u-boot-imx-3cbd823116ea8b7c654e275a8c2fca87cd1f5dc5.tar.bz2 | |
Coding Style cleanup, update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/MPC8572DS.h | 63 | ||||
| -rw-r--r-- | include/configs/fx12mm.h | 13 |
2 files changed, 36 insertions, 40 deletions
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 244ecc2..c3693b8 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -158,7 +158,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * Localbus non-cacheable * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable - * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable + * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable @@ -268,50 +268,49 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); CONFIG_SYS_NAND_BASE + 0x80000,\ CONFIG_SYS_NAND_BASE + 0xC0000} #define CONFIG_SYS_MAX_NAND_DEVICE 4 -#define NAND_MAX_CHIPS 1 +#define NAND_MAX_CHIPS 1 #define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_CMD_NAND 1 -#define CONFIG_NAND_FSL_ELBC 1 +#define CONFIG_CMD_NAND 1 +#define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) /* NAND flash config */ #define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ - | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ - | BR_PS_8 /* Port Size = 8 bit */ \ - | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V) /* valid */ -#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ - | OR_FCM_PGS /* Large Page*/ \ - | OR_FCM_CSCT \ - | OR_FCM_CST \ - | OR_FCM_CHT \ - | OR_FCM_SCY_1 \ - | OR_FCM_TRLX \ - | OR_FCM_EHTR) + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ + | OR_FCM_PGS /* Large Page*/ \ + | OR_FCM_CSCT \ + | OR_FCM_CST \ + | OR_FCM_CHT \ + | OR_FCM_SCY_1 \ + | OR_FCM_TRLX \ + | OR_FCM_EHTR) #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)\ - | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ - | BR_PS_8 /* Port Size = 8 bit */ \ - | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ #define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ - | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ - | BR_PS_8 /* Port Size = 8 bit */ \ - | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ #define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0xC0000)\ - | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ - | BR_PS_8 /* Port Size = 8 bit */ \ - | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ - + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ /* Serial Port - controlled on board with jumper J8 diff --git a/include/configs/fx12mm.h b/include/configs/fx12mm.h index 8481c33..5844567 100644 --- a/include/configs/fx12mm.h +++ b/include/configs/fx12mm.h @@ -25,11 +25,10 @@ * MA 02111-1307 USA */ - /* - Configuration file for the Virtex4FX12 Minimodul by Avnet/Memec, - see http://www.em.avnet.com -*/ + * Configuration file for the Virtex4FX12 Minimodul by Avnet/Memec, + * see http://www.em.avnet.com + */ #ifndef __CONFIG_FX12_H #define __CONFIG_FX12_H @@ -54,7 +53,7 @@ /*Misc*/ #define CONFIG_SYS_PROMPT "FX12MM:/# " /* Monitor Command Prompt */ -#define CONFIG_PREBOOT "echo U-Boot is up and runnining;" +#define CONFIG_PREBOOT "echo U-Boot is up and running;" /*Flash*/ #define CONFIG_SYS_FLASH_SIZE (4*1024*1024) @@ -62,8 +61,6 @@ #define MTDIDS_DEFAULT "nor0=fx12mm-flash" #define MTDPARTS_DEFAULT "mtdparts=fx12mm-flash:-(user)" - #include "configs/xilinx-ppc405.h" -#endif /* __CONFIG_H */ - +#endif /* __CONFIG_H */ |