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| author | Priyanka Jain <Priyanka.Jain@freescale.com> | 2014-01-03 11:24:55 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-01-21 13:35:20 -0800 |
| commit | 2eb3ac7fe8ee29b2edfd7e0309115c2fc6875f95 (patch) | |
| tree | 1a174ed13fc1cb7972bf6f1c7a33de339ce86791 /include | |
| parent | b44bd2c73c4cfb6e3b9e7f8cf987e8e39aa74a0b (diff) | |
| download | u-boot-imx-2eb3ac7fe8ee29b2edfd7e0309115c2fc6875f95.zip u-boot-imx-2eb3ac7fe8ee29b2edfd7e0309115c2fc6875f95.tar.gz u-boot-imx-2eb3ac7fe8ee29b2edfd7e0309115c2fc6875f95.tar.bz2 | |
powerpc/t1040qds: Update DDR initialization related settings
Update following DDR related settings for T1040QDS
-Correct number of chip selects to two as t1040qds supports
two Chip selects.
-Update board_specific_parameters udimm structure with settings
derived via calibration.
-Reduced I2C speed to 50KHz as DDR-SPD does not get reliably
read at 400KHz.
Verified the updated settings to be working fine with dual-ranked
Micron, MT18KSF51272AZ-1G6 DIMM at data rate 833MT/s, 1333MT/s and
1600MT/s.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/T1040QDS.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 7d0bc04..cfaac43 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -167,7 +167,7 @@ unsigned long get_board_ddr_clk(void); /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR3 @@ -414,9 +414,9 @@ unsigned long get_board_ddr_clk(void); /* I2C */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ -#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ +#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ +#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 |