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authorMarkus Klotzbücher <Markus Klotzbümk@pollux.denx.de>2006-03-06 13:45:42 +0100
committerMarkus Klotzbücher <mk@pollux.denx.de>2006-03-06 13:45:42 +0100
commitf9e029184be5ef550d05262e0f150d31fb09d19b (patch)
tree5109bf2a67225fb57ad0561ba3e31331ae65d7bc /include
parentbf7cac033b27589c7de71a5f37f0c8e872ad489a (diff)
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NAND finally working. Two bugs fixed:
* For READ_STATUS and READID commands always 8 bytes need to be read from NDDB. Otherwise they stay there and get send to flash as the first data word when writing. * In nand_base.c the oob variable is not reset so this->oob_buf is overwritten what eventually screws up the bad block descriptor table.
Diffstat (limited to 'include')
-rw-r--r--include/configs/delta.h10
1 files changed, 7 insertions, 3 deletions
diff --git a/include/configs/delta.h b/include/configs/delta.h
index 99ce0f6..3a94661 100644
--- a/include/configs/delta.h
+++ b/include/configs/delta.h
@@ -43,7 +43,7 @@
/*
* Size of malloc() pool
*/
-#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024)
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
@@ -164,7 +164,7 @@
*/
/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */
#define CONFIG_NEW_NAND_CODE
-#define CFG_NAND0_BASE 0x43100040 /* 0x10000000 */
+#define CFG_NAND0_BASE 0x0 /* 0x43100040 */ /* 0x10000000 */
#undef CFG_NAND1_BASE
#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE }
@@ -174,9 +174,13 @@
#define NAND_DELAY_US 25 /* mk@tbd: could be 0, I guess */
/* nand timeout values */
-#define CFG_NAND_PROG_ERASE_TO 300
+#define CFG_NAND_PROG_ERASE_TO 3000
#define CFG_NAND_OTHER_TO 100
#define CFG_NAND_SENDCMD_RETRY 3
+#define NAND_ALLOW_ERASE_ALL 1
+
+#define CONFIG_MTD_DEBUG
+#define CONFIG_MTD_DEBUG_VERBOSE 1
#define ADDR_COLUMN 1
#define ADDR_PAGE 2