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authorJeffrey Mann <mannj@embeddedplanet.com>2007-05-05 08:32:14 +0200
committerStefan Roese <sr@denx.de>2007-05-05 08:32:14 +0200
commite3b8c78bc2489c27ae020986ef0eaca684866cef (patch)
tree556626bd30e27d51d07265f25f7b32ca8ad6d2f0 /include
parentf544ff6656fca263ed1ebe39899b6d95da67c8b8 (diff)
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ppc4xx: Detect if the sysclk on Sequoia is 33 or 33.333 MHz
The AMCC Secquoia board has been changed in a new revision from using a 33.000 MHz clock to a 33.333 MHz system clock. A bit in the CPLD indicates the difference. This patch reads that bit and uses the correct clock speed for the board. This code is backward compatable will all prior boards. All prior boards will be read as 33.000. Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com> Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include')
-rw-r--r--include/configs/sequoia.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 1f19621..b7f79c2 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -38,7 +38,9 @@
#define CONFIG_440GRX 1 /* Specific PPC440GRx */
#endif
#define CONFIG_4xx 1 /* ... PPC4xx family */
-#define CONFIG_SYS_CLK_FREQ 33000000 /* external freq to pll */
+/* Detect Sequoia PLL input clock automatically via CPLD bit */
+#define CONFIG_SYS_CLK_FREQ ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \
+ 3333333 : 33000000)
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */