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authorAlison Wang <b18965@freescale.com>2014-10-17 15:26:33 +0800
committerYork Sun <yorksun@freescale.com>2014-11-24 09:27:23 -0800
commitc207ff612903389f8b32e377fe32be43e6efd8f7 (patch)
treeaec5085a78492690ae3a46b84aaa6de15c3345e1 /include
parent644bc7ec5cee3a93ecb3adc364be6374d3f60a27 (diff)
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arm: ls102xa: Remove bit reversing for SCFG registers
SCFG_SCFGREVCR is SCFG bit reverse register. This register must be written with 0xFFFFFFFF before writing to any other SCFG register. Then other SCFG register could be written in big-endian mode. Address: 157_0000h base + 200h offset = 157_0200h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15|16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 W/R SCFGREV Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0-31 SCFGREV SCFG Bit Reverse Control Filed 32'h 0000_0000 - No bit reverse is applied 32'h FFFF_FFFF - Bit reverse is applied; so 31:0 will be stored/read as 0:31 This patch removes the bit reversing for SCFG registers in u-boot. It will be implemented through PBI commands in RCW .pbi write 0x570200, 0xffffffff .end So other SCFG register could be written in big-endian mode in u-boot or kernel directly. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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