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authorYe.Li <B37916@freescale.com>2015-06-19 15:27:49 +0800
committerYe.Li <B37916@freescale.com>2015-06-19 17:15:35 +0800
commitc0fc92d28b133ddf053f39635cc9f745224f8111 (patch)
treeb432b9867bd8de1468471b1a21e93f986145a72d /include
parentd307893d5c62ba6f4172e526d4193c4c97b3fba6 (diff)
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MLK-11135-2 imx: mx6ul: Add MX6UL LPDDR2 ARM2 board support
Add MX6UL LPDDR2 ARM2 board BSP codes, supported peripherals: SD1, eMMC(USDHC2), USB OTG1, I2C, ENET2, PMIC. Due to a board issue, the SD1 only supports 1 bit bus width. Signed-off-by: Ye.Li <B37916@freescale.com>
Diffstat (limited to 'include')
-rw-r--r--include/configs/mx6ul_14x14_lpddr2_arm2.h69
1 files changed, 69 insertions, 0 deletions
diff --git a/include/configs/mx6ul_14x14_lpddr2_arm2.h b/include/configs/mx6ul_14x14_lpddr2_arm2.h
new file mode 100644
index 0000000..c0b2129
--- /dev/null
+++ b/include/configs/mx6ul_14x14_lpddr2_arm2.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6UL 14x14 LPDDR2 ARM2.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __MX6UL_14X14_LPDDR2_ARM2_CONFIG_H
+#define __MX6UL_14X14_LPDDR2_ARM2_CONFIG_H
+
+#define CONFIG_DEFAULT_FDT_FILE "imx6ul-14x14-lpddr2-arm2.dtb"
+
+#ifdef CONFIG_SYS_BOOT_QSPI
+#define CONFIG_SYS_USE_QSPI
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#elif defined CONFIG_SYS_BOOT_SPINOR
+#define CONFIG_SYS_USE_SPINOR
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#elif defined CONFIG_SYS_BOOT_EIMNOR
+#define CONFIG_SYS_USE_EIMNOR
+#define CONFIG_ENV_IS_IN_FLASH
+#elif defined CONFIG_SYS_BOOT_NAND
+#define CONFIG_SYS_USE_NAND
+#define CONFIG_ENV_IS_IN_NAND
+#else
+#define CONFIG_ENV_IS_IN_MMC
+#endif
+
+#include "mx6ul_arm2.h"
+
+#define PHYS_SDRAM_SIZE SZ_512M
+
+#ifdef CONFIG_SYS_USE_SPINOR
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_BUS 1
+#define CONFIG_SF_DEFAULT_SPEED 20000000
+#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
+#define CONFIG_SF_DEFAULT_CS 0
+#endif
+
+#define CONFIG_CMD_NET
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define CONFIG_FEC_ENET_DEV 1 /* The ENET1 has pin conflict with UART1 */
+
+#if (CONFIG_FEC_ENET_DEV == 0)
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR 0x2
+#define CONFIG_FEC_XCV_TYPE MII100
+#elif (CONFIG_FEC_ENET_DEV == 1)
+#define IMX_FEC_BASE ENET2_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR 0x1
+#define CONFIG_FEC_XCV_TYPE RMII
+#endif
+#define CONFIG_ETHPRIME "FEC"
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_FEC_DMA_MINALIGN 64
+#endif
+
+#endif