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authorMatthias Fuchs <matthias.fuchs@esd-electronics.com>2009-02-20 10:19:19 +0100
committerWolfgang Denk <wd@denx.de>2009-03-20 22:39:14 +0100
commitbb57ad4be76d0e2e7f9ec56678235cc9872ff40f (patch)
treed02d3c5da773f66005bd4c2151e40529d06d4c4a /include
parent049216f045fd8e0f45bcef121c2bb1c7d3de6988 (diff)
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ppc4xx: Use correct io accessors for esd 405/440 boards
This patch replaces in/out8/16/32 macros by in/out_8/_be16/_be32 macros. Also volatile pointer references are replaced by the new accessors. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include')
-rw-r--r--include/configs/HH405.h17
1 files changed, 0 insertions, 17 deletions
diff --git a/include/configs/HH405.h b/include/configs/HH405.h
index ed9a235..9233523 100644
--- a/include/configs/HH405.h
+++ b/include/configs/HH405.h
@@ -413,23 +413,6 @@
#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */
-/* FPGA internal regs */
-#define CONFIG_SYS_FPGA_CTRL 0x000
-
-/* FPGA Control Reg */
-#define CONFIG_SYS_FPGA_CTRL_REV0 0x0001
-#define CONFIG_SYS_FPGA_CTRL_REV1 0x0002
-#define CONFIG_SYS_FPGA_CTRL_VGA0_BL 0x0004
-#define CONFIG_SYS_FPGA_CTRL_VGA0_BL_MODE 0x0008
-#define CONFIG_SYS_FPGA_CTRL_CF_RESET 0x0040
-#define CONFIG_SYS_FPGA_CTRL_PS2_PWR 0x0080
-#define CONFIG_SYS_FPGA_CTRL_CF_PWRN 0x0100 /* low active */
-#define CONFIG_SYS_FPGA_CTRL_CF_BUS_EN 0x0200
-#define CONFIG_SYS_FPGA_CTRL_LCD_CLK 0x7000 /* Mask for lcd clock */
-#define CONFIG_SYS_FPGA_CTRL_OW_ENABLE 0x8000
-
-#define CONFIG_SYS_FPGA_STATUS_CF_DETECT 0x8000
-
#define LCD_CLK_OFF 0x0000 /* Off */
#define LCD_CLK_02083 0x1000 /* 2.083 MHz */
#define LCD_CLK_03135 0x2000 /* 3.135 MHz */