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authorBin Meng <bmeng.cn@gmail.com>2014-12-12 21:05:25 +0800
committerSimon Glass <sjg@chromium.org>2014-12-13 22:32:05 -0700
commita2927e09bccca5b665709d77fc54919292d4bcb7 (patch)
tree0852399092f7a8184f74e8fc25f06154127a72ed /include
parent568868dda9b8f8e901962231713fc0cb3f42c410 (diff)
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x86: Add a simple superio driver for SMSC LPC47M
On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8) are provided by a superio chip connected to the LPC bus. We must program the superio chip so that serial ports are available for us. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include')
-rw-r--r--include/smsc_lpc47m.h19
1 files changed, 19 insertions, 0 deletions
diff --git a/include/smsc_lpc47m.h b/include/smsc_lpc47m.h
new file mode 100644
index 0000000..bffd622
--- /dev/null
+++ b/include/smsc_lpc47m.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SMSC_LPC47M_H_
+#define _SMSC_LPC47M_H_
+
+/**
+ * Configure the base I/O port of the specified serial device and enable the
+ * serial device.
+ *
+ * @dev: High 8 bits = Super I/O port, low 8 bits = logical device number.
+ * @iobase: Processor I/O port address to assign to this serial device.
+ */
+void lpc47m_enable_serial(u16 dev, u16 iobase);
+
+#endif /* _SMSC_LPC47M_H_ */