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authorAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-05-30 14:45:06 +0200
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-05-30 14:45:06 +0200
commita19b0dd62d7b8efc658fa1aa685ff5665878f3ee (patch)
tree1fadf0fb3da83203ba28f209ec99e1b33e03f4d5 /include
parent60985bba58e7695dac1fddae8cdbb62d8cfd1254 (diff)
parenta71d45d706a5b51c348160163b6c159632273fed (diff)
downloadu-boot-imx-a19b0dd62d7b8efc658fa1aa685ff5665878f3ee.zip
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Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts: common/cmd_fpga.c drivers/usb/host/ohci-at91.c
Diffstat (limited to 'include')
-rw-r--r--include/asm-generic/u-boot.h8
-rw-r--r--include/bootstage.h59
-rw-r--r--include/common.h41
-rw-r--r--include/configs/Alaska8220.h334
-rw-r--r--include/configs/B4860QDS.h16
-rw-r--r--include/configs/T4240QDS.h1
-rw-r--r--include/configs/Yukon8220.h326
-rw-r--r--include/configs/bf527-ezkit.h12
-rw-r--r--include/configs/bf537-stamp.h10
-rw-r--r--include/configs/bf548-ezkit.h25
-rw-r--r--include/configs/bf561-ezkit.h5
-rw-r--r--include/configs/bf609-ezkit.h10
-rw-r--r--include/configs/bfin_adi_common.h14
-rw-r--r--include/configs/coreboot.h18
-rw-r--r--include/configs/corenet_ds.h2
-rw-r--r--include/configs/microblaze-generic.h3
-rw-r--r--include/configs/sorcery.h298
-rw-r--r--include/configs/t4qds.h45
-rw-r--r--include/ext4fs.h1
-rw-r--r--include/ext_common.h12
-rw-r--r--include/faraday/ftsdc010.h31
-rw-r--r--include/fdt.h53
-rw-r--r--include/fdt_support.h2
-rw-r--r--include/fm_eth.h4
-rw-r--r--include/hash.h22
-rw-r--r--include/image.h151
-rw-r--r--include/libfdt.h38
-rw-r--r--include/libfdt_env.h3
-rw-r--r--include/lmb.h2
-rw-r--r--include/mmc.h30
-rw-r--r--include/mpc8220.h717
-rw-r--r--include/mtd/cfi_flash.h18
-rw-r--r--include/netdev.h1
-rw-r--r--include/phy.h2
-rw-r--r--include/ppc_asm.tmpl2
-rw-r--r--include/usb.h6
-rw-r--r--include/usb_defs.h46
-rw-r--r--include/watchdog.h3
38 files changed, 566 insertions, 1805 deletions
diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h
index a9aa8ba..a4bfdac 100644
--- a/include/asm-generic/u-boot.h
+++ b/include/asm-generic/u-boot.h
@@ -61,14 +61,6 @@ typedef struct bd_info {
#if defined(CONFIG_MPC83xx)
unsigned long bi_immrbar;
#endif
-#if defined(CONFIG_MPC8220)
- unsigned long bi_mbar_base; /* base of internal registers */
- unsigned long bi_inpfreq; /* Input Freq, In MHz */
- unsigned long bi_pcifreq; /* PCI Freq, in MHz */
- unsigned long bi_pevfreq; /* PEV Freq, in MHz */
- unsigned long bi_flbfreq; /* Flexbus Freq, in MHz */
- unsigned long bi_vcofreq; /* VCO Freq, in MHz */
-#endif
unsigned long bi_bootflags; /* boot / reboot flag (Unused) */
unsigned long bi_ip_addr; /* IP Address */
unsigned char bi_enetaddr[6]; /* OLD: see README.enetaddr */
diff --git a/include/bootstage.h b/include/bootstage.h
index 3b2216b..6dc0422 100644
--- a/include/bootstage.h
+++ b/include/bootstage.h
@@ -221,7 +221,7 @@ enum bootstage_id {
*/
ulong timer_get_boot_us(void);
-#ifndef CONFIG_SPL_BUILD
+#if !defined(CONFIG_SPL_BUILD) && !defined(USE_HOSTCC)
/*
* Board code can implement show_boot_progress() if needed.
*
@@ -233,10 +233,21 @@ void show_boot_progress(int val);
#define show_boot_progress(val) do {} while (0)
#endif
-#if defined(CONFIG_BOOTSTAGE) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_BOOTSTAGE) && !defined(CONFIG_SPL_BUILD) && \
+ !defined(USE_HOSTCC)
/* This is the full bootstage implementation */
/**
+ * Relocate existing bootstage records
+ *
+ * Call this after relocation has happened and after malloc has been initted.
+ * We need to copy any pointers in bootstage records that were added pre-
+ * relocation, since memory can be overritten later.
+ * @return Always returns 0, to indicate success
+ */
+int bootstage_relocate(void);
+
+/**
* Add a new bootstage record
*
* @param id Bootstage ID to use (ignored if flags & BOOTSTAGEF_ALLOC)
@@ -257,6 +268,19 @@ ulong bootstage_error(enum bootstage_id id);
ulong bootstage_mark_name(enum bootstage_id id, const char *name);
/**
+ * Mark a time stamp in the given function and line number
+ *
+ * See BOOTSTAGE_MARKER() for a convenient macro.
+ *
+ * @param file Filename to record (NULL if none)
+ * @param func Function name to record
+ * @param linenum Line number to record
+ * @return recorded time stamp
+ */
+ulong bootstage_mark_code(const char *file, const char *func,
+ int linenum);
+
+/**
* Mark the start of a bootstage activity. The end will be marked later with
* bootstage_accum() and at that point we accumulate the time taken. Calling
* this function turns the given id into a accumulator rather than and
@@ -315,11 +339,22 @@ int bootstage_stash(void *base, int size);
int bootstage_unstash(void *base, int size);
#else
+static inline ulong bootstage_add_record(enum bootstage_id id,
+ const char *name, int flags, ulong mark)
+{
+ return 0;
+}
+
/*
* This is a dummy implementation which just calls show_boot_progress(),
* and won't even do that unless CONFIG_SHOW_BOOT_PROGRESS is defined
*/
+static inline int bootstage_relocate(void)
+{
+ return 0;
+}
+
static inline ulong bootstage_mark(enum bootstage_id id)
{
show_boot_progress(id);
@@ -337,6 +372,22 @@ static inline ulong bootstage_mark_name(enum bootstage_id id, const char *name)
return 0;
}
+static inline ulong bootstage_mark_code(const char *file, const char *func,
+ int linenum)
+{
+ return 0;
+}
+
+static inline uint32_t bootstage_start(enum bootstage_id id, const char *name)
+{
+ return 0;
+}
+
+static inline uint32_t bootstage_accum(enum bootstage_id id)
+{
+ return 0;
+}
+
static inline int bootstage_stash(void *base, int size)
{
return 0; /* Pretend to succeed */
@@ -348,4 +399,8 @@ static inline int bootstage_unstash(void *base, int size)
}
#endif /* CONFIG_BOOTSTAGE */
+/* Helper macro for adding a bootstage to a line of code */
+#define BOOTSTAGE_MARKER() \
+ bootstage_mark_code(__FILE__, __func__, __LINE__)
+
#endif
diff --git a/include/common.h b/include/common.h
index 8a1f3e4..e682bd8 100644
--- a/include/common.h
+++ b/include/common.h
@@ -71,8 +71,6 @@ typedef volatile unsigned char vu_char;
#include <mpc5xxx.h>
#elif defined(CONFIG_MPC512X)
#include <asm/immap_512x.h>
-#elif defined(CONFIG_MPC8220)
-#include <asm/immap_8220.h>
#elif defined(CONFIG_8260)
#if defined(CONFIG_MPC8247) \
|| defined(CONFIG_MPC8248) \
@@ -199,18 +197,35 @@ typedef void (interrupt_handler_t)(void *);
* General Purpose Utilities
*/
#define min(X, Y) \
- ({ typeof (X) __x = (X); \
- typeof (Y) __y = (Y); \
+ ({ typeof(X) __x = (X); \
+ typeof(Y) __y = (Y); \
(__x < __y) ? __x : __y; })
#define max(X, Y) \
- ({ typeof (X) __x = (X); \
- typeof (Y) __y = (Y); \
+ ({ typeof(X) __x = (X); \
+ typeof(Y) __y = (Y); \
(__x > __y) ? __x : __y; })
#define MIN(x, y) min(x, y)
#define MAX(x, y) max(x, y)
+#define min3(X, Y, Z) \
+ ({ typeof(X) __x = (X); \
+ typeof(Y) __y = (Y); \
+ typeof(Z) __z = (Z); \
+ __x < __y ? (__x < __z ? __x : __z) : \
+ (__y < __z ? __y : __z); })
+
+#define max3(X, Y, Z) \
+ ({ typeof(X) __x = (X); \
+ typeof(Y) __y = (Y); \
+ typeof(Z) __z = (Z); \
+ __x > __y ? (__x > __z ? __x : __z) : \
+ (__y > __z ? __y : __z); })
+
+#define MIN3(x, y, z) min3(x, y, z)
+#define MAX3(x, y, z) max3(x, y, z)
+
/*
* Return the absolute value of a number.
*
@@ -323,6 +338,16 @@ int update_flash_size(int flash_size);
*/
void board_show_dram(ulong size);
+/**
+ * arch_fixup_memory_node() - Write arch-specific memory information to fdt
+ *
+ * Defined in arch/$(ARCH)/lib/bootm.c
+ *
+ * @blob: FDT blob to write to
+ * @return 0 if ok, or -ve FDT_ERR_... on failure
+ */
+int arch_fixup_memory_node(void *blob);
+
/* common/flash.c */
void flash_perror (int);
@@ -556,7 +581,6 @@ void trap_init (ulong);
defined (CONFIG_74x) || \
defined (CONFIG_75x) || \
defined (CONFIG_74xx) || \
- defined (CONFIG_MPC8220) || \
defined (CONFIG_MPC85xx) || \
defined (CONFIG_MPC86xx) || \
defined (CONFIG_MPC83xx)
@@ -648,9 +672,6 @@ int prt_8260_clks (void);
#elif defined(CONFIG_MPC5xxx)
int prt_mpc5xxx_clks (void);
#endif
-#if defined(CONFIG_MPC8220)
-int prt_mpc8220_clks (void);
-#endif
#ifdef CONFIG_4xx
ulong get_OPB_freq (void);
ulong get_PCI_freq (void);
diff --git a/include/configs/Alaska8220.h b/include/configs/Alaska8220.h
deleted file mode 100644
index 39c29ec..0000000
--- a/include/configs/Alaska8220.h
+++ /dev/null
@@ -1,334 +0,0 @@
-/*
- * (C) Copyright 2004
- * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC8220 1
-#define CONFIG_ALASKA8220 1 /* ... on Alaska board */
-
-#define CONFIG_SYS_TEXT_BASE 0xfff00000
-
-#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
- determine the CPU speed. */
-#define CONFIG_SYS_MPC8220_CLKIN 30000000/* ... running at 30MHz */
-#define CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
-
-/*
- * Serial console configuration
- */
-
-/* Define this for PSC console
-#define CONFIG_PSC_CONSOLE 1
-*/
-
-#define CONFIG_EXTUART_CONSOLE 1
-
-#ifdef CONFIG_EXTUART_CONSOLE
-# define CONFIG_CONS_INDEX 1
-# define CONFIG_SYS_NS16550_SERIAL
-# define CONFIG_SYS_NS16550
-# define CONFIG_SYS_NS16550_REG_SIZE 1
-# define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CPLD_BASE + 0x1008)
-# define CONFIG_SYS_NS16550_CLK 18432000
-#endif
-
-#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BOOTD
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SNTP
-
-
-#define CONFIG_MII
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_BOOTARGS "root=/dev/ram rw"
-#define CONFIG_ETHADDR 00:e0:0c:bc:e0:60
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 00:e0:0c:bc:e0:61
-#define CONFIG_IPADDR 192.162.1.2
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_SERVERIP 192.162.1.1
-#define CONFIG_GATEWAYIP 192.162.1.1
-#define CONFIG_HOSTNAME Alaska
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_MODULE 1
-
-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*
- * EEPROM configuration
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1011000xb */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
-/*
-#define CONFIG_ENV_IS_IN_EEPROM 1
-#define CONFIG_ENV_OFFSET 0
-#define CONFIG_ENV_SIZE 256
-*/
-
-/* If CONFIG_SYS_AMD_BOOT is defined, the the system will boot from AMD.
- else undefined it will boot from Intel Strata flash */
-#define CONFIG_SYS_AMD_BOOT 1
-
-/*
- * Flexbus Chipselect configuration
- */
-#if defined (CONFIG_SYS_AMD_BOOT)
-#define CONFIG_SYS_CS0_BASE 0xfff0
-#define CONFIG_SYS_CS0_MASK 0x00080000 /* 512 KB */
-#define CONFIG_SYS_CS0_CTRL 0x003f0d40
-
-#define CONFIG_SYS_CS1_BASE 0xfe00
-#define CONFIG_SYS_CS1_MASK 0x01000000 /* 16 MB */
-#define CONFIG_SYS_CS1_CTRL 0x003f1540
-#else
-#define CONFIG_SYS_CS0_BASE 0xff00
-#define CONFIG_SYS_CS0_MASK 0x01000000 /* 16 MB */
-#define CONFIG_SYS_CS0_CTRL 0x003f1540
-
-#define CONFIG_SYS_CS1_BASE 0xfe08
-#define CONFIG_SYS_CS1_MASK 0x00080000 /* 512 KB */
-#define CONFIG_SYS_CS1_CTRL 0x003f0d40
-#endif
-
-#define CONFIG_SYS_CS2_BASE 0xf100
-#define CONFIG_SYS_CS2_MASK 0x00040000
-#define CONFIG_SYS_CS2_CTRL 0x003f1140
-
-#define CONFIG_SYS_CS3_BASE 0xf200
-#define CONFIG_SYS_CS3_MASK 0x00040000
-#define CONFIG_SYS_CS3_CTRL 0x003f1100
-
-
-#define CONFIG_SYS_FLASH0_BASE (CONFIG_SYS_CS0_BASE << 16)
-#define CONFIG_SYS_FLASH1_BASE (CONFIG_SYS_CS1_BASE << 16)
-
-#if defined (CONFIG_SYS_AMD_BOOT)
-#define CONFIG_SYS_AMD_BASE CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_INTEL_BASE CONFIG_SYS_FLASH1_BASE + 0xf00000
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_AMD_BASE
-#else
-#define CONFIG_SYS_INTEL_BASE CONFIG_SYS_FLASH0_BASE + 0xf00000
-#define CONFIG_SYS_AMD_BASE CONFIG_SYS_FLASH1_BASE
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_INTEL_BASE
-#endif
-
-#define CONFIG_SYS_CPLD_BASE (CONFIG_SYS_CS2_BASE << 16)
-#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_CS3_BASE << 16)
-
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
-#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
-
-#define PHYS_AMD_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */
-#define PHYS_INTEL_SECT_SIZE 0x00020000 /* 128 KB sectors (x2) */
-
-#define CONFIG_SYS_FLASH_CHECKSUM
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#if defined (CONFIG_SYS_AMD_BOOT)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_AMD_SECT_SIZE)
-#define CONFIG_ENV_SIZE PHYS_AMD_SECT_SIZE
-#define CONFIG_ENV_SECT_SIZE PHYS_AMD_SECT_SIZE
-#define CONFIG_ENV1_ADDR (CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_INTEL_SECT_SIZE)
-#define CONFIG_ENV1_SIZE PHYS_INTEL_SECT_SIZE
-#define CONFIG_ENV1_SECT_SIZE PHYS_INTEL_SECT_SIZE
-#else
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_INTEL_SECT_SIZE)
-#define CONFIG_ENV_SIZE PHYS_INTEL_SECT_SIZE
-#define CONFIG_ENV_SECT_SIZE PHYS_INTEL_SECT_SIZE
-#define CONFIG_ENV1_ADDR (CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_AMD_SECT_SIZE)
-#define CONFIG_ENV1_SIZE PHYS_AMD_SECT_SIZE
-#define CONFIG_ENV1_SECT_SIZE PHYS_AMD_SECT_SIZE
-#endif
-
-#define CONFIG_ENV_OVERWRITE 1
-
-#if defined CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_EEPROM
-#elif defined CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_EEPROM
-#elif defined CONFIG_ENV_IS_IN_EEPROM
-#undef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_FLASH
-#endif
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR 0xF0000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-#define CONFIG_SYS_SRAM_BASE (CONFIG_SYS_MBAR + 0x20000)
-#define CONFIG_SYS_SRAM_SIZE 0x8000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MBAR + 0x20000)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in DPRAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/* SDRAM configuration */
-#define CONFIG_SYS_SDRAM_TOTAL_BANKS 2
-#define CONFIG_SYS_SDRAM_SPD_I2C_ADDR 0x51 /* 7bit */
-#define CONFIG_SYS_SDRAM_SPD_SIZE 0x40
-#define CONFIG_SYS_SDRAM_CAS_LATENCY 4 /* (CL=2)x2 */
-
-/* SDRAM drive strength register */
-#define CONFIG_SYS_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_LOW << SDRAMDS_SBE_SHIFT) | \
- (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
- (DRIVE_STRENGTH_LOW << SDRAMDS_SBA_SHIFT) | \
- (DRIVE_STRENGTH_OFF << SDRAMDS_SBS_SHIFT) | \
- (DRIVE_STRENGTH_LOW << SDRAMDS_SBD_SHIFT))
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC8220_FEC 1
-#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
-#define CONFIG_PHY_ADDR 0x18
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-
-/*
- * JFFS2 partitions
- */
-
-/* No command line, one static partition */
-/*
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nor0"
-#define CONFIG_JFFS2_PART_SIZE 0x00400000
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-*/
-
-/* mtdparts command line support */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nor0=alaska-0"
-#define MTDPARTS_DEFAULT "mtdparts=alaska-0:4m(user)"
-*/
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index b09119a..1c9d08e 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -36,7 +36,6 @@
/* High Level Configuration Options */
#define CONFIG_BOOKE
-#define CONFIG_E6500
#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
@@ -528,6 +527,15 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SF_DEFAULT_MODE 0
/*
+ * MAPLE
+ */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull
+#else
+#define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000
+#endif
+
+/*
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
@@ -623,7 +631,11 @@ unsigned long get_board_ddr_clk(void);
#ifdef CONFIG_FMAN_ENET
#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10
#define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11
-#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
+
+/*B4860 QDS AMC2PEX-2S default PHY_ADDR */
+#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/
+#define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/
+
#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index 76b3ca6..6dd5c0d 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -25,7 +25,6 @@
*/
#define CONFIG_T4240QDS
#define CONFIG_PHYS_64BIT
-#define CONFIG_PPC_T4240
#define CONFIG_FSL_SATA_V2
#define CONFIG_PCIE4
diff --git a/include/configs/Yukon8220.h b/include/configs/Yukon8220.h
deleted file mode 100644
index 5f925b3..0000000
--- a/include/configs/Yukon8220.h
+++ /dev/null
@@ -1,326 +0,0 @@
-/*
- * (C) Copyright 2004
- * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC8220 1
-#define CONFIG_YUKON8220 1 /* ... on Yukon board */
-
-#define CONFIG_SYS_TEXT_BASE 0xfff00000
-
-#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
- determine the CPU speed. */
-#define CONFIG_SYS_MPC8220_CLKIN 30000000/* ... running at 30MHz */
-#define CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
-
-/*
- * Serial console configuration
- */
-
-/* Define this for PSC console
-#define CONFIG_PSC_CONSOLE 1
-*/
-
-#define CONFIG_EXTUART_CONSOLE 1
-
-#ifdef CONFIG_EXTUART_CONSOLE
-# define CONFIG_CONS_INDEX 1
-# define CONFIG_SYS_NS16550_SERIAL
-# define CONFIG_SYS_NS16550
-# define CONFIG_SYS_NS16550_REG_SIZE 1
-# define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CPLD_BASE + 0x1008)
-# define CONFIG_SYS_NS16550_CLK 18432000
-#endif
-
-#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BOOTD
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SNTP
-
-
-#define CONFIG_MII
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_BOOTARGS "root=/dev/ram rw"
-#define CONFIG_ETHADDR 00:e0:0c:bc:e0:60
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 00:e0:0c:bc:e0:61
-#define CONFIG_IPADDR 192.162.1.2
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_SERVERIP 192.162.1.1
-#define CONFIG_GATEWAYIP 192.162.1.1
-#define CONFIG_HOSTNAME yukon
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_MODULE 1
-
-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*
- * EEPROM configuration
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1011000xb */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
-/*
-#define CONFIG_ENV_IS_IN_EEPROM 1
-#define CONFIG_ENV_OFFSET 0
-#define CONFIG_ENV_SIZE 256
-*/
-
-/* If CONFIG_SYS_AMD_BOOT is defined, the the system will boot from AMD.
- else undefined it will boot from Intel Strata flash */
-#define CONFIG_SYS_AMD_BOOT 1
-
-/*
- * Flexbus Chipselect configuration
- */
-#if defined (CONFIG_SYS_AMD_BOOT)
-#define CONFIG_SYS_CS0_BASE 0xfff0
-#define CONFIG_SYS_CS0_MASK 0x00080000 /* 512 KB */
-#define CONFIG_SYS_CS0_CTRL 0x003f0d40
-
-#define CONFIG_SYS_CS1_BASE 0xfe00
-#define CONFIG_SYS_CS1_MASK 0x01000000 /* 16 MB */
-#define CONFIG_SYS_CS1_CTRL 0x003f1540
-#else
-#define CONFIG_SYS_CS0_BASE 0xff00
-#define CONFIG_SYS_CS0_MASK 0x01000000 /* 16 MB */
-#define CONFIG_SYS_CS0_CTRL 0x003f1540
-
-#define CONFIG_SYS_CS1_BASE 0xfe08
-#define CONFIG_SYS_CS1_MASK 0x00080000 /* 512 KB */
-#define CONFIG_SYS_CS1_CTRL 0x003f0d40
-#endif
-
-#define CONFIG_SYS_CS2_BASE 0xf100
-#define CONFIG_SYS_CS2_MASK 0x00040000
-#define CONFIG_SYS_CS2_CTRL 0x003f1140
-
-#define CONFIG_SYS_CS3_BASE 0xf200
-#define CONFIG_SYS_CS3_MASK 0x00040000
-#define CONFIG_SYS_CS3_CTRL 0x003f1100
-
-
-#define CONFIG_SYS_FLASH0_BASE (CONFIG_SYS_CS0_BASE << 16)
-#define CONFIG_SYS_FLASH1_BASE (CONFIG_SYS_CS1_BASE << 16)
-
-#if defined (CONFIG_SYS_AMD_BOOT)
-#define CONFIG_SYS_AMD_BASE CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_INTEL_BASE CONFIG_SYS_FLASH1_BASE + 0xf00000
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_AMD_BASE
-#else
-#define CONFIG_SYS_INTEL_BASE CONFIG_SYS_FLASH0_BASE + 0xf00000
-#define CONFIG_SYS_AMD_BASE CONFIG_SYS_FLASH1_BASE
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_INTEL_BASE
-#endif
-
-#define CONFIG_SYS_CPLD_BASE (CONFIG_SYS_CS2_BASE << 16)
-#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_CS3_BASE << 16)
-
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
-#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
-
-#define PHYS_AMD_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */
-#define PHYS_INTEL_SECT_SIZE 0x00020000 /* 128 KB sectors (x2) */
-
-#define CONFIG_SYS_FLASH_CHECKSUM
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#if defined (CONFIG_SYS_AMD_BOOT)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_AMD_SECT_SIZE)
-#define CONFIG_ENV_SIZE PHYS_AMD_SECT_SIZE
-#define CONFIG_ENV_SECT_SIZE PHYS_AMD_SECT_SIZE
-#define CONFIG_ENV1_ADDR (CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_INTEL_SECT_SIZE)
-#define CONFIG_ENV1_SIZE PHYS_INTEL_SECT_SIZE
-#define CONFIG_ENV1_SECT_SIZE PHYS_INTEL_SECT_SIZE
-#else
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_INTEL_SECT_SIZE)
-#define CONFIG_ENV_SIZE PHYS_INTEL_SECT_SIZE
-#define CONFIG_ENV_SECT_SIZE PHYS_INTEL_SECT_SIZE
-#define CONFIG_ENV1_ADDR (CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_AMD_SECT_SIZE)
-#define CONFIG_ENV1_SIZE PHYS_AMD_SECT_SIZE
-#define CONFIG_ENV1_SECT_SIZE PHYS_AMD_SECT_SIZE
-#endif
-
-#define CONFIG_ENV_OVERWRITE 1
-
-#if defined CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_EEPROM
-#elif defined CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_EEPROM
-#elif defined CONFIG_ENV_IS_IN_EEPROM
-#undef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_FLASH
-#endif
-
-#ifndef CONFIG_SYS_JFFS2_FIRST_SECTOR
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0
-#endif
-#ifndef CONFIG_SYS_JFFS2_FIRST_BANK
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0
-#endif
-#ifndef CONFIG_SYS_JFFS2_NUM_BANKS
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-#endif
-#define CONFIG_SYS_JFFS2_LAST_BANK (CONFIG_SYS_JFFS2_FIRST_BANK + CONFIG_SYS_JFFS2_NUM_BANKS - 1)
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR 0xF0000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-#define CONFIG_SYS_SRAM_BASE (CONFIG_SYS_MBAR + 0x20000)
-#define CONFIG_SYS_SRAM_SIZE 0x8000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MBAR + 0x20000)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in DPRAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/* SDRAM configuration */
-#define CONFIG_SYS_SDRAM_TOTAL_BANKS 2
-#define CONFIG_SYS_SDRAM_SPD_I2C_ADDR 0x51 /* 7bit */
-#define CONFIG_SYS_SDRAM_SPD_SIZE 0x40
-#define CONFIG_SYS_SDRAM_CAS_LATENCY 4 /* (CL=2)x2 */
-
-/* SDRAM drive strength register */
-#define CONFIG_SYS_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_LOW << SDRAMDS_SBE_SHIFT) | \
- (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
- (DRIVE_STRENGTH_LOW << SDRAMDS_SBA_SHIFT) | \
- (DRIVE_STRENGTH_OFF << SDRAMDS_SBS_SHIFT) | \
- (DRIVE_STRENGTH_LOW << SDRAMDS_SBD_SHIFT))
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC8220_FEC 1
-#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
-#define CONFIG_PHY_ADDR 0x18
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h
index 7b51b53..db1b613 100644
--- a/include/configs/bf527-ezkit.h
+++ b/include/configs/bf527-ezkit.h
@@ -149,10 +149,15 @@
#define CONFIG_MUSB_TIMEOUT 100000
#endif
+/* Don't waste time transferring a logo over the UART */
+#if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
+/*# define CONFIG_VIDEO*/
+#endif
/*
* Video Settings
*/
+#ifdef CONFIG_VIDEO
#ifdef CONFIG_BF527_EZKIT_REV_2_1
# define CONFIG_LQ035Q1_SPI_BUS 0
# define CONFIG_LQ035Q1_SPI_CS 7
@@ -166,7 +171,7 @@
#else
# define EASYLOGO_HEADER <asm/bfin_logo_230x230_lzma.h>
#endif
-
+#endif /* CONFIG_VIDEO */
/*
* Misc Settings
@@ -175,11 +180,6 @@
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 1
-/* Don't waste time transferring a logo over the UART */
-#if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
-# define CONFIG_VIDEO
-#endif
-
/*
* Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index 05029d4..25cebf8 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -52,7 +52,7 @@
#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
@@ -135,15 +135,17 @@
/*
* SPI_MMC Settings
*/
+#define CONFIG_MMC_SPI
+#ifdef CONFIG_MMC_SPI
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC_SPI
-
+#endif
/*
* NAND Settings
*/
/* #define CONFIG_NAND_PLAT */
+#ifdef CONFIG_NAND_PLAT
#define CONFIG_SYS_NAND_BASE 0x20212000
#define CONFIG_SYS_MAX_NAND_DEVICE 1
@@ -158,7 +160,7 @@
#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
#define NAND_PLAT_GPIO_DEV_READY GPIO_PF3
-
+#endif /* CONFIG_NAND_PLAT */
/*
* CF-CARD IDE-HDD Support
diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h
index e6b05db..da5f029 100644
--- a/include/configs/bf548-ezkit.h
+++ b/include/configs/bf548-ezkit.h
@@ -120,18 +120,16 @@
#define CONFIG_ENV_SECT_SIZE 0x8000
#endif
-
/*
* NAND Settings
*/
-#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
-# define CONFIG_BFIN_NFC_BOOTROM_ECC
-#endif
+#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
+#define CONFIG_BFIN_NFC_BOOTROM_ECC
#define CONFIG_DRIVER_NAND_BFIN
-#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
+#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#endif
/*
* I2C Settings
@@ -184,13 +182,12 @@
#define CONFIG_UART_CONSOLE 1
#define CONFIG_BFIN_SPI_IMG_SIZE 0x50000
-#ifndef __ADSPBF542__
-/* Don't waste time transferring a logo over the UART */
-# if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
-# define CONFIG_VIDEO
-# define EASYLOGO_HEADER <asm/bfin_logo_230x230_gzip.h>
-# endif
-# define CONFIG_DEB_DMA_URGENT
+#define CONFIG_ADI_GPIO2
+
+#undef CONFIG_VIDEO
+#ifdef CONFIG_VIDEO
+#define EASYLOGO_HEADER < asm/bfin_logo_230x230_gzip.h >
+#define CONFIG_DEB_DMA_URGENT
#endif
/* Define if want to do post memory test */
diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h
index 1a9d27e..6ee1e4c 100644
--- a/include/configs/bf561-ezkit.h
+++ b/include/configs/bf561-ezkit.h
@@ -98,6 +98,11 @@
*/
#define CONFIG_UART_CONSOLE 0
+/*
+ * Run core 1 from L1 SRAM start address when init uboot on core 0
+ */
+/* #define CONFIG_CORE1_RUN 1 */
+
/*
* Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h
index 02149fa..1a43e1b 100644
--- a/include/configs/bf609-ezkit.h
+++ b/include/configs/bf609-ezkit.h
@@ -144,10 +144,13 @@
#define CONFIG_UART_CONSOLE 0
#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_SOFTSWITCH
#define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 20*1024*1024 + 4)
#define CONFIG_BFIN_SOFT_SWITCH
+#define CONFIG_ADI_GPIO2
+
#if 0
#define CONFIG_UART_MEM 1024
#undef CONFIG_UART_CONSOLE
@@ -155,6 +158,13 @@
#undef CONFIG_UART_CONSOLE_IS_JTAG
#endif
+#define CONFIG_BOARD_SIZE_LIMIT $$((512 * 1024))
+
+/*
+ * Run core 1 from L1 SRAM start address when init uboot on core 0
+ */
+/* #define CONFIG_CORE1_RUN 1 */
+
/*
* Pull in common ADI header for remaining command/environment setup
*/
diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index d3ae3a7..e1a6fe3 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -111,8 +111,8 @@
#ifndef CONFIG_BAUDRATE
# define CONFIG_BAUDRATE 57600
#endif
-#ifndef CONFIG_DEBUG_EARLY_SERIAL
-# define CONFIG_SYS_BFIN_UART
+#ifdef CONFIG_UART_CONSOLE
+# define CONFIG_BFIN_SERIAL
#endif
/*
@@ -317,5 +317,13 @@
#define CONFIG_BFIN_SPI_GPIO_CS /* Only matters if BFIN_SPI is enabled */
#define CONFIG_LZMA
#define CONFIG_MONITOR_IS_IN_RAM
-
+#ifdef CONFIG_HW_WATCHDOG
+# define CONFIG_BFIN_WATCHDOG
+# ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
+# define CONFIG_WATCHDOG_TIMEOUT_MSECS 5000
+# endif
+#endif
+#ifndef CONFIG_ADI_GPIO2
+# define CONFIG_ADI_GPIO1
+#endif
#endif
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index 5bacc77..be04a75 100644
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -38,7 +38,6 @@
#define CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_LAST_STAGE_INIT
#define CONFIG_SYS_VSNPRINTF
-#define CONFIG_INTEL_CORE_ARCH /* Sandy bridge and ivy bridge chipsets. */
#define CONFIG_ZBOOT_32
#define CONFIG_PHYSMEM
#define CONFIG_SYS_EARLY_PCI_INIT
@@ -49,6 +48,19 @@
#define CONFIG_OF_SEPARATE
#define CONFIG_DEFAULT_DEVICE_TREE link
+#define CONFIG_BOOTSTAGE
+#define CONFIG_BOOTSTAGE_REPORT
+#define CONFIG_BOOTSTAGE_FDT
+#define CONFIG_CMD_BOOTSTAGE
+/* Place to stash bootstage data from first-stage U-Boot */
+#define CONFIG_BOOTSTAGE_STASH 0x0110f000
+#define CONFIG_BOOTSTAGE_STASH_SIZE 0x7fc
+#define CONFIG_BOOTSTAGE_USER_COUNT 60
+
+#define CONFIG_LZO
+#undef CONFIG_ZLIB
+#undef CONFIG_GZIP
+
/*-----------------------------------------------------------------------
* Watchdog Configuration
*/
@@ -218,7 +230,6 @@
#define CONFIG_SYS_MEMTEST_END 0x01000000
#define CONFIG_SYS_LOAD_ADDR 0x100000
#define CONFIG_SYS_HZ 1000
-#define CONFIG_SYS_X86_ISR_TIMER
/*-----------------------------------------------------------------------
* SDRAM Configuration
@@ -235,8 +246,9 @@
* CPU Features
*/
-#define CONFIG_SYS_GENERIC_TIMER
+#define CONFIG_SYS_X86_TSC_TIMER
#define CONFIG_SYS_PCAT_INTERRUPTS
+#define CONFIG_SYS_PCAT_TIMER
#define CONFIG_SYS_NUM_IRQS 16
/*-----------------------------------------------------------------------
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 5cc9b5a..2e2d439 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -38,6 +38,8 @@
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg
#elif defined(CONFIG_P5020DS)
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg
+#elif defined(CONFIG_P5040DS)
+#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5040ds.cfg
#endif
#endif
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index 0c4e719..17f53ba 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -104,7 +104,7 @@
/* gpio */
#ifdef XILINX_GPIO_BASEADDR
-# define CONFIG_SYS_GPIO_0 1
+# define CONFIG_XILINX_GPIO
# define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR
#endif
@@ -312,6 +312,7 @@
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MFSL
#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_GPIO
#if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE)
# define CONFIG_CMD_CACHE
diff --git a/include/configs/sorcery.h b/include/configs/sorcery.h
deleted file mode 100644
index f67898e..0000000
--- a/include/configs/sorcery.h
+++ /dev/null
@@ -1,298 +0,0 @@
-/*
- * (C) Copyright 2004
- * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC8220 1
-#define CONFIG_SORCERY 1 /* Sorcery board */
-
-#define CONFIG_SYS_TEXT_BASE 0xfff00000
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* Input clock running at 60Mhz, read Hid1 for the CPU multiplier to
- determine the CPU speed. */
-#define CONFIG_SYS_MPC8220_CLKIN 60000000 /* ... running at 60MHz */
-#define CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER 8 /* VCO multiplier can't be read from any register */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE 1 /* console is on PSC */
-
-#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/* PCI */
-#define CONFIG_PCI 1
-#define CONFIG_PCI_PNP 1
-
-#define CONFIG_PCI_MEM_BUS 0x80000000
-#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE 0x10000000
-
-#define CONFIG_PCI_IO_BUS 0x71000000
-#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE 0x01000000
-
-#define CONFIG_PCI_CFG_BUS 0x70000000
-#define CONFIG_PCI_CFG_PHYS CONFIG_PCI_CFG_BUS
-#define CONFIG_PCI_CFG_SIZE 0x01000000
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BOOTD
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SNTP
-
-
-/*
- * Default Environment
- */
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_HOSTNAME sorcery
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $bootargs " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
- ":$hostname:$netdev:off panic=1\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm $kernel_addr\0" \
- "flash_self=run ramargs addip;" \
- "bootm $kernel_addr $ramdisk_addr\0" \
- "net_nfs=tftp 200000 $bootfile;run nfsargs addip;bootm\0" \
- "rootpath=/opt/eldk/ppc_82xx\0" \
- "bootfile=/tftpboot/sorcery/uImage\0" \
- "kernel_addr=FFE00000\0" \
- "ramdisk_addr=FFB00000\0" \
- ""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-#define CONFIG_EEPRO100
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_MODULE 1
-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/*
- * Flexbus Chipselect configuration
- * Beware: Some CS# seem to be mandatory (if these CS# are not set,
- * board can hang-up in unpredictable place).
- * Sorcery_Memory_Map v0.3 is possibly wrong with CPLD CS#
- */
-
-/* Flash */
-#define CONFIG_SYS_CS0_BASE 0xf800
-#define CONFIG_SYS_CS0_MASK 0x08000000 /* 128 MB (two chips) */
-#define CONFIG_SYS_CS0_CTRL 0x001019c0
-
-/* NVM */
-#define CONFIG_SYS_CS1_BASE 0xf7e8
-#define CONFIG_SYS_CS1_MASK 0x00040000 /* 256K */
-#define CONFIG_SYS_CS1_CTRL 0x00101940 /* 8bit port size */
-
-/* Atlas2 + Gemini */
-#define CONFIG_SYS_CS2_BASE 0xf7e7
-#define CONFIG_SYS_CS2_MASK 0x00010000 /* 64K*/
-#define CONFIG_SYS_CS2_CTRL 0x001011c0 /* 16bit port size */
-
-/* CAN Controller */
-#define CONFIG_SYS_CS3_BASE 0xf7e6
-#define CONFIG_SYS_CS3_MASK 0x00010000 /* 64K */
-#define CONFIG_SYS_CS3_CTRL 0x00102140 /* 8Bit port size */
-
-/* Foreign interface */
-#define CONFIG_SYS_CS4_BASE 0xf7e5
-#define CONFIG_SYS_CS4_MASK 0x00010000 /* 64K */
-#define CONFIG_SYS_CS4_CTRL 0x00101dc0 /* 16bit port size */
-
-/* CPLD */
-#define CONFIG_SYS_CS5_BASE 0xf7e4
-#define CONFIG_SYS_CS5_MASK 0x00010000 /* 64K */
-#define CONFIG_SYS_CS5_CTRL 0x001000c0 /* 16bit port size */
-
-#define CONFIG_SYS_FLASH0_BASE (CONFIG_SYS_CS0_BASE << 16)
-#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_FLASH0_BASE)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
-
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
- CONFIG_SYS_FLASH_BASE+0x04000000 } /* two banks */
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x8000000 - 0x40000)
-#define CONFIG_ENV_SIZE 0x4000 /* 16K */
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + 0x20000)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-#define CONFIG_ENV_OVERWRITE 1
-
-#if defined CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_EEPROM
-#elif defined CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_EEPROM
-#elif defined CONFIG_ENV_IS_IN_EEPROM
-#undef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_FLASH
-#endif
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR 0xF0000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-#define CONFIG_SYS_SRAM_BASE (CONFIG_SYS_MBAR + 0x20000)
-#define CONFIG_SYS_SRAM_SIZE 0x8000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MBAR + 0x20000)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in DPRAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/* SDRAM configuration (for SPD) */
-#define CONFIG_SYS_SDRAM_TOTAL_BANKS 1
-#define CONFIG_SYS_SDRAM_SPD_I2C_ADDR 0x50 /* 7bit */
-#define CONFIG_SYS_SDRAM_SPD_SIZE 0x100
-#define CONFIG_SYS_SDRAM_CAS_LATENCY 5 /* (CL=2.5)x2 */
-
-/* SDRAM drive strength register (for SSTL_2 class II)*/
-#define CONFIG_SYS_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_HIGH << SDRAMDS_SBE_SHIFT) | \
- (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
- (DRIVE_STRENGTH_HIGH << SDRAMDS_SBA_SHIFT) | \
- (DRIVE_STRENGTH_HIGH << SDRAMDS_SBS_SHIFT) | \
- (DRIVE_STRENGTH_HIGH << SDRAMDS_SBD_SHIFT))
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC8220_FEC 1
-#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
-#define CONFIG_PHY_ADDR 0x1F
-#define CONFIG_MII 1
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT 0
-#define CONFIG_SYS_HID0_FINAL 0
-
-/*
-#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-*/
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index 2c665b8..fa1dcc3 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -29,13 +29,14 @@
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_pbi.cfg
+#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg
#endif
#define CONFIG_CMD_REGINFO
/* High Level Configuration Options */
#define CONFIG_BOOKE
-#define CONFIG_E6500
#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
@@ -444,11 +445,19 @@ unsigned long get_board_ddr_clk(void);
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
-/* VSC Crossbar switches */
-#define CONFIG_VSC_CROSSBAR
#define I2C_MUX_CH_DEFAULT 0x8
+#define I2C_MUX_CH_VOL_MONITOR 0xa
#define I2C_MUX_CH_VSC3316_FS 0xc
#define I2C_MUX_CH_VSC3316_BS 0xd
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR 0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+
+/* VSC Crossbar switches */
+#define CONFIG_VSC_CROSSBAR
#define VSC3316_FSM_TX_ADDR 0x70
#define VSC3316_FSM_RX_ADDR 0x71
@@ -504,7 +513,7 @@ unsigned long get_board_ddr_clk(void);
*/
#define CONFIG_FSL_ESPI
#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_SST
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
@@ -641,15 +650,10 @@ unsigned long get_board_ddr_clk(void);
#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
-#define XFI_CARD_PORT1_PHY_ADDR 0x1 /* tmp, FIXME below addr */
-#define XFI_CARD_PORT2_PHY_ADDR 0x2
-#define XFI_CARD_PORT3_PHY_ADDR 0x3
-#define XFI_CARD_PORT4_PHY_ADDR 0x4
-#define QSGMII_CARD_PHY_ADDR 0x5
-#define FM1_10GEC1_PHY_ADDR 0x6
-#define FM1_10GEC2_PHY_ADDR 0x7
-#define FM2_10GEC1_PHY_ADDR 0x8
-#define FM2_10GEC2_PHY_ADDR 0x9
+#define FM1_10GEC1_PHY_ADDR 0x0
+#define FM1_10GEC2_PHY_ADDR 0x1
+#define FM2_10GEC1_PHY_ADDR 0x2
+#define FM2_10GEC2_PHY_ADDR 0x3
#endif
#ifdef CONFIG_PCI
@@ -783,8 +787,21 @@ unsigned long get_board_ddr_clk(void);
#define __USB_PHY_TYPE utmi
+/*
+ * T4240 has 3 DDR controllers. Default to 3way_4KB interleaving. It can be
+ * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to
+ * cacheline interleaving. It can be cacheline, page, bank, superbank.
+ * See doc/README.fsl-ddr for details.
+ */
+#ifdef CONFIG_PPC_T4240
+#define CTRL_INTLV_PREFERED 3way_4KB
+#else
+#define CTRL_INTLV_PREFERED cacheline
+#endif
+
#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:ctlr_intlv=3way_4KB," \
+ "hwconfig=fsl_ddr:" \
+ "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
"bank_intlv=auto;" \
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
"netdev=eth0\0" \
diff --git a/include/ext4fs.h b/include/ext4fs.h
index 025a2e8..379f7eb 100644
--- a/include/ext4fs.h
+++ b/include/ext4fs.h
@@ -141,4 +141,5 @@ long int read_allocated_block(struct ext2_inode *inode, int fileblock);
int ext4fs_probe(block_dev_desc_t *fs_dev_desc,
disk_partition_t *fs_partition);
int ext4_read_file(const char *filename, void *buf, int offset, int len);
+int ext4_read_superblock(char *buffer);
#endif
diff --git a/include/ext_common.h b/include/ext_common.h
index 86373a6..78a7808 100644
--- a/include/ext_common.h
+++ b/include/ext_common.h
@@ -34,7 +34,6 @@
#define __EXT_COMMON__
#include <command.h>
#define SECTOR_SIZE 0x200
-#define SECTOR_BITS 9
/* Magic value used to identify an ext2 filesystem. */
#define EXT2_MAGIC 0xEF53
@@ -58,18 +57,13 @@
#define FILETYPE_INO_SYMLINK 0120000
#define EXT2_ROOT_INO 2 /* Root inode */
-/* Bits used as offset in sector */
-#define DISK_SECTOR_BITS 9
/* The size of an ext2 block in bytes. */
#define EXT2_BLOCK_SIZE(data) (1 << LOG2_BLOCK_SIZE(data))
-/* Log2 size of ext2 block in 512 blocks. */
-#define LOG2_EXT2_BLOCK_SIZE(data) (__le32_to_cpu \
- (data->sblock.log2_block_size) + 1)
-
/* Log2 size of ext2 block in bytes. */
-#define LOG2_BLOCK_SIZE(data) (__le32_to_cpu \
- (data->sblock.log2_block_size) + 10)
+#define LOG2_BLOCK_SIZE(data) (__le32_to_cpu \
+ (data->sblock.log2_block_size) \
+ + EXT2_MIN_BLOCK_LOG_SIZE)
#define INODE_SIZE_FILESYSTEM(data) (__le32_to_cpu \
(data->sblock.inode_size))
diff --git a/include/faraday/ftsdc010.h b/include/faraday/ftsdc010.h
index c34dde7..8284f53 100644
--- a/include/faraday/ftsdc010.h
+++ b/include/faraday/ftsdc010.h
@@ -23,6 +23,7 @@
#define __FTSDC010_H
#ifndef __ASSEMBLY__
+
/* sd controller register */
struct ftsdc010_mmc {
unsigned int cmd; /* 0x00 - command reg */
@@ -143,6 +144,15 @@ int ftsdc010_mmc_init(int dev_index);
#define FTSDC010_STATUS_SDIO_IRPT (1 << 16) /* SDIO card intr */
#define FTSDC010_STATUS_DATA0_STATUS (1 << 17)
#endif /* CONFIG_FTSDC010_SDIO */
+#define FTSDC010_STATUS_RSP_ERROR \
+ (FTSDC010_STATUS_RSP_CRC_FAIL | FTSDC010_STATUS_RSP_TIMEOUT)
+#define FTSDC010_STATUS_RSP_MASK \
+ (FTSDC010_STATUS_RSP_ERROR | FTSDC010_STATUS_RSP_CRC_OK)
+#define FTSDC010_STATUS_DATA_ERROR \
+ (FTSDC010_STATUS_DATA_CRC_FAIL | FTSDC010_STATUS_DATA_TIMEOUT)
+#define FTSDC010_STATUS_DATA_MASK \
+ (FTSDC010_STATUS_DATA_ERROR | FTSDC010_STATUS_DATA_CRC_OK \
+ | FTSDC010_STATUS_DATA_END)
/* 0x2c - clear register */
#define FTSDC010_CLR_RSP_CRC_FAIL (1 << 0)
@@ -192,21 +202,24 @@ int ftsdc010_mmc_init(int dev_index);
#define FTSDC010_CCR_CLK_DIV(x) (((x) & 0x7f) << 0)
#define FTSDC010_CCR_CLK_SD (1 << 7) /* 0: MMC, 1: SD */
#define FTSDC010_CCR_CLK_DIS (1 << 8)
+#define FTSDC010_CCR_CLK_HISPD (1 << 9) /* high speed */
/* card type */
#define FTSDC010_CARD_TYPE_SD FTSDC010_CLOCK_REG_CARD_TYPE
#define FTSDC010_CARD_TYPE_MMC 0x0
/* 0x3c - bus width register */
-#define FTSDC010_BWR_SINGLE_BUS (1 << 0)
-#define FTSDC010_BWR_WIDE_8_BUS (1 << 1)
-#define FTSDC010_BWR_WIDE_4_BUS (1 << 2)
-#define FTSDC010_BWR_WIDE_BUS_SUPPORT(x) (((x) >> 3) & 0x3)
-#define FTSDC010_BWR_CARD_DETECT (1 << 5)
-
-#define FTSDC010_BWR_1_BUS_SUPPORT 0x0
-#define FTSDC010_BWR_4_BUS_SUPPORT 0x1
-#define FTSDC010_BWR_8_BUS_SUPPORT 0x2
+#define FTSDC010_BWR_MODE_1BIT (1 << 0) /* 1 bit mode enabled */
+#define FTSDC010_BWR_MODE_8BIT (1 << 1) /* 8 bit mode enabled */
+#define FTSDC010_BWR_MODE_4BIT (1 << 2) /* 4 bit mode enabled */
+#define FTSDC010_BWR_MODE_MASK (7 << 0)
+#define FTSDC010_BWR_MODE_SHIFT (0)
+#define FTSDC010_BWR_CAPS_1BIT (0 << 3) /* 1 bits mode supported */
+#define FTSDC010_BWR_CAPS_4BIT (1 << 3) /* 1,4 bits mode supported */
+#define FTSDC010_BWR_CAPS_8BIT (2 << 3) /* 1,4,8 bits mode supported */
+#define FTSDC010_BWR_CAPS_MASK (3 << 3)
+#define FTSDC010_BWR_CAPS_SHIFT (3)
+#define FTSDC010_BWR_CARD_DETECT (1 << 5)
/* 0x44 or 0x9c - feature register */
#define FTSDC010_FEATURE_FIFO_DEPTH(x) (((x) >> 0) & 0xff)
diff --git a/include/fdt.h b/include/fdt.h
index f9612ed..526aedb 100644
--- a/include/fdt.h
+++ b/include/fdt.h
@@ -1,5 +1,56 @@
#ifndef _FDT_H
#define _FDT_H
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ * Copyright 2012 Kim Phillips, Freescale Semiconductor.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this library; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ * b) Redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following
+ * conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials
+ * provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
#ifndef __ASSEMBLY__
@@ -57,6 +108,4 @@ struct fdt_property {
#define FDT_V16_SIZE FDT_V3_SIZE
#define FDT_V17_SIZE (FDT_V16_SIZE + sizeof(fdt32_t))
-/* adding a ramdisk needs 0x44 bytes in version 2008.10 */
-#define FDT_RAMDISK_OVERHEAD 0x80
#endif /* _FDT_H */
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 2cccc35..8f07a67 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -78,11 +78,9 @@ static inline void fdt_fixup_crypto_node(void *blob, int sec_rev) {}
int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose);
#endif
-#ifdef CONFIG_OF_BOARD_SETUP
void ft_board_setup(void *blob, bd_t *bd);
void ft_cpu_setup(void *blob, bd_t *bd);
void ft_pci_setup(void *blob, bd_t *bd);
-#endif
void set_working_fdt_addr(void *addr);
int fdt_resize(void *blob);
diff --git a/include/fm_eth.h b/include/fm_eth.h
index 495765b..8fcf172 100644
--- a/include/fm_eth.h
+++ b/include/fm_eth.h
@@ -88,7 +88,7 @@ enum fm_eth_type {
#define FM_TGEC_INFO_INITIALIZER(idx, n) \
{ \
- FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
+ FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR) \
.index = idx, \
.num = n - 1, \
.type = FM_ETH_10G_E, \
@@ -96,7 +96,7 @@ enum fm_eth_type {
.rx_port_id = RX_PORT_10G_BASE + n - 1, \
.tx_port_id = TX_PORT_10G_BASE + n - 1, \
.compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
- offsetof(struct ccsr_fman, memac[n-1]),\
+ offsetof(struct ccsr_fman, memac[n-1+8]),\
}
#else
#define FM_DTSEC_INFO_INITIALIZER(idx, n) \
diff --git a/include/hash.h b/include/hash.h
index 2dbbd9b..c402067 100644
--- a/include/hash.h
+++ b/include/hash.h
@@ -71,4 +71,26 @@ enum {
int hash_command(const char *algo_name, int flags, cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[]);
+/**
+ * hash_block() - Hash a block according to the requested algorithm
+ *
+ * The caller probably knows the hash length for the chosen algorithm, but
+ * in order to provide a general interface, and output_size parameter is
+ * provided.
+ *
+ * @algo_name: Hash algorithm to use
+ * @data: Data to hash
+ * @len: Lengh of data to hash in bytes
+ * @output: Place to put hash value
+ * @output_size: On entry, pointer to the number of bytes available in
+ * output. On exit, pointer to the number of bytes used.
+ * If NULL, then it is assumed that the caller has
+ * allocated enough space for the hash. This is possible
+ * since the caller is selecting the algorithm.
+ * @return 0 if ok, -ve on error: -EPROTONOSUPPORT for an unknown algorithm,
+ * -ENOSPC if the output buffer is not large enough.
+ */
+int hash_block(const char *algo_name, const void *data, unsigned int len,
+ uint8_t *output, int *output_size);
+
#endif
diff --git a/include/image.h b/include/image.h
index 4ad0e6b..b8cc523 100644
--- a/include/image.h
+++ b/include/image.h
@@ -36,6 +36,9 @@
#include "compiler.h"
#include <asm/byteorder.h>
+/* Define this to avoid #ifdefs later on */
+struct lmb;
+
#ifdef USE_HOSTCC
/* new uImage format support enabled on host */
@@ -43,19 +46,79 @@
#define CONFIG_OF_LIBFDT 1
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
+#define IMAGE_ENABLE_IGNORE 0
+#define IMAGE_INDENT_STRING ""
+
#else
#include <lmb.h>
#include <asm/u-boot.h>
#include <command.h>
+/* Take notice of the 'ignore' property for hashes */
+#define IMAGE_ENABLE_IGNORE 1
+#define IMAGE_INDENT_STRING " "
+
#endif /* USE_HOSTCC */
#if defined(CONFIG_FIT)
#include <libfdt.h>
#include <fdt_support.h>
-#define CONFIG_MD5 /* FIT images need MD5 support */
-#define CONFIG_SHA1 /* and SHA1 */
+# ifdef CONFIG_SPL_BUILD
+# ifdef CONFIG_SPL_CRC32_SUPPORT
+# define IMAGE_ENABLE_CRC32 1
+# endif
+# ifdef CONFIG_SPL_MD5_SUPPORT
+# define IMAGE_ENABLE_MD5 1
+# endif
+# ifdef CONFIG_SPL_SHA1_SUPPORT
+# define IMAGE_ENABLE_SHA1 1
+# endif
+# else
+# define CONFIG_CRC32 /* FIT images need CRC32 support */
+# define CONFIG_MD5 /* and MD5 */
+# define CONFIG_SHA1 /* and SHA1 */
+# define IMAGE_ENABLE_CRC32 1
+# define IMAGE_ENABLE_MD5 1
+# define IMAGE_ENABLE_SHA1 1
+# endif
+
+#ifndef IMAGE_ENABLE_CRC32
+#define IMAGE_ENABLE_CRC32 0
+#endif
+
+#ifndef IMAGE_ENABLE_MD5
+#define IMAGE_ENABLE_MD5 0
+#endif
+
+#ifndef IMAGE_ENABLE_SHA1
+#define IMAGE_ENABLE_SHA1 0
+#endif
+
+#endif /* CONFIG_FIT */
+
+#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
+# define IMAGE_ENABLE_RAMDISK_HIGH 1
+#else
+# define IMAGE_ENABLE_RAMDISK_HIGH 0
+#endif
+
+#ifdef CONFIG_OF_LIBFDT
+# define IMAGE_ENABLE_OF_LIBFDT 1
+#else
+# define IMAGE_ENABLE_OF_LIBFDT 0
+#endif
+
+#ifdef CONFIG_SYS_BOOT_GET_CMDLINE
+# define IMAGE_BOOT_GET_CMDLINE 1
+#else
+# define IMAGE_BOOT_GET_CMDLINE 0
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+# define IMAAGE_OF_BOARD_SETUP 1
+#else
+# define IMAAGE_OF_BOARD_SETUP 0
#endif
/*
@@ -244,9 +307,7 @@ typedef struct bootm_headers {
ulong rd_start, rd_end;/* ramdisk start/end */
-#ifdef CONFIG_OF_LIBFDT
char *ft_addr; /* flat dev tree address */
-#endif
ulong ft_len; /* length of flat device tree */
ulong initrd_start;
@@ -333,34 +394,35 @@ int genimg_get_type_id(const char *name);
int genimg_get_comp_id(const char *name);
void genimg_print_size(uint32_t size);
+#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || \
+ defined(USE_HOSTCC)
+#define IMAGE_ENABLE_TIMESTAMP 1
+#else
+#define IMAGE_ENABLE_TIMESTAMP 0
+#endif
+void genimg_print_time(time_t timestamp);
+
#ifndef USE_HOSTCC
/* Image format types, returned by _get_format() routine */
#define IMAGE_FORMAT_INVALID 0x00
#define IMAGE_FORMAT_LEGACY 0x01 /* legacy image_header based format */
#define IMAGE_FORMAT_FIT 0x02 /* new, libfdt based format */
-int genimg_get_format(void *img_addr);
+int genimg_get_format(const void *img_addr);
int genimg_has_config(bootm_headers_t *images);
ulong genimg_get_image(ulong img_addr);
int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images,
uint8_t arch, ulong *rd_start, ulong *rd_end);
-
-#ifdef CONFIG_OF_LIBFDT
int boot_get_fdt(int flag, int argc, char * const argv[],
bootm_headers_t *images, char **of_flat_tree, ulong *of_size);
void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob);
int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size);
-#endif
-#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len,
ulong *initrd_start, ulong *initrd_end);
-#endif /* CONFIG_SYS_BOOT_RAMDISK_HIGH */
-#ifdef CONFIG_SYS_BOOT_GET_CMDLINE
int boot_get_cmdline(struct lmb *lmb, ulong *cmd_start, ulong *cmd_end);
-#endif /* CONFIG_SYS_BOOT_GET_CMDLINE */
#ifdef CONFIG_SYS_BOOT_GET_KBD
int boot_get_kbd(struct lmb *lmb, bd_t **kbd);
#endif /* CONFIG_SYS_BOOT_GET_KBD */
@@ -502,6 +564,31 @@ static inline int image_check_target_arch(const image_header_t *hdr)
}
#endif /* USE_HOSTCC */
+/**
+ * Set up properties in the FDT
+ *
+ * This sets up properties in the FDT that is to be passed to linux.
+ *
+ * @images: Images information
+ * @blob: FDT to update
+ * @of_size: Size of the FDT
+ * @lmb: Points to logical memory block structure
+ * @return 0 if ok, <0 on failure
+ */
+int image_setup_libfdt(bootm_headers_t *images, void *blob,
+ int of_size, struct lmb *lmb);
+
+/**
+ * Set up the FDT to use for booting a kernel
+ *
+ * This performs ramdisk setup, sets up the FDT if required, and adds
+ * paramters to the FDT if libfdt is available.
+ *
+ * @param images Images information
+ * @return 0 if ok, <0 on failure
+ */
+int image_setup_linux(bootm_headers_t *images);
+
/*******************************************************************/
/* New uImage format specific code (prefixed with fit_) */
/*******************************************************************/
@@ -543,7 +630,6 @@ int fit_parse_subimage(const char *spec, ulong addr_curr,
void fit_print_contents(const void *fit);
void fit_image_print(const void *fit, int noffset, const char *p);
-void fit_image_print_hash(const void *fit, int noffset, const char *p);
/**
* fit_get_end - get FIT image size
@@ -599,18 +685,19 @@ int fit_image_get_data(const void *fit, int noffset,
int fit_image_hash_get_algo(const void *fit, int noffset, char **algo);
int fit_image_hash_get_value(const void *fit, int noffset, uint8_t **value,
int *value_len);
-#ifndef USE_HOSTCC
-int fit_image_hash_get_ignore(const void *fit, int noffset, int *ignore);
-#endif
int fit_set_timestamp(void *fit, int noffset, time_t timestamp);
-int fit_set_hashes(void *fit);
-int fit_image_set_hashes(void *fit, int image_noffset);
-int fit_image_hash_set_value(void *fit, int noffset, uint8_t *value,
- int value_len);
-int fit_image_check_hashes(const void *fit, int noffset);
-int fit_all_image_check_hashes(const void *fit);
+/**
+ * fit_add_verification_data() - Calculate and add hashes to FIT
+ *
+ * @fit: Fit image to process
+ * @return 0 if ok, <0 for error
+ */
+int fit_add_verification_data(void *fit);
+
+int fit_image_verify(const void *fit, int noffset);
+int fit_all_image_verify(const void *fit);
int fit_image_check_os(const void *fit, int noffset, uint8_t os);
int fit_image_check_arch(const void *fit, int noffset, uint8_t arch);
int fit_image_check_type(const void *fit, int noffset, uint8_t type);
@@ -623,8 +710,28 @@ int fit_conf_get_kernel_node(const void *fit, int noffset);
int fit_conf_get_ramdisk_node(const void *fit, int noffset);
int fit_conf_get_fdt_node(const void *fit, int noffset);
+/**
+ * fit_conf_get_prop_node() - Get node refered to by a configuration
+ * @fit: FIT to check
+ * @noffset: Offset of conf@xxx node to check
+ * @prop_name: Property to read from the conf node
+ *
+ * The conf@ nodes contain references to other nodes, using properties
+ * like 'kernel = "kernel@1"'. Given such a property name (e.g. "kernel"),
+ * return the offset of the node referred to (e.g. offset of node
+ * "/images/kernel@1".
+ */
+int fit_conf_get_prop_node(const void *fit, int noffset,
+ const char *prop_name);
+
void fit_conf_print(const void *fit, int noffset, const char *p);
+int fit_check_ramdisk(const void *fit, int os_noffset,
+ uint8_t arch, int verify);
+
+int calculate_hash(const void *data, int data_len, const char *algo,
+ uint8_t *value, int *value_len);
+
#ifndef USE_HOSTCC
static inline int fit_image_check_target_arch(const void *fdt, int node)
{
diff --git a/include/libfdt.h b/include/libfdt.h
index fc7f75b..c5ec2ac 100644
--- a/include/libfdt.h
+++ b/include/libfdt.h
@@ -136,6 +136,28 @@ uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset);
int fdt_next_node(const void *fdt, int offset, int *depth);
+/**
+ * fdt_first_subnode() - get offset of first direct subnode
+ *
+ * @fdt: FDT blob
+ * @offset: Offset of node to check
+ * @return offset of first subnode, or -FDT_ERR_NOTFOUND if there is none
+ */
+int fdt_first_subnode(const void *fdt, int offset);
+
+/**
+ * fdt_next_subnode() - get offset of next direct subnode
+ *
+ * After first calling fdt_first_subnode(), call this function repeatedly to
+ * get direct subnodes of a parent node.
+ *
+ * @fdt: FDT blob
+ * @offset: Offset of previous subnode
+ * @return offset of next subnode, or -FDT_ERR_NOTFOUND if there are no more
+ * subnodes
+ */
+int fdt_next_subnode(const void *fdt, int offset);
+
/**********************************************************************/
/* General functions */
/**********************************************************************/
@@ -582,7 +604,7 @@ const char *fdt_get_alias_namelen(const void *fdt,
* value of the property named 'name' in the node /aliases.
*
* returns:
- * a pointer to the expansion of the alias named 'name', of it exists
+ * a pointer to the expansion of the alias named 'name', if it exists
* NULL, if the given alias or the /aliases node does not exist
*/
const char *fdt_get_alias(const void *fdt, const char *name);
@@ -816,6 +838,20 @@ int fdt_node_check_compatible(const void *fdt, int nodeoffset,
int fdt_node_offset_by_compatible(const void *fdt, int startoffset,
const char *compatible);
+/**
+ * fdt_stringlist_contains - check a string list property for a string
+ * @strlist: Property containing a list of strings to check
+ * @listlen: Length of property
+ * @str: String to search for
+ *
+ * This is a utility function provided for convenience. The list contains
+ * one or more strings, each terminated by \0, as is found in a device tree
+ * "compatible" property.
+ *
+ * @return: 1 if the string is found in the list, 0 not found, or invalid list
+ */
+int fdt_stringlist_contains(const char *strlist, int listlen, const char *str);
+
/**********************************************************************/
/* Write-in-place functions */
/**********************************************************************/
diff --git a/include/libfdt_env.h b/include/libfdt_env.h
index 3e3defc..0821258 100644
--- a/include/libfdt_env.h
+++ b/include/libfdt_env.h
@@ -35,4 +35,7 @@ typedef __be64 fdt64_t;
#define fdt64_to_cpu(x) be64_to_cpu(x)
#define cpu_to_fdt64(x) cpu_to_be64(x)
+/* adding a ramdisk needs 0x44 bytes in version 2008.10 */
+#define FDT_RAMDISK_OVERHEAD 0x80
+
#endif /* _LIBFDT_ENV_H */
diff --git a/include/lmb.h b/include/lmb.h
index 5d1f4b6..43082a3 100644
--- a/include/lmb.h
+++ b/include/lmb.h
@@ -1,7 +1,6 @@
#ifndef _LINUX_LMB_H
#define _LINUX_LMB_H
#ifdef __KERNEL__
-#ifdef CONFIG_LMB
#include <asm/types.h>
/*
@@ -57,7 +56,6 @@ lmb_size_bytes(struct lmb_region *type, unsigned long region_nr)
void board_lmb_reserve(struct lmb *lmb);
void arch_lmb_reserve(struct lmb *lmb);
-#endif /* CONFIG_LMB */
#endif /* __KERNEL__ */
#endif /* _LINUX_LMB_H */
diff --git a/include/mmc.h b/include/mmc.h
index 8bbc6b6..566db59 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -68,6 +68,7 @@
#define UNUSABLE_ERR -17 /* Unusable Card */
#define COMM_ERR -18 /* Communications Error */
#define TIMEOUT -19
+#define IN_PROGRESS -20 /* operation is in progress */
#define MMC_CMD_GO_IDLE_STATE 0
#define MMC_CMD_SEND_OP_COND 1
@@ -270,6 +271,10 @@ struct mmc {
int (*getcd)(struct mmc *mmc);
int (*getwp)(struct mmc *mmc);
uint b_max;
+ char op_cond_pending; /* 1 if we are waiting on an op_cond command */
+ char init_in_progress; /* 1 if we have done mmc_start_init() */
+ char preinit; /* start init as early as possible */
+ uint op_cond_response; /* the response byte from the last op_cond */
};
int mmc_register(struct mmc *mmc);
@@ -287,6 +292,31 @@ int mmc_getcd(struct mmc *mmc);
int mmc_getwp(struct mmc *mmc);
void spl_mmc_load(void) __noreturn;
+/**
+ * Start device initialization and return immediately; it does not block on
+ * polling OCR (operation condition register) status. Then you should call
+ * mmc_init, which would block on polling OCR status and complete the device
+ * initializatin.
+ *
+ * @param mmc Pointer to a MMC device struct
+ * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error.
+ */
+int mmc_start_init(struct mmc *mmc);
+
+/**
+ * Set preinit flag of mmc device.
+ *
+ * This will cause the device to be pre-inited during mmc_initialize(),
+ * which may save boot time if the device is not accessed until later.
+ * Some eMMC devices take 200-300ms to init, but unfortunately they
+ * must be sent a series of commands to even get them to start preparing
+ * for operation.
+ *
+ * @param mmc Pointer to a MMC device struct
+ * @param preinit preinit flag value
+ */
+void mmc_set_preinit(struct mmc *mmc, int preinit);
+
#ifdef CONFIG_GENERIC_MMC
#define mmc_host_is_spi(mmc) ((mmc)->host_caps & MMC_MODE_SPI)
struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
diff --git a/include/mpc8220.h b/include/mpc8220.h
deleted file mode 100644
index c4900a0..0000000
--- a/include/mpc8220.h
+++ /dev/null
@@ -1,717 +0,0 @@
-/*
- * include/mpc8220.h
- *
- * Prototypes, etc. for the Motorola MPC8220
- * embedded cpu chips
- *
- * 2004 (c) Freescale, Inc.
- * Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef __MPC8220_H__
-#define __MPC8220_H__
-
-/* Processor name */
-#if defined(CONFIG_MPC8220)
-#define CPU_ID_STR "MPC8220"
-#endif
-
-/* Exception offsets (PowerPC standard) */
-#define EXC_OFF_SYS_RESET 0x0100
-#define _START_OFFSET EXC_OFF_SYS_RESET
-
-/* Internal memory map */
-/* MPC8220 Internal Register MMAP */
-#define MMAP_MBAR (CONFIG_SYS_MBAR + 0x00000000) /* chip selects */
-#define MMAP_MEMCTL (CONFIG_SYS_MBAR + 0x00000100) /* sdram controller */
-#define MMAP_XLBARB (CONFIG_SYS_MBAR + 0x00000200) /* xlb arbitration control */
-#define MMAP_CDM (CONFIG_SYS_MBAR + 0x00000300) /* clock distribution module */
-#define MMAP_VDOPLL (CONFIG_SYS_MBAR + 0x00000400) /* video PLL */
-#define MMAP_FB (CONFIG_SYS_MBAR + 0x00000500) /* flex bus controller */
-#define MMAP_PCFG (CONFIG_SYS_MBAR + 0x00000600) /* port config */
-#define MMAP_ICTL (CONFIG_SYS_MBAR + 0x00000700) /* interrupt controller */
-#define MMAP_GPTMR (CONFIG_SYS_MBAR + 0x00000800) /* general purpose timers */
-#define MMAP_SLTMR (CONFIG_SYS_MBAR + 0x00000900) /* slice timers */
-#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000A00) /* gpio module */
-#define MMAP_XCPCI (CONFIG_SYS_MBAR + 0x00000B00) /* pci controller */
-#define MMAP_PCIARB (CONFIG_SYS_MBAR + 0x00000C00) /* pci arbiter */
-#define MMAP_EXTDMA1 (CONFIG_SYS_MBAR + 0x00000D00) /* external dma1 */
-#define MMAP_EXTDMA2 (CONFIG_SYS_MBAR + 0x00000E00) /* external dma1 */
-#define MMAP_USBH (CONFIG_SYS_MBAR + 0x00001000) /* usb host */
-#define MMAP_CMTMR (CONFIG_SYS_MBAR + 0x00007f00) /* comm timers */
-#define MMAP_DMA (CONFIG_SYS_MBAR + 0x00008000) /* dma */
-#define MMAP_USBD (CONFIG_SYS_MBAR + 0x00008200) /* usb device */
-#define MMAP_COMMPCI (CONFIG_SYS_MBAR + 0x00008400) /* pci comm Bus regs */
-#define MMAP_1284 (CONFIG_SYS_MBAR + 0x00008500) /* 1284 */
-#define MMAP_PEV (CONFIG_SYS_MBAR + 0x00008600) /* print engine video */
-#define MMAP_PSC1 (CONFIG_SYS_MBAR + 0x00008800) /* psc1 block */
-#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00008f00) /* i2c controller */
-#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00009000) /* fast ethernet 1 */
-#define MMAP_FEC2 (CONFIG_SYS_MBAR + 0x00009800) /* fast ethernet 2 */
-#define MMAP_JBIGRAM (CONFIG_SYS_MBAR + 0x0000a000) /* jbig RAM */
-#define MMAP_JBIG (CONFIG_SYS_MBAR + 0x0000c000) /* jbig */
-#define MMAP_PDLA (CONFIG_SYS_MBAR + 0x00010000) /* */
-#define MMAP_SRAMCFG (CONFIG_SYS_MBAR + 0x0001ff00) /* SRAM config */
-#define MMAP_SRAM (CONFIG_SYS_MBAR + 0x00020000) /* SRAM */
-
-#define SRAM_SIZE 0x8000 /* 32 KB */
-
-/* ------------------------------------------------------------------------ */
-/*
- * Macro for Programmable Serial Channel
- */
-/* equates for mode reg. 1 for channel A or B */
-#define PSC_MR1_RX_RTS 0x80000000 /* receiver RTS enabled */
-#define PSC_MR1_RX_INT 0x40000000 /* receiver intrupt enabled */
-#define PSC_MR1_ERR_MODE 0x20000000 /* block error mode */
-#define PSC_MR1_PAR_MODE_MULTI 0x18000000 /* multi_drop mode */
-#define PSC_MR1_NO_PARITY 0x10000000 /* no parity mode */
-#define PSC_MR1_ALWAYS_0 0x08000000 /* force parity mode */
-#define PSC_MR1_ALWAYS_1 0x0c000000 /* force parity mode */
-#define PSC_MR1_EVEN_PARITY 0x00000000 /* parity mode */
-#define PSC_MR1_ODD_PARITY 0x04000000 /* 0 = even, 1 = odd */
-#define PSC_MR1_BITS_CHAR_8 0x03000000 /* 8 bits */
-#define PSC_MR1_BITS_CHAR_7 0x02000000 /* 7 bits */
-#define PSC_MR1_BITS_CHAR_6 0x01000000 /* 6 bits */
-#define PSC_MR1_BITS_CHAR_5 0x00000000 /* 5 bits */
-
-/* equates for mode reg. 2 for channel A or B */
-#define PSC_MR2_NORMAL_MODE 0x00000000 /* normal channel mode */
-#define PSC_MR2_AUTO_MODE 0x40000000 /* automatic channel mode */
-#define PSC_MR2_LOOPBACK_LOCL 0x80000000 /* local loopback channel mode */
-#define PSC_MR2_LOOPBACK_REMT 0xc0000000 /* remote loopback channel mode */
-#define PSC_MR2_TX_RTS 0x20000000 /* transmitter RTS enabled */
-#define PSC_MR2_TX_CTS 0x10000000 /* transmitter CTS enabled */
-#define PSC_MR2_STOP_BITS_2 0x0f000000 /* 2 stop bits */
-#define PSC_MR2_STOP_BITS_1 0x07000000 /* 1 stop bit */
-
-/* equates for status reg. A or B */
-#define PSC_SR_BREAK 0x80000000 /* received break */
-#define PSC_SR_NEOF PSC_SR_BREAK /* Next byte is EOF - MIR/FIR */
-#define PSC_SR_FRAMING 0x40000000 /* framing error */
-#define PSC_SR_PHYERR PSC_SR_FRAMING/* Physical Layer error - MIR/FIR */
-#define PSC_SR_PARITY 0x20000000 /* parity error */
-#define PSC_SR_CRCERR PSC_SR_PARITY /* CRC error */
-#define PSC_SR_OVERRUN 0x10000000 /* overrun error */
-#define PSC_SR_TXEMT 0x08000000 /* transmitter empty */
-#define PSC_SR_TXRDY 0x04000000 /* transmitter ready*/
-#define PSC_SR_FFULL 0x02000000 /* fifo full */
-#define PSC_SR_RXRDY 0x01000000 /* receiver ready */
-#define PSC_SR_DEOF 0x00800000 /* Detect EOF or RX-FIFO contain EOF */
-#define PSC_SR_ERR 0x00400000 /* Error Status including FIFO */
-
-/* equates for clock select reg. */
-#define PSC_CSRX16EXT_CLK 0x1110 /* x 16 ext_clock */
-#define PSC_CSRX1EXT_CLK 0x1111 /* x 1 ext_clock */
-
-/* equates for command reg. A or B */
-#define PSC_CR_NO_COMMAND 0x00000000 /* no command */
-#define PSC_CR_RST_MR_PTR_CMD 0x10000000 /* reset mr pointer command */
-#define PSC_CR_RST_RX_CMD 0x20000000 /* reset receiver command */
-#define PSC_CR_RST_TX_CMD 0x30000000 /* reset transmitter command */
-#define PSC_CR_RST_ERR_STS_CMD 0x40000000 /* reset error status cmnd */
-#define PSC_CR_RST_BRK_INT_CMD 0x50000000 /* reset break int. command */
-#define PSC_CR_STR_BREAK_CMD 0x60000000 /* start break command */
-#define PSC_CR_STP_BREAK_CMD 0x70000000 /* stop break command */
-#define PSC_CR_RX_ENABLE 0x01000000 /* receiver enabled */
-#define PSC_CR_RX_DISABLE 0x02000000 /* receiver disabled */
-#define PSC_CR_TX_ENABLE 0x04000000 /* transmitter enabled */
-#define PSC_CR_TX_DISABLE 0x08000000 /* transmitter disabled */
-
-/* equates for input port change reg. */
-#define PSC_IPCR_SYNC 0x80000000 /* Sync Detect */
-#define PSC_IPCR_D_CTS 0x10000000 /* Delta CTS */
-#define PSC_IPCR_CTS 0x01000000 /* CTS - current state of PSC_CTS */
-
-/* equates for auxiliary control reg. (timer and counter clock selects) */
-#define PSC_ACR_BRG 0x80000000 /* for 68681 compatibility
- baud rate gen select
- 0 = set 1; 1 = set 2
- equates are set 2 ONLY */
-#define PSC_ACR_TMR_EXT_CLK_16 0x70000000 /* xtnl clock divided by 16 */
-#define PSC_ACR_TMR_EXT_CLK 0x60000000 /* external clock */
-#define PSC_ACR_TMR_IP2_16 0x50000000 /* ip2 divided by 16 */
-#define PSC_ACR_TMR_IP2 0x40000000 /* ip2 */
-#define PSC_ACR_CTR_EXT_CLK_16 0x30000000 /* xtnl clock divided by 16 */
-#define PSC_ACR_CTR_TXCB 0x20000000 /* channel B xmitr clock */
-#define PSC_ACR_CTR_TXCA 0x10000000 /* channel A xmitr clock */
-#define PSC_ACR_CTR_IP2 0x00000000 /* ip2 */
-#define PSC_ACR_IEC0 0x01000000 /* interrupt enable ctrl for D_CTS */
-
-/* equates for int. status reg. */
-#define PSC_ISR_IPC 0x80000000 /* input port change*/
-#define PSC_ISR_BREAK 0x04000000 /* delta break */
-#define PSC_ISR_RX_RDY 0x02000000 /* receiver rdy /fifo full */
-#define PSC_ISR_TX_RDY 0x01000000 /* transmitter ready */
-#define PSC_ISR_DEOF 0x00800000 /* Detect EOF / RX-FIFO contains EOF */
-#define PSC_ISR_ERR 0x00400000 /* Error Status including FIFO */
-
-/* equates for int. mask reg. */
-#define PSC_IMR_CLEAR 0xff000000 /* Clear the imr */
-#define PSC_IMR_IPC 0x80000000 /* input port change*/
-#define PSC_IMR_BREAK 0x04000000 /* delta break */
-#define PSC_IMR_RX_RDY 0x02000000 /* rcvr ready / fifo full */
-#define PSC_IMR_TX_RDY 0x01000000 /* transmitter ready */
-#define PSC_IMR_DEOF 0x00800000 /* Detect EOF / RX-FIFO contains EOF */
-#define PSC_IMR_ERR 0x00400000 /* Error Status including FIFO */
-
-/* equates for input port reg. */
-#define PSC_IP_LPWRB 0x80000000 /* Low power mode in Ac97 */
-#define PSC_IP_TGL 0x40000000 /* test usage */
-#define PSC_IP_CTS 0x01000000 /* CTS */
-
-/* equates for output port bit set reg. */
-#define PSC_OPSET_RTS 0x01000000 /* Assert PSC_RTS output */
-
-/* equates for output port bit reset reg. */
-#define PSC_OPRESET_RTS 0x01000000 /* Assert PSC_RTS output */
-
-/* equates for rx FIFO number of data reg. */
-#define PSC_RFNUM(x) ((x&0xff)<<24)/* receive count */
-
-/* equates for tx FIFO number of data reg. */
-#define PSC_TFNUM(x) ((x&0xff)<<24)/* receive count */
-
-/* equates for rx FIFO status reg */
-#define PSC_RFSTAT_TAG(x) ((x&3)<<28) /* tag */
-#define PSC_RFSTAT_FRAME0 0x08 /* Frame Indicator 0 */
-#define PSC_RFSTAT_FRAME1 0x04 /* Frame Indicator 1 */
-#define PSC_RFSTAT_FRAME2 0x02 /* Frame Indicator 2 */
-#define PSC_RFSTAT_FRAME3 0x01 /* Frame Indicator 3 */
-#define PSC_RFSTAT_FRAME(x) ((x&0x0f)<<24)/* Frame indicator */
-#define PSC_RFSTAT_ERR 0x00400000 /* Fifo err */
-#define PSC_RFSTAT_UF 0x00200000 /* Underflow */
-#define PSC_RFSTAT_OF 0x00100000 /* overflow */
-#define PSC_RFSTAT_FR 0x00080000 /* frame ready */
-#define PSC_RFSTAT_FULL 0x00040000 /* full */
-#define PSC_RFSTAT_ALARM 0x00020000 /* alarm */
-#define PSC_RFSTAT_EMPTY 0x00010000 /* empty */
-
-/* equates for tx FIFO status reg */
-#define PSC_TFSTAT_TAG(x) ((x&3)<<28) /* tag */
-#define PSC_TFSTAT_FRAME0 0x08 /* Frame Indicator 0 */
-#define PSC_TFSTAT_FRAME1 0x04 /* Frame Indicator 1 */
-#define PSC_TFSTAT_FRAME2 0x02 /* Frame Indicator 2 */
-#define PSC_TFSTAT_FRAME3 0x01 /* Frame Indicator 3 */
-#define PSC_TFSTAT_FRAME(x) ((x&0x0f)<<24)/* Frame indicator */
-#define PSC_TFSTAT_ERR 0x00400000 /* Fifo err */
-#define PSC_TFSTAT_UF 0x00200000 /* Underflow */
-#define PSC_TFSTAT_OF 0x00100000 /* overflow */
-#define PSC_TFSTAT_FR 0x00080000 /* frame ready */
-#define PSC_TFSTAT_FULL 0x00040000 /* full */
-#define PSC_TFSTAT_ALARM 0x00020000 /* alarm */
-#define PSC_TFSTAT_EMPTY 0x00010000 /* empty */
-
-/* equates for rx FIFO control reg. */
-#define PSC_RFCNTL_WTAG(x) ((x&3)<<29) /* Write tag */
-#define PSC_RFCNTL_FRAME 0x08000000 /* Frame mode enable */
-#define PSC_RFCNTL_GR(x) ((x&7)<<24) /* Granularity */
-
-/* equates for tx FIFO control reg. */
-#define PSC_TFCNTL_WTAG(x) ((x&3)<<29) /* Write tag */
-#define PSC_TFCNTL_FRAME 0x08000000 /* Frame mode enable */
-#define PSC_TFCNTL_GR(x) ((x&7)<<24) /* Granularity */
-
-/* equates for rx FIFO alarm reg */
-#define PSC_RFALARM(x) (x&0x1ff) /* Alarm */
-
-/* equates for tx FIFO alarm reg */
-#define PSC_TFALARM(x) (x&0x1ff) /* Alarm */
-
-/* equates for rx FIFO read pointer */
-#define PSC_RFRPTR(x) (x&0x1ff) /* read pointer */
-
-/* equates for tx FIFO read pointer */
-#define PSC_TFRPTR(x) (x&0x1ff) /* read pointer */
-
-/* equates for rx FIFO write pointer */
-#define PSC_RFWPTR(x) (x&0x1ff) /* write pointer */
-
-/* equates for rx FIFO write pointer */
-#define PSC_TFWPTR(x) (x&0x1ff) /* write pointer */
-
-/* equates for rx FIFO last read frame pointer reg */
-#define PSC_RFLRFPTR(x) (x&0x1ff) /* last read frame pointer */
-
-/* equates for tx FIFO last read frame pointer reg */
-#define PSC_TFLRFPTR(x) (x&0x1ff) /* last read frame pointer */
-
-/* equates for rx FIFO last write frame pointer reg */
-#define PSC_RFLWFPTR(x) (x&0x1ff) /* last write frame pointer */
-
-/* equates for tx FIFO last write frame pointer reg */
-#define PSC_TFLWFPTR(x) (x&0x1ff) /* last write frame pointer */
-
-/* PCI configuration (only for PLL determination)*/
-#define PCI_REG_PCIGSCR (MMAP_XCPCI + 0x60) /* Global status/control register */
-#define PCI_REG_PCIGSCR_PCI2XLB_CLK_MASK 0x07000000
-#define PCI_REG_PCIGSCR_PCI2XLB_CLK_BIT 24
-
-#define PCI_REG_PCICAR (MMAP_XCPCI + 0xF8) /* Configuration Address Register */
-
-/* ------------------------------------------------------------------------ */
-/*
- * Macro for General Purpose Timer
- */
-/* Enable and Mode Select */
-#define GPT_OCT(x) (x & 0x3)<<4/* Output Compare Type */
-#define GPT_ICT(x) (x & 0x3) /* Input Capture Type */
-#define GPT_CTRL_WDEN 0x80 /* Watchdog Enable */
-#define GPT_CTRL_CE 0x10 /* Counter Enable */
-#define GPT_CTRL_STPCNT 0x04 /* Stop continous */
-#define GPT_CTRL_ODRAIN 0x02 /* Open Drain */
-#define GPT_CTRL_INTEN 0x01 /* Interrupt Enable */
-#define GPT_MODE_GPIO(x) (x & 0x3)<<4/* Gpio Mode Type */
-#define GPT_TMS_ICT 0x01 /* Input Capture Enable */
-#define GPT_TMS_OCT 0x02 /* Output Capture Enable */
-#define GPT_TMS_PWM 0x03 /* PWM Capture Enable */
-#define GPT_TMS_SGPIO 0x04 /* PWM Capture Enable */
-
-#define GPT_PWM_WIDTH(x) (x & 0xffff)
-
-/* Status */
-#define GPT_STA_CAPTURE(x) (x & 0xffff)/* Read of internal counter */
-
-#define GPT_OVFPIN_OVF(x) (x & 0x70) /* Internal counter roll over */
-#define GPT_OVFPIN_PIN 0x01 /* Input pin - Timer 0 and 1 */
-
-#define GPT_INT_TEXP 0x08 /* Timer Expired in Internal Timer mode */
-#define GPT_INT_PWMP 0x04 /* PWM end of period occurred */
-#define GPT_INT_COMP 0x02 /* OC reference event occurred */
-#define GPT_INT_CAPT 0x01 /* IC reference event occurred */
-
-/* ------------------------------------------------------------------------ */
-/*
- * Port configuration
- */
-#define CONFIG_SYS_FEC1_PORT0_CONFIG 0x00000000
-#define CONFIG_SYS_FEC1_PORT1_CONFIG 0x00000000
-#define CONFIG_SYS_1284_PORT0_CONFIG 0x00000000
-#define CONFIG_SYS_1284_PORT1_CONFIG 0x00000000
-#define CONFIG_SYS_FEC2_PORT2_CONFIG 0x00000000
-#define CONFIG_SYS_PEV_PORT2_CONFIG 0x00000000
-#define CONFIG_SYS_GP0_PORT0_CONFIG 0x00000000
-#define CONFIG_SYS_GP1_PORT2_CONFIG 0xaaaaaac0
-#define CONFIG_SYS_PSC_PORT3_CONFIG 0x00020000
-#define CONFIG_SYS_CS1_PORT3_CONFIG 0x00000000
-#define CONFIG_SYS_CS2_PORT3_CONFIG 0x10000000
-#define CONFIG_SYS_CS3_PORT3_CONFIG 0x40000000
-#define CONFIG_SYS_CS4_PORT3_CONFIG 0x00000400
-#define CONFIG_SYS_CS5_PORT3_CONFIG 0x00000200
-#define CONFIG_SYS_PCI_PORT3_CONFIG 0x01400180
-#define CONFIG_SYS_I2C_PORT3_CONFIG 0x00000000
-#define CONFIG_SYS_GP2_PORT3_CONFIG 0x000200a0
-
-/* ------------------------------------------------------------------------ */
-/*
- * DRAM configuration
- */
-
-/* Field definitions for the control register */
-#define CTL_MODE_ENABLE_SHIFT 31
-#define CTL_CKE_SHIFT 30
-#define CTL_DDR_SHIFT 29
-#define CTL_REFRESH_SHIFT 28
-#define CTL_ADDRMUX_SHIFT 24
-#define CTL_PRECHARGE_SHIFT 23
-#define CTL_DRIVE_RULE_SHIFT 22
-#define CTL_REFRESH_INTERVAL_SHIFT 16
-#define CTL_DQSOEN_SHIFT 8
-#define CTL_BUFFERED_SHIFT 4
-#define CTL_REFRESH_CMD_SHIFT 2
-#define CTL_PRECHARGE_CMD_SHIFT 1
-
-#define CTL_MODE_ENABLE (1<<CTL_MODE_ENABLE_SHIFT)
-#define CTL_CKE_HIGH (1<<CTL_CKE_SHIFT)
-#define CTL_DDR_MODE (1<<CTL_DDR_SHIFT)
-#define CTL_REFRESH_ENABLE (1<<CTL_REFRESH_SHIFT)
-#define CTL_ADDRMUX(value) ((value)<<CTL_ADDRMUX_SHIFT)
-#define CTL_A8PRECHARGE (1<<CTL_PRECHARGE_SHIFT)
-#define CTL_REFRESH_INTERVAL(value) ((value)<<CTL_REFRESH_INTERVAL_SHIFT)
-#define CTL_DQSOEN(value) ((value)<<CTL_DQSOEN_SHIFT)
-#define CTL_BUFFERED (1<<CTL_BUFFERED_SHIFT)
-#define CTL_REFRESH_CMD (1<<CTL_REFRESH_CMD_SHIFT)
-#define CTL_PRECHARGE_CMD (1<<CTL_PRECHARGE_CMD_SHIFT)
-
-/* Field definitions for config register 1 */
-
-#define CFG1_SRD2RWP_SHIFT 28
-#define CFG1_SWT2RWP_SHIFT 24
-#define CFG1_RLATENCY_SHIFT 20
-#define CFG1_ACT2WR_SHIFT 16
-#define CFG1_PRE2ACT_SHIFT 12
-#define CFG1_REF2ACT_SHIFT 8
-#define CFG1_WLATENCY_SHIFT 4
-
-#define CFG1_SRD2RWP(value) ((value)<<CFG1_SRD2RWP_SHIFT)
-#define CFG1_SWT2RWP(value) ((value)<<CFG1_SWT2RWP_SHIFT)
-#define CFG1_RLATENCY(value) ((value)<<CFG1_RLATENCY_SHIFT)
-#define CFG1_ACT2WR(value) ((value)<<CFG1_ACT2WR_SHIFT)
-#define CFG1_PRE2ACT(value) ((value)<<CFG1_PRE2ACT_SHIFT)
-#define CFG1_REF2ACT(value) ((value)<<CFG1_REF2ACT_SHIFT)
-#define CFG1_WLATENCY(value) ((value)<<CFG1_WLATENCY_SHIFT)
-
-/* Field definitions for config register 2 */
-#define CFG2_BRD2RP_SHIFT 28
-#define CFG2_BWT2RWP_SHIFT 24
-#define CFG2_BRD2WT_SHIFT 20
-#define CFG2_BURSTLEN_SHIFT 16
-
-#define CFG2_BRD2RP(value) ((value)<<CFG2_BRD2RP_SHIFT)
-#define CFG2_BWT2RWP(value) ((value)<<CFG2_BWT2RWP_SHIFT)
-#define CFG2_BRD2WT(value) ((value)<<CFG2_BRD2WT_SHIFT)
-#define CFG2_BURSTLEN(value) ((value)<<CFG2_BURSTLEN_SHIFT)
-
-/* Field definitions for the mode/extended mode register - mode
- * register access
- */
-#define MODE_REG_SHIFT 30
-#define MODE_OPMODE_SHIFT 25
-#define MODE_CL_SHIFT 22
-#define MODE_BT_SHIFT 21
-#define MODE_BURSTLEN_SHIFT 18
-#define MODE_CMD_SHIFT 16
-
-#define MODE_MODE 0
-#define MODE_OPMODE(value) ((value)<<MODE_OPMODE_SHIFT)
-#define MODE_CL(value) ((value)<<MODE_CL_SHIFT)
-#define MODE_BT_INTERLEAVED (1<<MODE_BT_SHIFT)
-#define MODE_BT_SEQUENTIAL (0<<MODE_BT_SHIFT)
-#define MODE_BURSTLEN(value) ((value)<<MODE_BURSTLEN_SHIFT)
-#define MODE_CMD (1<<MODE_CMD_SHIFT)
-
-#define MODE_BURSTLEN_8 3
-#define MODE_BURSTLEN_4 2
-#define MODE_BURSTLEN_2 1
-
-#define MODE_CL_2 2
-#define MODE_CL_2p5 6
-#define MODE_OPMODE_NORMAL 0
-#define MODE_OPMODE_RESETDLL 2
-
-
-/* Field definitions for the mode/extended mode register - extended
- * mode register access
- */
-#define MODE_X_DLL_SHIFT 18 /* DLL enable/disable */
-#define MODE_X_DS_SHIFT 19 /* Drive strength normal/reduced */
-#define MODE_X_QFC_SHIFT 20 /* QFC function (whatever that is) */
-#define MODE_X_OPMODE_SHIFT 21
-
-#define MODE_EXTENDED (1<<MODE_REG_SHIFT)
-#define MODE_X_DLL_ENABLE 0
-#define MODE_X_DLL_DISABLE (1<<MODE_X_DLL_SHIFT)
-#define MODE_X_DS_NORMAL 0
-#define MODE_X_DS_REDUCED (1<<MODE_X_DS_SHIFT)
-#define MODE_X_QFC_DISABLED 0
-#define MODE_X_OPMODE(value) ((value)<<MODE_X_OPMODE_SHIFT)
-
-#ifndef __ASSEMBLY__
-/*
- * DMA control/status registers.
- */
-struct mpc8220_dma {
- u32 taskBar; /* DMA + 0x00 */
- u32 currentPointer; /* DMA + 0x04 */
- u32 endPointer; /* DMA + 0x08 */
- u32 variablePointer;/* DMA + 0x0c */
-
- u8 IntVect1; /* DMA + 0x10 */
- u8 IntVect2; /* DMA + 0x11 */
- u16 PtdCntrl; /* DMA + 0x12 */
-
- u32 IntPend; /* DMA + 0x14 */
- u32 IntMask; /* DMA + 0x18 */
-
- u16 tcr_0; /* DMA + 0x1c */
- u16 tcr_1; /* DMA + 0x1e */
- u16 tcr_2; /* DMA + 0x20 */
- u16 tcr_3; /* DMA + 0x22 */
- u16 tcr_4; /* DMA + 0x24 */
- u16 tcr_5; /* DMA + 0x26 */
- u16 tcr_6; /* DMA + 0x28 */
- u16 tcr_7; /* DMA + 0x2a */
- u16 tcr_8; /* DMA + 0x2c */
- u16 tcr_9; /* DMA + 0x2e */
- u16 tcr_a; /* DMA + 0x30 */
- u16 tcr_b; /* DMA + 0x32 */
- u16 tcr_c; /* DMA + 0x34 */
- u16 tcr_d; /* DMA + 0x36 */
- u16 tcr_e; /* DMA + 0x38 */
- u16 tcr_f; /* DMA + 0x3a */
-
- u8 IPR0; /* DMA + 0x3c */
- u8 IPR1; /* DMA + 0x3d */
- u8 IPR2; /* DMA + 0x3e */
- u8 IPR3; /* DMA + 0x3f */
- u8 IPR4; /* DMA + 0x40 */
- u8 IPR5; /* DMA + 0x41 */
- u8 IPR6; /* DMA + 0x42 */
- u8 IPR7; /* DMA + 0x43 */
- u8 IPR8; /* DMA + 0x44 */
- u8 IPR9; /* DMA + 0x45 */
- u8 IPR10; /* DMA + 0x46 */
- u8 IPR11; /* DMA + 0x47 */
- u8 IPR12; /* DMA + 0x48 */
- u8 IPR13; /* DMA + 0x49 */
- u8 IPR14; /* DMA + 0x4a */
- u8 IPR15; /* DMA + 0x4b */
- u8 IPR16; /* DMA + 0x4c */
- u8 IPR17; /* DMA + 0x4d */
- u8 IPR18; /* DMA + 0x4e */
- u8 IPR19; /* DMA + 0x4f */
- u8 IPR20; /* DMA + 0x50 */
- u8 IPR21; /* DMA + 0x51 */
- u8 IPR22; /* DMA + 0x52 */
- u8 IPR23; /* DMA + 0x53 */
- u8 IPR24; /* DMA + 0x54 */
- u8 IPR25; /* DMA + 0x55 */
- u8 IPR26; /* DMA + 0x56 */
- u8 IPR27; /* DMA + 0x57 */
- u8 IPR28; /* DMA + 0x58 */
- u8 IPR29; /* DMA + 0x59 */
- u8 IPR30; /* DMA + 0x5a */
- u8 IPR31; /* DMA + 0x5b */
-
- u32 res1; /* DMA + 0x5c */
- u32 res2; /* DMA + 0x60 */
- u32 res3; /* DMA + 0x64 */
- u32 MDEDebug; /* DMA + 0x68 */
- u32 ADSDebug; /* DMA + 0x6c */
- u32 Value1; /* DMA + 0x70 */
- u32 Value2; /* DMA + 0x74 */
- u32 Control; /* DMA + 0x78 */
- u32 Status; /* DMA + 0x7c */
- u32 EU00; /* DMA + 0x80 */
- u32 EU01; /* DMA + 0x84 */
- u32 EU02; /* DMA + 0x88 */
- u32 EU03; /* DMA + 0x8c */
- u32 EU04; /* DMA + 0x90 */
- u32 EU05; /* DMA + 0x94 */
- u32 EU06; /* DMA + 0x98 */
- u32 EU07; /* DMA + 0x9c */
- u32 EU10; /* DMA + 0xa0 */
- u32 EU11; /* DMA + 0xa4 */
- u32 EU12; /* DMA + 0xa8 */
- u32 EU13; /* DMA + 0xac */
- u32 EU14; /* DMA + 0xb0 */
- u32 EU15; /* DMA + 0xb4 */
- u32 EU16; /* DMA + 0xb8 */
- u32 EU17; /* DMA + 0xbc */
- u32 EU20; /* DMA + 0xc0 */
- u32 EU21; /* DMA + 0xc4 */
- u32 EU22; /* DMA + 0xc8 */
- u32 EU23; /* DMA + 0xcc */
- u32 EU24; /* DMA + 0xd0 */
- u32 EU25; /* DMA + 0xd4 */
- u32 EU26; /* DMA + 0xd8 */
- u32 EU27; /* DMA + 0xdc */
- u32 EU30; /* DMA + 0xe0 */
- u32 EU31; /* DMA + 0xe4 */
- u32 EU32; /* DMA + 0xe8 */
- u32 EU33; /* DMA + 0xec */
- u32 EU34; /* DMA + 0xf0 */
- u32 EU35; /* DMA + 0xf4 */
- u32 EU36; /* DMA + 0xf8 */
- u32 EU37; /* DMA + 0xfc */
-};
-
-/*
- * PCI Header Registers
- */
-typedef struct mpc8220_xcpci {
- u32 dev_ven_id; /* 0xb00 - device/vendor ID */
- u32 stat_cmd_reg; /* 0xb04 - status command register */
- u32 class_code_rev_id; /* 0xb08 - class code / revision ID */
- u32 bist_htyp_lat_cshl; /* 0xb0c - BIST/HeaderType/Latency/cache line */
- u32 base0; /* 0xb10 - base address 0 */
- u32 base1; /* 0xb14 - base address 1 */
- u32 reserved1[4]; /* 0xb18->0xd27 - base address 2 - 5 */
- u32 cis; /* 0xb28 - cardBus CIS pointer */
- u32 sub_sys_ven_id; /* 0xb2c - sub system ID/ subsystem vendor ID */
- u32 reserved2; /* 0xb30 - expansion ROM base address */
- u32 reserved3; /* 0xb00 - reserved */
- u32 reserved4; /* 0xb00 - reserved */
- u32 mlat_mgnt_ipl; /* 0xb3c - MaxLat/MinGnt/ int pin/int line */
- u32 reserved5[8];
- /* MPC8220 specific - not accessible in PCI header space externally */
- u32 glb_stat_ctl; /* 0xb60 - Global Status Control */
- u32 target_bar0; /* 0xb64 - Target Base Address 0 */
- u32 target_bar1; /* 0xb68 - Target Base Address 1 */
- u32 target_ctrl; /* 0xb6c - Target Control */
- u32 init_win0; /* 0xb70 - Initiator Window 0 Base/Translation */
- u32 init_win1; /* 0xb74 - Initiator Window 1 Base/Translation */
- u32 init_win2; /* 0xb78 - Initiator Window 2 Base/Translation */
- u32 reserved6; /* 0xb7c - reserved */
- u32 init_win_cfg; /* 0xb80 */
- u32 init_ctrl; /* 0xb84 */
- u32 init_stat; /* 0xb88 */
- u32 reserved7[27];
- u32 cfg_adr; /* 0xbf8 */
- u32 reserved8;
-} mpc8220_xcpci_t;
-
-/* PCI->XLB space translation (MPC8220 target), reg0 can address max 256MB,
- reg1 - 1GB */
-#define PCI_BASE_ADDR_REG0 0x40000000
-#define PCI_BASE_ADDR_REG1 (CONFIG_SYS_SDRAM_BASE)
-#define PCI_TARGET_BASE_ADDR_REG0 (CONFIG_SYS_MBAR)
-#define PCI_TARGET_BASE_ADDR_REG1 (CONFIG_SYS_SDRAM_BASE)
-#define PCI_TARGET_BASE_ADDR_EN 1<<0
-
-
-/* PCI Global Status/Control Register (PCIGSCR) */
-#define PCI_GLB_STAT_CTRL_PE_SHIFT 29
-#define PCI_GLB_STAT_CTRL_SE_SHIFT 28
-#define PCI_GLB_STAT_CTRL_XLB_TO_PCI_CLK_SHIFT 24
-#define PCI_GLB_STAT_CTRL_XLB_TO_PCI_CLK_MASK 0x7
-#define PCI_GLB_STAT_CTRL_IPG_TO_PCI_CLK_SHIFT 16
-#define PCI_GLB_STAT_CTRL_IPG_TO_PCI_CLK_MASK 0x7
-#define PCI_GLB_STAT_CTRL_PEE_SHIFT 13
-#define PCI_GLB_STAT_CTRL_SEE_SHIFT 12
-#define PCI_GLB_STAT_CTRL_PR_SHIFT 0
-
-#define PCI_GLB_STAT_CTRL_PE (1<<PCI_GLB_STAT_CTRL_PE_SHIFT)
-#define PCI_GLB_STAT_CTRL_SE (1<<PCI_GLB_STAT_CTRL_SE_SHIFT)
-#define PCI_GLB_STAT_CTRL_PEE (1<<PCI_GLB_STAT_CTRL_PEE_SHIFT)
-#define PCI_GLB_STAT_CTRL_SEE (1<<PCI_GLB_STAT_CTRL_SEE_SHIFT)
-#define PCI_GLB_STAT_CTRL_PR (1<<PCI_GLB_STAT_CTRL_PR_SHIFT)
-
-/* PCI Target Control Register (PCITCR) */
-#define PCI_TARGET_CTRL_LD_SHIFT 24
-#define PCI_TARGET_CTRL_P_SHIFT 16
-
-#define PCI_TARGET_CTRL_LD (1<<PCI_TARGET_CTRL_LD_SHIFT)
-#define PCI_TARGET_CTRL_P (1<<PCI_TARGET_CTRL_P_SHIFT)
-
-/* PCI Initiator Window Configuration Register (PCIIWCR) */
-#define PCI_INIT_WIN_CFG_WIN0_CTRL_IO_SHIFT 27
-#define PCI_INIT_WIN_CFG_WIN0_CTRL_PRC_SHIFT 25
-#define PCI_INIT_WIN_CFG_WIN0_CTRL_PRC_MASK 0x3
-#define PCI_INIT_WIN_CFG_WIN0_CTRL_EN_SHIFT 24
-#define PCI_INIT_WIN_CFG_WIN1_CTRL_IO_SHIFT 19
-#define PCI_INIT_WIN_CFG_WIN1_CTRL_PRC_SHIFT 17
-#define PCI_INIT_WIN_CFG_WIN1_CTRL_PRC_MASK 0x3
-#define PCI_INIT_WIN_CFG_WIN1_CTRL_EN_SHIFT 16
-#define PCI_INIT_WIN_CFG_WIN2_CTRL_IO_SHIFT 11
-#define PCI_INIT_WIN_CFG_WIN2_CTRL_PRC_SHIFT 9
-#define PCI_INIT_WIN_CFG_WIN2_CTRL_PRC_MASK 0x3
-#define PCI_INIT_WIN_CFG_WIN2_CTRL_EN_SHIFT 8
-
-#define PCI_INIT_WIN_CFG_WIN_MEM_READ 0x0
-#define PCI_INIT_WIN_CFG_WIN_MEM_READ_LINE 0x1
-#define PCI_INIT_WIN_CFG_WIN_MEM_READ_MULTIPLE 0x2
-
-#define PCI_INIT_WIN_CFG_WIN0_CTRL_IO (1<<PCI_INIT_WIN_CFG_WIN0_CTRL_IO_SHIFT)
-#define PCI_INIT_WIN_CFG_WIN0_CTRL_EN (1<<PCI_INIT_WIN_CFG_WIN0_CTRL_EN_SHIFT)
-#define PCI_INIT_WIN_CFG_WIN1_CTRL_IO (1<<PCI_INIT_WIN_CFG_WIN1_CTRL_IO_SHIFT)
-#define PCI_INIT_WIN_CFG_WIN1_CTRL_EN (1<<PCI_INIT_WIN_CFG_WIN1_CTRL_EN_SHIFT)
-#define PCI_INIT_WIN_CFG_WIN2_CTRL_IO (1<<PCI_INIT_WIN_CFG_WIN2_CTRL_IO_SHIFT)
-#define PCI_INIT_WIN_CFG_WIN2_CTRL_EN (1<<PCI_INIT_WIN_CFG_WIN2_CTRL_EN_SHIFT)
-
-/* PCI Initiator Control Register (PCIICR) */
-#define PCI_INIT_CTRL_REE_SHIFT 26
-#define PCI_INIT_CTRL_IAE_SHIFT 25
-#define PCI_INIT_CTRL_TAE_SHIFT 24
-#define PCI_INIT_CTRL_MAX_RETRIES_SHIFT 0
-#define PCI_INIT_CTRL_MAX_RETRIES_MASK 0xff
-
-#define PCI_INIT_CTRL_REE (1<<PCI_INIT_CTRL_REE_SHIFT)
-#define PCI_INIT_CTRL_IAE (1<<PCI_INIT_CTRL_IAE_SHIFT)
-#define PCI_INIT_CTRL_TAE (1<<PCI_INIT_CTRL_TAE_SHIFT)
-
-/* PCI Status/Command Register (PCISCR) - PCI Dword 1 */
-#define PCI_STAT_CMD_PE_SHIFT 31
-#define PCI_STAT_CMD_SE_SHIFT 30
-#define PCI_STAT_CMD_MA_SHIFT 29
-#define PCI_STAT_CMD_TR_SHIFT 28
-#define PCI_STAT_CMD_TS_SHIFT 27
-#define PCI_STAT_CMD_DT_SHIFT 25
-#define PCI_STAT_CMD_DT_MASK 0x3
-#define PCI_STAT_CMD_DP_SHIFT 24
-#define PCI_STAT_CMD_FC_SHIFT 23
-#define PCI_STAT_CMD_R_SHIFT 22
-#define PCI_STAT_CMD_66M_SHIFT 21
-#define PCI_STAT_CMD_C_SHIFT 20
-#define PCI_STAT_CMD_F_SHIFT 9
-#define PCI_STAT_CMD_S_SHIFT 8
-#define PCI_STAT_CMD_ST_SHIFT 7
-#define PCI_STAT_CMD_PER_SHIFT 6
-#define PCI_STAT_CMD_V_SHIFT 5
-#define PCI_STAT_CMD_MW_SHIFT 4
-#define PCI_STAT_CMD_SP_SHIFT 3
-#define PCI_STAT_CMD_B_SHIFT 2
-#define PCI_STAT_CMD_M_SHIFT 1
-#define PCI_STAT_CMD_IO_SHIFT 0
-
-#define PCI_STAT_CMD_PE (1<<PCI_STAT_CMD_PE_SHIFT)
-#define PCI_STAT_CMD_SE (1<<PCI_STAT_CMD_SE_SHIFT)
-#define PCI_STAT_CMD_MA (1<<PCI_STAT_CMD_MA_SHIFT)
-#define PCI_STAT_CMD_TR (1<<PCI_STAT_CMD_TR_SHIFT)
-#define PCI_STAT_CMD_TS (1<<PCI_STAT_CMD_TS_SHIFT)
-#define PCI_STAT_CMD_DP (1<<PCI_STAT_CMD_DP_SHIFT)
-#define PCI_STAT_CMD_FC (1<<PCI_STAT_CMD_FC_SHIFT)
-#define PCI_STAT_CMD_R (1<<PCI_STAT_CMD_R_SHIFT)
-#define PCI_STAT_CMD_66M (1<<PCI_STAT_CMD_66M_SHIFT)
-#define PCI_STAT_CMD_C (1<<PCI_STAT_CMD_C_SHIFT)
-#define PCI_STAT_CMD_F (1<<PCI_STAT_CMD_F_SHIFT)
-#define PCI_STAT_CMD_S (1<<PCI_STAT_CMD_S_SHIFT)
-#define PCI_STAT_CMD_ST (1<<PCI_STAT_CMD_ST_SHIFT)
-#define PCI_STAT_CMD_PER (1<<PCI_STAT_CMD_PER_SHIFT)
-#define PCI_STAT_CMD_V (1<<PCI_STAT_CMD_V_SHIFT)
-#define PCI_STAT_CMD_MW (1<<PCI_STAT_CMD_MW_SHIFT)
-#define PCI_STAT_CMD_SP (1<<PCI_STAT_CMD_SP_SHIFT)
-#define PCI_STAT_CMD_B (1<<PCI_STAT_CMD_B_SHIFT)
-#define PCI_STAT_CMD_M (1<<PCI_STAT_CMD_M_SHIFT)
-#define PCI_STAT_CMD_IO (1<<PCI_STAT_CMD_IO_SHIFT)
-
-/* PCI Configuration 1 Register (PCICR1) - PCI Dword 3 */
-#define PCI_CFG1_HT_SHIFT 16
-#define PCI_CFG1_HT_MASK 0xff
-#define PCI_CFG1_LT_SHIFT 8
-#define PCI_CFG1_LT_MASK 0xff
-#define PCI_CFG1_CLS_SHIFT 0
-#define PCI_CFG1_CLS_MASK 0xf
-
-/* function prototypes */
-void loadtask(int basetask, int tasks);
-u32 dramSetup(void);
-
-#if defined(CONFIG_PSC_CONSOLE)
-int psc_serial_init (void);
-void psc_serial_putc(const char c);
-void psc_serial_puts (const char *s);
-int psc_serial_getc(void);
-int psc_serial_tstc(void);
-void psc_serial_setbrg(void);
-#endif
-
-#if defined (CONFIG_EXTUART_CONSOLE)
-int ext_serial_init (void);
-void ext_serial_putc(const char c);
-void ext_serial_puts (const char *s);
-int ext_serial_getc(void);
-int ext_serial_tstc(void);
-void ext_serial_setbrg(void);
-#endif
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __MPC8220_H__ */
diff --git a/include/mtd/cfi_flash.h b/include/mtd/cfi_flash.h
index 966b5e0..b644b91 100644
--- a/include/mtd/cfi_flash.h
+++ b/include/mtd/cfi_flash.h
@@ -129,12 +129,16 @@ typedef union {
} cfiword_t;
/* CFI standard query structure */
+/* The offsets and sizes of this packed structure members correspond
+ * to the actual layout in CFI Flash chips. Some 16- and 32-bit members
+ * are unaligned and must be accessed with explicit unaligned access macros.
+ */
struct cfi_qry {
u8 qry[3];
- u16 p_id;
- u16 p_adr;
- u16 a_id;
- u16 a_adr;
+ u16 p_id; /* unaligned */
+ u16 p_adr; /* unaligned */
+ u16 a_id; /* unaligned */
+ u16 a_adr; /* unaligned */
u8 vcc_min;
u8 vcc_max;
u8 vpp_min;
@@ -148,10 +152,10 @@ struct cfi_qry {
u8 block_erase_timeout_max;
u8 chip_erase_timeout_max;
u8 dev_size;
- u16 interface_desc;
- u16 max_buf_write_size;
+ u16 interface_desc; /* aligned */
+ u16 max_buf_write_size; /* aligned */
u8 num_erase_regions;
- u32 erase_region_info[NUM_ERASE_REGIONS];
+ u32 erase_region_info[NUM_ERASE_REGIONS]; /* unaligned */
} __attribute__((packed));
struct cfi_pri_hdr {
diff --git a/include/netdev.h b/include/netdev.h
index 516b351..df454b5 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -77,7 +77,6 @@ int mcdmafec_initialize(bd_t *bis);
int mcffec_initialize(bd_t *bis);
int mpc512x_fec_initialize(bd_t *bis);
int mpc5xxx_fec_initialize(bd_t *bis);
-int mpc8220_fec_initialize(bd_t *bis);
int mpc82xx_scc_enet_initialize(bd_t *bis);
int mvgbe_initialize(bd_t *bis);
int natsemi_initialize(bd_t *bis);
diff --git a/include/phy.h b/include/phy.h
index 7b4ce74..75bf3b4 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -52,6 +52,7 @@ typedef enum {
PHY_INTERFACE_MODE_MII,
PHY_INTERFACE_MODE_GMII,
PHY_INTERFACE_MODE_SGMII,
+ PHY_INTERFACE_MODE_QSGMII,
PHY_INTERFACE_MODE_TBI,
PHY_INTERFACE_MODE_RMII,
PHY_INTERFACE_MODE_RGMII,
@@ -67,6 +68,7 @@ static const char *phy_interface_strings[] = {
[PHY_INTERFACE_MODE_MII] = "mii",
[PHY_INTERFACE_MODE_GMII] = "gmii",
[PHY_INTERFACE_MODE_SGMII] = "sgmii",
+ [PHY_INTERFACE_MODE_QSGMII] = "qsgmii",
[PHY_INTERFACE_MODE_TBI] = "tbi",
[PHY_INTERFACE_MODE_RMII] = "rmii",
[PHY_INTERFACE_MODE_RGMII] = "rgmii",
diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl
index 2db4784..c0f8cc8 100644
--- a/include/ppc_asm.tmpl
+++ b/include/ppc_asm.tmpl
@@ -175,7 +175,7 @@
#define IM_IMMR (IM_REGBASE+0x01a8)
#define IM_SCCR (IM_REGBASE+0x0c80)
-#elif defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8220)
+#elif defined(CONFIG_MPC5xxx)
#define HID0_ICE_BITPOS 16
#define HID0_DCE_BITPOS 17
diff --git a/include/usb.h b/include/usb.h
index d79c865..d7b082d 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -76,6 +76,12 @@ struct usb_interface {
unsigned char act_altsetting;
struct usb_endpoint_descriptor ep_desc[USB_MAXENDPOINTS];
+ /*
+ * Super Speed Device will have Super Speed Endpoint
+ * Companion Descriptor (section 9.6.7 of usb 3.0 spec)
+ * Revision 1.0 June 6th 2011
+ */
+ struct usb_ss_ep_comp_descriptor ss_ep_comp_desc[USB_MAXENDPOINTS];
} __attribute__ ((packed));
/* Configuration information.. */
diff --git a/include/usb_defs.h b/include/usb_defs.h
index 9502544..4f3601a 100644
--- a/include/usb_defs.h
+++ b/include/usb_defs.h
@@ -150,6 +150,18 @@
#define USB_REQ_SET_IDLE 0x0A
#define USB_REQ_SET_PROTOCOL 0x0B
+/* Device features */
+#define USB_FEAT_HALT 0x00
+#define USB_FEAT_WAKEUP 0x01
+#define USB_FEAT_TEST 0x02
+
+/* Test modes */
+#define USB_TEST_MODE_J 0x01
+#define USB_TEST_MODE_K 0x02
+#define USB_TEST_MODE_SE0_NAK 0x03
+#define USB_TEST_MODE_PACKET 0x04
+#define USB_TEST_MODE_FORCE_ENABLE 0x05
+
/* "pipe" definitions */
@@ -208,6 +220,18 @@
#define USB_PORT_FEAT_C_SUSPEND 18
#define USB_PORT_FEAT_C_OVER_CURRENT 19
#define USB_PORT_FEAT_C_RESET 20
+#define USB_PORT_FEAT_TEST 21
+
+/*
+ * Changes to Port feature numbers for Super speed,
+ * from USB 3.0 spec Table 10-8
+ */
+#define USB_SS_PORT_FEAT_U1_TIMEOUT 23
+#define USB_SS_PORT_FEAT_U2_TIMEOUT 24
+#define USB_SS_PORT_FEAT_C_LINK_STATE 25
+#define USB_SS_PORT_FEAT_C_CONFIG_ERROR 26
+#define USB_SS_PORT_FEAT_BH_RESET 28
+#define USB_SS_PORT_FEAT_C_BH_RESET 29
/* wPortStatus bits */
#define USB_PORT_STAT_CONNECTION 0x0001
@@ -218,9 +242,19 @@
#define USB_PORT_STAT_POWER 0x0100
#define USB_PORT_STAT_LOW_SPEED 0x0200
#define USB_PORT_STAT_HIGH_SPEED 0x0400 /* support for EHCI */
-#define USB_PORT_STAT_SPEED \
+#define USB_PORT_STAT_SUPER_SPEED 0x0600 /* faking support to XHCI */
+#define USB_PORT_STAT_SPEED_MASK \
(USB_PORT_STAT_LOW_SPEED | USB_PORT_STAT_HIGH_SPEED)
+/*
+ * Changes to wPortStatus bit field in USB 3.0
+ * See USB 3.0 spec Table 10-11
+ */
+#define USB_SS_PORT_STAT_LINK_STATE 0x01e0
+#define USB_SS_PORT_STAT_POWER 0x0200
+#define USB_SS_PORT_STAT_SPEED 0x1c00
+#define USB_SS_PORT_STAT_SPEED_5GBPS 0x0000
+
/* wPortChange bits */
#define USB_PORT_STAT_C_CONNECTION 0x0001
#define USB_PORT_STAT_C_ENABLE 0x0002
@@ -228,13 +262,21 @@
#define USB_PORT_STAT_C_OVERCURRENT 0x0008
#define USB_PORT_STAT_C_RESET 0x0010
+/*
+ * Changes to wPortChange bit fields in USB 3.0
+ * See USB 3.0 spec Table 10-12
+ */
+#define USB_SS_PORT_STAT_C_BH_RESET 0x0020
+#define USB_SS_PORT_STAT_C_LINK_STATE 0x0040
+#define USB_SS_PORT_STAT_C_CONFIG_ERROR 0x0080
+
/* wHubCharacteristics (masks) */
#define HUB_CHAR_LPSM 0x0003
#define HUB_CHAR_COMPOUND 0x0004
#define HUB_CHAR_OCPM 0x0018
/*
- *Hub Status & Hub Change bit masks
+ * Hub Status & Hub Change bit masks
*/
#define HUB_STATUS_LOCAL_POWER 0x0001
#define HUB_STATUS_OVERCURRENT 0x0002
diff --git a/include/watchdog.h b/include/watchdog.h
index 97ec186..d95e4b1 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -108,8 +108,7 @@ int init_func_watchdog_reset(void);
void reset_4xx_watchdog(void);
#endif
-/* Freescale i.MX */
-#if defined(CONFIG_IMX_WATCHDOG) && !defined(__ASSEMBLY__)
+#if defined(CONFIG_HW_WATCHDOG) && !defined(__ASSEMBLY__)
void hw_watchdog_init(void);
#endif
#endif /* _WATCHDOG_H_ */