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authorWolfgang Denk <wd@denx.de>2009-10-27 20:56:31 +0100
committerWolfgang Denk <wd@denx.de>2009-10-27 20:56:31 +0100
commit98cecb610f3fa53aa7d825a634d35ef9cf6c5487 (patch)
treef9a153be5ec31919981e4d53e5ee274cffa3d15b /include
parenta747a7f31059b9069e97c78bba5496409c33aa05 (diff)
parent3fca80375981fe83d4674a0267183b469a1ea7ff (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'include')
-rw-r--r--include/asm-ppc/config.h10
-rw-r--r--include/asm-ppc/fsl_pci.h3
-rw-r--r--include/configs/MPC8569MDS.h39
-rw-r--r--include/configs/XPEDITE5370.h8
4 files changed, 59 insertions, 1 deletions
diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h
index eba7901..af0853b 100644
--- a/include/asm-ppc/config.h
+++ b/include/asm-ppc/config.h
@@ -47,6 +47,16 @@
#define CONFIG_MAX_CPUS 1
#endif
+/*
+ * Provide a default boot page translation virtual address that lines up with
+ * Freescale's default e500 reset page.
+ */
+#if (defined(CONFIG_E500) && defined(CONFIG_MP))
+#ifndef CONFIG_BPTR_VIRT_ADDR
+#define CONFIG_BPTR_VIRT_ADDR 0xfffff000
+#endif
+#endif
+
/* Relocation to SDRAM works on all PPC boards */
#define CONFIG_RELOC_FIXUP_WORKS
diff --git a/include/asm-ppc/fsl_pci.h b/include/asm-ppc/fsl_pci.h
index 2790da7..6b0c89b 100644
--- a/include/asm-ppc/fsl_pci.h
+++ b/include/asm-ppc/fsl_pci.h
@@ -62,6 +62,7 @@ typedef struct pci_inbound_window {
#define PIWAR_LOCAL 0x00f00000
#define PIWAR_READ_SNOOP 0x00050000
#define PIWAR_WRITE_SNOOP 0x00005000
+#define PIWAR_IWS_4K 0x0000000b
u32 res2[3];
} pit_t;
@@ -171,7 +172,7 @@ struct fsl_pci_info {
};
int fsl_pci_init_port(struct fsl_pci_info *pci_info,
- struct pci_controller *hose, int busno);
+ struct pci_controller *hose, int busno, int pcie_ep);
#define SET_STD_PCI_INFO(x, num) \
{ \
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 32e747e..17ea3bb 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -70,6 +70,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_ENABLE_36BIT_PHYS 1
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+#define CONFIG_HWCONFIG
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
@@ -180,6 +181,29 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
+/* Chip select 3 - NAND */
+#define CONFIG_SYS_NAND_BASE 0xFC000000
+#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE 1
+#define CONFIG_CMD_NAND 1
+#define CONFIG_NAND_FSL_ELBC 1
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
+ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+ | BR_PS_8 /* Port Size = 8 bit */ \
+ | BR_MS_FCM /* MSEL = FCM */ \
+ | BR_V) /* valid */
+#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
+ | OR_FCM_CSCT \
+ | OR_FCM_CST \
+ | OR_FCM_CHT \
+ | OR_FCM_SCY_1 \
+ | OR_FCM_TRLX \
+ | OR_FCM_EHTR)
+#define CONFIG_SYS_BR3_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR3_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
/*
* SDRAM on the LocalBus
@@ -206,6 +230,7 @@ extern unsigned long get_clock_freq(void);
/* Serial Port */
#define CONFIG_CONS_INDEX 1
+#define CONFIG_SERIAL_MULTI 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
@@ -258,8 +283,10 @@ extern unsigned long get_clock_freq(void);
#define PLPPAR1_I2C_BIT_MASK 0x0000000F
#define PLPPAR1_I2C2_VAL 0x00000000
+#define PLPPAR1_ESDHC_VAL 0x0000000A
#define PLPDIR1_I2C_BIT_MASK 0x0000000F
#define PLPDIR1_I2C2_VAL 0x0000000F
+#define PLPDIR1_ESDHC_VAL 0x00000006
/*
* General PCI
@@ -450,6 +477,18 @@ extern unsigned long get_clock_freq(void);
#undef CONFIG_WATCHDOG /* watchdog disabled */
+#define CONFIG_MMC 1
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
/*
* Miscellaneous configurable options
*/
diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h
index 26b798b..7782df3 100644
--- a/include/configs/XPEDITE5370.h
+++ b/include/configs/XPEDITE5370.h
@@ -49,6 +49,13 @@
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
+ * Multicore config
+ */
+#define CONFIG_MP
+#define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
+#define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */
+
+/*
* DDR config
*/
#define CONFIG_FSL_DDR2
@@ -109,6 +116,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
* 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
* 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
* 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
+ * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
* 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
* 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
* 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable