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authorTom Rini <trini@ti.com>2014-07-18 11:51:32 -0400
committerTom Rini <trini@ti.com>2014-08-25 08:52:34 -0400
commit865813ed83792e7fbfde23118c906099b64fe556 (patch)
treef3fa46cdb6d17d670779e872659fc2b0a4618b60 /include
parent6d9e610ca24a926c11a0125f4e1f5d7728707cfb (diff)
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TI:armv7: Change CONFIG_SPL_STACK to not be CONFIG_SYS_INIT_SP_ADDR
There are times where we may need more than a few kilobytes of stack space. We also will not be using CONFIG_SPL_STACK location prior to DDR being initialized (CONFIG_SYS_INIT_SP_ADDR is still used there) so pick a good location within DDR for this to be. Tested on OMAP4/AM335x/OMAP5/DRA7xx. Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'include')
-rw-r--r--include/configs/ti_armv7_common.h19
1 files changed, 11 insertions, 8 deletions
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index 26ac251..85171db 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -202,15 +202,18 @@
#define CONFIG_SPL_OS_BOOT
/*
- * Place the image at the start of the ROM defined image space.
- * We limit our size to the ROM-defined downloaded image area, and use the
- * rest of the space for stack. We load U-Boot itself into memory at
- * 0x80800000 for legacy reasons (to not conflict with older SPLs). We
- * have our BSS be placed 1MiB after this, to allow for the default
- * Linux kernel address of 0x80008000 to work, in the Falcon Mode case.
- * We have the SPL malloc pool at the end of the BSS area.
+ * Place the image at the start of the ROM defined image space (per
+ * CONFIG_SPL_TEXT_BASE and we limit our size to the ROM-defined
+ * downloaded image area. We initalize DRAM as soon as we can so that
+ * we can place stack, malloc and BSS there. We load U-Boot itself into
+ * memory at 0x80800000 for legacy reasons (to not conflict with older
+ * SPLs). We have our BSS be placed 2MiB after this, to allow for the
+ * default Linux kernel address of 0x80008000 to work with most sized
+ * kernels, in the Falcon Mode case. We have the SPL malloc pool at the
+ * end of the BSS area. We place our stack at 32MiB after the start of
+ * DRAM to allow room for all of the above.
*/
-#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SPL_STACK (CONFIG_SYS_SDRAM_BASE + (32 << 20))
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0x80800000
#endif