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authorJon Loeliger <jdl@freescale.com>2008-07-10 12:05:32 -0500
committerJon Loeliger <jdl@freescale.com>2008-07-10 12:05:32 -0500
commit859f24350e6e4313626f85161dd03f025a4dac59 (patch)
treea025f68619045556e662326c8e1cbc147f9b633e /include
parent3473ab737282b08ad61841fcbb14c4d264a93a8e (diff)
parente0320b1ebec13755911a53b0af12cbf3e5e49a65 (diff)
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Merge commit 'wd/master'
Diffstat (limited to 'include')
-rw-r--r--include/asm-arm/arch-pxa/mmc.h17
-rw-r--r--include/asm-arm/mach-types.h13
-rw-r--r--include/asm-arm/u-boot-arm.h2
-rw-r--r--include/asm-avr32/arch-at32ap700x/gpio.h8
-rw-r--r--include/asm-avr32/arch-at32ap700x/mmc.h19
-rw-r--r--include/asm-ppc/bitops.h52
-rw-r--r--include/asm-ppc/ppc4xx-sdram.h4
-rw-r--r--include/asm-ppc/processor.h9
-rw-r--r--include/asm-sparc/io.h1
-rw-r--r--include/asm-sparc/types.h3
-rw-r--r--include/common.h22
-rw-r--r--include/configs/MPC8260ADS.h7
-rw-r--r--include/configs/MPC8349EMDS.h1
-rw-r--r--include/configs/MVBLM7.h7
-rw-r--r--include/configs/MigoR.h4
-rw-r--r--include/configs/atngw100.h7
-rw-r--r--include/configs/atstk1002.h1
-rw-r--r--include/configs/atstk1003.h1
-rw-r--r--include/configs/atstk1004.h1
-rw-r--r--include/configs/atstk1006.h1
-rw-r--r--include/configs/davinci_sffsdr.h150
-rw-r--r--include/configs/katmai.h7
-rw-r--r--include/configs/korat.h11
-rw-r--r--include/configs/ml300.h1
-rw-r--r--include/configs/ms7722se.h4
-rw-r--r--include/configs/r2dplus.h42
-rw-r--r--include/configs/r7780mp.h41
-rw-r--r--include/configs/sacsng.h12
-rw-r--r--include/configs/sh7763rdp.h10
-rw-r--r--include/environment.h7
-rw-r--r--include/exports.h2
-rw-r--r--include/linux/mtd/mtd.h4
-rw-r--r--include/lmb.h1
-rw-r--r--include/lxt971a.h100
-rw-r--r--include/mmc.h24
-rw-r--r--include/nand.h5
-rw-r--r--include/ns7520_eth.h1
-rw-r--r--include/ns9750_eth.h1
-rw-r--r--include/pci_ids.h1
-rw-r--r--include/ppc440.h2
-rw-r--r--include/sha256.h16
-rw-r--r--include/spi.h9
42 files changed, 396 insertions, 235 deletions
diff --git a/include/asm-arm/arch-pxa/mmc.h b/include/asm-arm/arch-pxa/mmc.h
index 9440d80..85e144b 100644
--- a/include/asm-arm/arch-pxa/mmc.h
+++ b/include/asm-arm/arch-pxa/mmc.h
@@ -110,23 +110,6 @@
#define MMC_DEFAULT_RCA 1
#define MMC_BLOCK_SIZE 512
-#define MMC_CMD_RESET 0
-#define MMC_CMD_SEND_OP_COND 1
-#define MMC_CMD_ALL_SEND_CID 2
-#define MMC_CMD_SET_RCA 3
-#define MMC_CMD_SELECT_CARD 7
-#define MMC_CMD_SEND_CSD 9
-#define MMC_CMD_SEND_CID 10
-#define MMC_CMD_SEND_STATUS 13
-#define MMC_CMD_SET_BLOCKLEN 16
-#define MMC_CMD_READ_BLOCK 17
-#define MMC_CMD_RD_BLK_MULTI 18
-#define MMC_CMD_WRITE_BLOCK 24
-#define MMC_CMD_APP_CMD 55
-
-#define SD_CMD_APP_SET_BUS_WIDTH 6
-#define SD_CMD_APP_OP_COND 41
-
#define MMC_MAX_BLOCK_SIZE 512
#define MMC_R1_IDLE_STATE 0x01
diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h
index aaf2ea2..b347857 100644
--- a/include/asm-arm/mach-types.h
+++ b/include/asm-arm/mach-types.h
@@ -1595,6 +1595,7 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_P300 1602
#define MACH_TYPE_XDACOMET 1603
#define MACH_TYPE_DEXFLEX2 1604
+#define MACH_TYPE_SFFSDR 1657
#ifdef CONFIG_ARCH_EBSA110
# ifdef machine_arch_type
@@ -16500,6 +16501,18 @@ extern unsigned int __machine_arch_type;
# define machine_is_schmoogie() (0)
#endif
+#ifdef CONFIG_MACH_SFFSDR
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SFFSDR
+# endif
+# define machine_is_sffsdr() (machine_arch_type == MACH_TYPE_SFFSDR)
+#else
+# define machine_is_sffsdr() (0)
+#endif
+
#ifdef CONFIG_MACH_AZTOOL
# ifdef machine_arch_type
# undef machine_arch_type
diff --git a/include/asm-arm/u-boot-arm.h b/include/asm-arm/u-boot-arm.h
index 41e7a8f..4ee5a32 100644
--- a/include/asm-arm/u-boot-arm.h
+++ b/include/asm-arm/u-boot-arm.h
@@ -52,7 +52,7 @@ void setup_revision_tag (struct tag **params);
/* To be fixed! */
/* ------------------------------------------------------------ */
/* common/cmd_nvedit.c */
-void setenv (char *, char *);
+int setenv (char *, char *);
/* cpu/.../interrupt.c */
void reset_timer_masked (void);
diff --git a/include/asm-avr32/arch-at32ap700x/gpio.h b/include/asm-avr32/arch-at32ap700x/gpio.h
index ef20cea..8c922c7 100644
--- a/include/asm-avr32/arch-at32ap700x/gpio.h
+++ b/include/asm-avr32/arch-at32ap700x/gpio.h
@@ -180,6 +180,11 @@
#define GPIO_PIN_PE25 (GPIO_PIOE_BASE + 25)
#define GPIO_PIN_PE26 (GPIO_PIOE_BASE + 26)
+#define GPIOF_PULLUP 0x00000001 /* (not-OUT) Enable pull-up */
+#define GPIOF_OUTPUT 0x00000002 /* (OUT) Enable output driver */
+#define GPIOF_DEGLITCH 0x00000004 /* (IN) Filter glitches */
+#define GPIOF_MULTIDRV 0x00000008 /* Enable multidriver option */
+
static inline void *gpio_pin_to_addr(unsigned int pin)
{
switch (pin >> 5) {
@@ -200,6 +205,9 @@ static inline void *gpio_pin_to_addr(unsigned int pin)
void gpio_select_periph_A(unsigned int pin, int use_pullup);
void gpio_select_periph_B(unsigned int pin, int use_pullup);
+void gpio_select_pio(unsigned int pin, unsigned long gpiof_flags);
+void gpio_set_value(unsigned int pin, int value);
+int gpio_get_value(unsigned int pin);
void gpio_enable_ebi(void);
diff --git a/include/asm-avr32/arch-at32ap700x/mmc.h b/include/asm-avr32/arch-at32ap700x/mmc.h
index 6a33fef..9caba91 100644
--- a/include/asm-avr32/arch-at32ap700x/mmc.h
+++ b/include/asm-avr32/arch-at32ap700x/mmc.h
@@ -71,25 +71,6 @@ struct mmc_csd
u8 one:1;
};
-/* MMC Command numbers */
-#define MMC_CMD_GO_IDLE_STATE 0
-#define MMC_CMD_SEND_OP_COND 1
-#define MMC_CMD_ALL_SEND_CID 2
-#define MMC_CMD_SET_RELATIVE_ADDR 3
-#define MMC_CMD_SD_SEND_RELATIVE_ADDR 3
-#define MMC_CMD_SET_DSR 4
-#define MMC_CMD_SELECT_CARD 7
-#define MMC_CMD_SEND_CSD 9
-#define MMC_CMD_SEND_CID 10
-#define MMC_CMD_SEND_STATUS 13
-#define MMC_CMD_SET_BLOCKLEN 16
-#define MMC_CMD_READ_SINGLE_BLOCK 17
-#define MMC_CMD_READ_MULTIPLE_BLOCK 18
-#define MMC_CMD_WRITE_BLOCK 24
-#define MMC_CMD_APP_CMD 55
-
-#define MMC_ACMD_SD_SEND_OP_COND 41
-
#define R1_ILLEGAL_COMMAND (1 << 22)
#define R1_APP_CMD (1 << 5)
diff --git a/include/asm-ppc/bitops.h b/include/asm-ppc/bitops.h
index 4e9c608..daa66cf 100644
--- a/include/asm-ppc/bitops.h
+++ b/include/asm-ppc/bitops.h
@@ -152,6 +152,7 @@ extern __inline__ int test_bit(int nr, __const__ volatile void *addr)
}
/* Return the bit position of the most significant 1 bit in a word */
+/* - the result is undefined when x == 0 */
extern __inline__ int __ilog2(unsigned int x)
{
int lz;
@@ -167,6 +168,57 @@ extern __inline__ int ffz(unsigned int x)
return __ilog2(x & -x);
}
+/*
+ * fls: find last (most-significant) bit set.
+ * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
+ *
+ * On powerpc, __ilog2(0) returns -1, but this is not safe in general
+ */
+static __inline__ int fls(unsigned int x)
+{
+ return __ilog2(x) + 1;
+}
+
+/**
+ * fls64 - find last set bit in a 64-bit word
+ * @x: the word to search
+ *
+ * This is defined in a similar way as the libc and compiler builtin
+ * ffsll, but returns the position of the most significant set bit.
+ *
+ * fls64(value) returns 0 if value is 0 or the position of the last
+ * set bit if value is nonzero. The last (most significant) bit is
+ * at position 64.
+ */
+#if BITS_PER_LONG == 32
+static inline int fls64(__u64 x)
+{
+ __u32 h = x >> 32;
+ if (h)
+ return fls(h) + 32;
+ return fls(x);
+}
+#elif BITS_PER_LONG == 64
+static inline int fls64(__u64 x)
+{
+ if (x == 0)
+ return 0;
+ return __ilog2(x) + 1;
+}
+#else
+#error BITS_PER_LONG not 32 or 64
+#endif
+
+static inline int __ilog2_u64(u64 n)
+{
+ return fls64(n) - 1;
+}
+
+static inline int ffs64(u64 x)
+{
+ return __ilog2_u64(x & -x) + 1ull;
+}
+
#ifdef __KERNEL__
/*
diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h
index 83931f1..e151f0c 100644
--- a/include/asm-ppc/ppc4xx-sdram.h
+++ b/include/asm-ppc/ppc4xx-sdram.h
@@ -284,8 +284,8 @@
#if defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */
-#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((u32)(n))&0xFFE00000)>>2)
-#define SDRAM_RXBAS_SDBA_DECODE(n) ((((u32)(n))&0xFFE00000)<<2)
+#define SDRAM_RXBAS_SDBA_ENCODE(n) ((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000))
+#define SDRAM_RXBAS_SDBA_DECODE(n) ((((phys_size_t)(n)) & 0xFFE00000) << 2)
#endif /* CONFIG_440SPE */
#if defined(CONFIG_440SP)
#define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 139e686..10fd478 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -968,10 +968,17 @@ struct cpu_type {
u32 soc_ver;
};
-struct cpu_type *identify_cpu(uint ver);
+struct cpu_type *identify_cpu(u32 ver);
+#if defined(CONFIG_MPC85xx)
#define CPU_TYPE_ENTRY(n, v) \
{ .name = #n, .soc_ver = SVR_##v, }
+#else
+#if defined(CONFIG_MPC83XX)
+#define CPU_TYPE_ENTRY(x) {#x, SPR_##x}
+#endif
+#endif
+
#ifndef CONFIG_MACH_SPECIFIC
extern int _machine;
diff --git a/include/asm-sparc/io.h b/include/asm-sparc/io.h
index 2a27d06..ede0b1a 100644
--- a/include/asm-sparc/io.h
+++ b/include/asm-sparc/io.h
@@ -70,7 +70,6 @@
* that can be used to access the memory range with the caching
* properties specified by "flags".
*/
-typedef unsigned long phys_addr_t;
#define MAP_NOCACHE (0)
#define MAP_WRCOMBINE (0)
diff --git a/include/asm-sparc/types.h b/include/asm-sparc/types.h
index 69f93d6..2cf974a 100644
--- a/include/asm-sparc/types.h
+++ b/include/asm-sparc/types.h
@@ -65,6 +65,9 @@ typedef unsigned long long u64;
/* DMA addresses are 32-bits wide */
typedef u32 dma_addr_t;
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
#endif /* __KERNEL__ */
#endif /* __ASSEMBLY__ */
diff --git a/include/common.h b/include/common.h
index fd5adb3..2fcb1fd 100644
--- a/include/common.h
+++ b/include/common.h
@@ -243,9 +243,9 @@ char *getenv (char *);
int getenv_r (char *name, char *buf, unsigned len);
int saveenv (void);
#ifdef CONFIG_PPC /* ARM version to be fixed! */
-void inline setenv (char *, char *);
+int inline setenv (char *, char *);
#else
-void setenv (char *, char *);
+int setenv (char *, char *);
#ifdef CONFIG_HAS_UID
void forceenv (char *, char *);
#endif
@@ -607,8 +607,10 @@ ulong simple_strtoul(const char *cp,char **endp,unsigned int base);
unsigned long long simple_strtoull(const char *cp,char **endp,unsigned int base);
#endif
long simple_strtol(const char *cp,char **endp,unsigned int base);
-void panic(const char *fmt, ...);
-int sprintf(char * buf, const char *fmt, ...);
+void panic(const char *fmt, ...)
+ __attribute__ ((format (__printf__, 1, 2)));
+int sprintf(char * buf, const char *fmt, ...)
+ __attribute__ ((format (__printf__, 2, 3)));
int vsprintf(char *buf, const char *fmt, va_list args);
/* lib_generic/crc32.c */
@@ -630,7 +632,8 @@ int disable_ctrlc (int); /* 1 to disable, 0 to enable Control-C detect */
*/
/* serial stuff */
-void serial_printf (const char *fmt, ...);
+void serial_printf (const char *fmt, ...)
+ __attribute__ ((format (__printf__, 1, 2)));
/* stdin */
int getc(void);
@@ -639,7 +642,8 @@ int tstc(void);
/* stdout */
void putc(const char c);
void puts(const char *s);
-void printf(const char *fmt, ...);
+void printf(const char *fmt, ...)
+ __attribute__ ((format (__printf__, 1, 2)));
void vprintf(const char *fmt, va_list args);
/* stderr */
@@ -656,7 +660,8 @@ void vprintf(const char *fmt, va_list args);
#define stderr 2
#define MAX_FILES 3
-void fprintf(int file, const char *fmt, ...);
+void fprintf(int file, const char *fmt, ...)
+ __attribute__ ((format (__printf__, 2, 3)));
void fputs(int file, const char *s);
void fputc(int file, const char c);
int ftstc(int file);
@@ -682,6 +687,9 @@ void __attribute__((weak)) show_boot_progress (int val);
#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
+#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1)
+#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
+
/* Multicore arch functions */
#ifdef CONFIG_MP
int cpu_status(int nr);
diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h
index 23508f9..59d0bdb 100644
--- a/include/configs/MPC8260ADS.h
+++ b/include/configs/MPC8260ADS.h
@@ -197,6 +197,13 @@
#define CONFIG_BAUDRATE 115200
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#if defined(CONFIG_OF_LIBFDT)
+#define OF_CPU "cpu@0"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#endif
+
/*
* BOOTP options
*/
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 37e3ca4..8705838 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -355,7 +355,6 @@
/* SPI */
#define CONFIG_MPC8XXX_SPI
-#define CONFIG_HARD_SPI /* SPI with hardware support */
#undef CONFIG_SOFT_SPI /* SPI bit-banged */
/* GPIOs. Used as SPI chip selects */
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
index 349ca14..b412655 100644
--- a/include/configs/MVBLM7.h
+++ b/include/configs/MVBLM7.h
@@ -27,7 +27,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define MV_VERSION "v1.0.1"
+#include <version.h>
/*
* High Level Configuration Options
@@ -262,7 +262,7 @@
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
-#define CONFIG_LOADS_ECHO
+#define CONFIG_LOADS_ECHO
#define CFG_LOADS_BAUD_CHANGE
/*
@@ -336,6 +336,7 @@
#define CFG_HID0_FINAL CFG_HID0_INIT
#define CFG_HID2 HID2_HBE
+#define CONFIG_HIGH_BATS 1
/* DDR */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
@@ -446,7 +447,7 @@
"mv_dtb_addr=" MV_DTB_ADDR "\0" \
"mv_dtb_addr_ram=" MV_DTB_ADDR_RAM "\0" \
"dtb_name=" MV_DTB_NAME "\0" \
- "mv_version=" MV_VERSION "\0" \
+ "mv_version=" U_BOOT_VERSION "\0" \
"dhcp_client_id=" MV_CI "\0" \
"dhcp_vendor-class-identifier=" MV_VCI "\0" \
"netretry=no\0" \
diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h
index 99e1179..fa0e5db 100644
--- a/include/configs/MigoR.h
+++ b/include/configs/MigoR.h
@@ -45,10 +45,6 @@
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 192.168.10.100
-#define CONFIG_SERVERIP 192.168.10.77
-#define CONFIG_GATEWAYIP 192.168.10.77
#define CONFIG_VERSION_VARIABLE
#undef CONFIG_SHOW_BOOT_PROGRESS
diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h
index 3fc9975..84d235e 100644
--- a/include/configs/atngw100.h
+++ b/include/configs/atngw100.h
@@ -114,6 +114,8 @@
#define CONFIG_CMD_FAT
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MMC
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
#undef CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_FPGA
@@ -126,6 +128,11 @@
#define CFG_NR_PIOS 5
#define CFG_HSDRAMC 1
#define CONFIG_MMC 1
+#define CONFIG_ATMEL_MCI 1
+#define CONFIG_ATMEL_SPI 1
+
+#define CONFIG_SPI_FLASH 1
+#define CONFIG_SPI_FLASH_ATMEL 1
#define CFG_DCACHE_LINESZ 32
#define CFG_ICACHE_LINESZ 32
diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h
index ba18eb6..90910bb 100644
--- a/include/configs/atstk1002.h
+++ b/include/configs/atstk1002.h
@@ -153,6 +153,7 @@
#define CFG_NR_PIOS 5
#define CFG_HSDRAMC 1
#define CONFIG_MMC 1
+#define CONFIG_ATMEL_MCI 1
#define CFG_DCACHE_LINESZ 32
#define CFG_ICACHE_LINESZ 32
diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h
index a528ddf..03472a8 100644
--- a/include/configs/atstk1003.h
+++ b/include/configs/atstk1003.h
@@ -136,6 +136,7 @@
#define CONFIG_PIO2 1
#define CFG_HSDRAMC 1
#define CONFIG_MMC 1
+#define CONFIG_ATMEL_MCI 1
#define CFG_DCACHE_LINESZ 32
#define CFG_ICACHE_LINESZ 32
diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h
index fc9585e..07add82 100644
--- a/include/configs/atstk1004.h
+++ b/include/configs/atstk1004.h
@@ -136,6 +136,7 @@
#define CONFIG_PIO2 1
#define CFG_HSDRAMC 1
#define CONFIG_MMC 1
+#define CONFIG_ATMEL_MCI 1
#define CFG_DCACHE_LINESZ 32
#define CFG_ICACHE_LINESZ 32
diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h
index 9fd49a5..f9af675 100644
--- a/include/configs/atstk1006.h
+++ b/include/configs/atstk1006.h
@@ -153,6 +153,7 @@
#define CFG_NR_PIOS 5
#define CFG_HSDRAMC 1
#define CONFIG_MMC 1
+#define CONFIG_ATMEL_MCI 1
#define CFG_DCACHE_LINESZ 32
#define CFG_ICACHE_LINESZ 32
diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h
new file mode 100644
index 0000000..0e49e6c
--- /dev/null
+++ b/include/configs/davinci_sffsdr.h
@@ -0,0 +1,150 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+ * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/* Board */
+#define SFFSDR
+#define CFG_NAND_LARGEPAGE
+#define CFG_USE_NAND
+#define CFG_USE_DSPLINK /* This is to prevent U-Boot from
+ * powering ON the DSP. */
+/* SoC Configuration */
+#define CONFIG_ARM926EJS /* arm926ejs CPU core */
+#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */
+#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
+#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
+#define CFG_HZ 1000
+/* EEPROM definitions for Atmel 24LC64 EEPROM chip */
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_I2C_EEPROM_ADDR 0x50
+#define CFG_EEPROM_PAGE_WRITE_BITS 5
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
+/* Memory Info */
+#define CFG_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */
+#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */
+#define CFG_MEMTEST_START 0x80000000 /* memtest start address */
+#define CFG_MEMTEST_END 0x81000000 /* 16MB RAM test */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE (256*1024) /* regular stack */
+#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
+#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
+/* Serial Driver info */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */
+#define CFG_NS16550_COM1 0x01c20000 /* Base address of UART0 */
+#define CFG_NS16550_CLK 27000000 /* Input clock to NS16550 */
+#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+/* I2C Configuration */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CFG_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
+#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
+/* Network & Ethernet Configuration */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+/* Flash & Environment */
+#undef CFG_ENV_IS_IN_FLASH
+#define CFG_NO_FLASH
+#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
+#define CFG_ENV_SECT_SIZE 2048 /* Env sector Size */
+#define CFG_ENV_SIZE SZ_128K
+#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
+#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
+#define CFG_NAND_BASE 0x02000000
+#define CFG_NAND_HW_ECC
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_MAX_CHIPS 1
+#define CFG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
+/* I2C switch definitions for PCA9543 chip */
+#define CFG_I2C_PCA9543_ADDR 0x70
+#define CFG_I2C_PCA9543_ADDR_LEN 0 /* Single register. */
+#define CFG_I2C_PCA9543_ENABLE_CH0 0x01 /* Enable channel 0. */
+/* U-Boot general configuration */
+#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds. */
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_PBSIZE \
+ (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print buffer size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR 0x80700000 /* Default Linux kernel
+ * load address. */
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far,
+ * may be later */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_CMDLINE_EDITING
+#define CFG_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+/* Linux Information */
+#define LINUX_BOOT_PARAM_ADDR 0x80000100
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS \
+ "mem=56M " \
+ "console=ttyS0,115200n8 " \
+ "root=/dev/nfs rw noinitrd ip=dhcp " \
+ "nfsroot=${serverip}:/nfsroot/sffsdr " \
+ "eth0=${ethaddr}"
+#define CONFIG_BOOTCOMMAND \
+ "nand read 87A00000 100000 300000;" \
+ "bootelf 87A00000"
+/* U-Boot commands */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+/* KGDB support (if any) */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
+#endif
+#endif /* __CONFIG_H */
diff --git a/include/configs/katmai.h b/include/configs/katmai.h
index d3789bd..f07e470 100644
--- a/include/configs/katmai.h
+++ b/include/configs/katmai.h
@@ -41,6 +41,13 @@
#define CFG_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
/*
+ * Enable this board for more than 2GB of SDRAM
+ */
+#define CONFIG_PHYS_64BIT
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
+
+/*
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME katmai
diff --git a/include/configs/korat.h b/include/configs/korat.h
index 7655666..4ca4ed0 100644
--- a/include/configs/korat.h
+++ b/include/configs/korat.h
@@ -129,7 +129,7 @@
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_FLASH1_TOP - CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
@@ -145,7 +145,6 @@
#define CONFIG_DDR_ECC /* Use ECC when available */
#define SPD_EEPROM_ADDRESS {0x50}
#define CONFIG_PROG_SDRAM_TLB
-#define CFG_DRAM_TEST
#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
/* 440EPx errata CHIP 11 */
@@ -185,7 +184,7 @@
#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
/* Note: kernel_addr and ramdisk_addr assume that FLASH1 is 64 MiB. */
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#define CONFIG_EXTRA_ENV_SETTINGS \
CFG_BOOTFILE \
CFG_ROOTPATH \
"netdev=eth0\0" \
@@ -216,7 +215,7 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#define CONFIG_IBM_EMAC4_V4 1
+#define CONFIG_IBM_EMAC4_V4 1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */
#define CONFIG_PHY_DYNAMIC_ANEG 1
@@ -548,4 +547,8 @@
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
#endif /* __CONFIG_H */
diff --git a/include/configs/ml300.h b/include/configs/ml300.h
index 1945918..319923a 100644
--- a/include/configs/ml300.h
+++ b/include/configs/ml300.h
@@ -54,6 +54,7 @@
#define CONFIG_405 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
+#define CONFIG_XILINX_405 1
#define CONFIG_XILINX_ML300 1 /* ...on a Xilinx ML300 board */
#define CONFIG_SYSTEMACE 1
diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h
index 8d92a13..7298e55 100644
--- a/include/configs/ms7722se.h
+++ b/include/configs/ms7722se.h
@@ -40,10 +40,6 @@
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 192.168.0.22
-#define CONFIG_SERVERIP 192.168.0.1
-#define CONFIG_GATEWAYIP 192.168.0.1
#define CONFIG_VERSION_VARIABLE
#undef CONFIG_SHOW_BOOT_PROGRESS
diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h
index c20baca..e269336 100644
--- a/include/configs/r2dplus.h
+++ b/include/configs/r2dplus.h
@@ -35,12 +35,6 @@
#define CONFIG_BOOTARGS "console=ttySC0,115200"
#define CONFIG_ENV_OVERWRITE 1
-/* Network setting */
-#define CONFIG_NETMASK 255.0.0.0
-#define CONFIG_IPADDR 10.0.192.51
-#define CONFIG_SERVERIP 10.0.0.1
-#define CONFIG_GATEWAYIP 10.0.0.1
-
/* SDRAM */
#define CFG_SDRAM_BASE (0x8C000000)
#define CFG_SDRAM_SIZE (0x04000000)
@@ -60,45 +54,27 @@
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 32 * 1024 * 1024)
/* Address of u-boot image in Flash */
#define CFG_MONITOR_BASE (CFG_FLASH_BASE)
-#define CFG_MONITOR_LEN (128 * 1024)
+#define CFG_MONITOR_LEN (256 * 1024)
/* Size of DRAM reserved for malloc() use */
-#define CFG_MALLOC_LEN (256 * 1024)
+#define CFG_MALLOC_LEN (1024 * 1024)
/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_SIZE (256)
#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
/*
- * NOR Flash
+ * NOR Flash ( Spantion S29GL256P )
*/
#define CFG_FLASH_CFI
#define CFG_FLASH_CFI_DRIVER
-
-#if defined(CONFIG_R2DPLUS_OLD)
-#define CFG_FLASH_BASE (0xA0000000)
-#define CFG_MAX_FLASH_BANKS (1) /* Max number of
- * Flash memory banks
- */
-#define CFG_MAX_FLASH_SECT 142
-#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
-
-#else /* CONFIG_R2DPLUS_OLD */
-
#define CFG_FLASH_BASE (0xA0000000)
-#define CFG_FLASH_CFI_WIDTH 0x04 /* 32bit */
-#define CFG_MAX_FLASH_BANKS (2)
-#define CFG_MAX_FLASH_SECT 270
-#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\
- CFG_FLASH_BASE + 0x100000,\
- CFG_FLASH_BASE + 0x400000,\
- CFG_FLASH_BASE + 0x700000, }
-#endif /* CONFIG_R2DPLUS_OLD */
+#define CFG_MAX_FLASH_BANKS (1)
+#define CFG_MAX_FLASH_SECT 256
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE 0x20000
-#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
-#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-#define CFG_FLASH_ERASE_TOUT 120000
-#define CFG_FLASH_WRITE_TOUT 500
+#define CFG_ENV_SECT_SIZE 0x40000
+#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
/*
* SuperH Clock setting
diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h
index 4e89580..4c82c5a 100644
--- a/include/configs/r7780mp.h
+++ b/include/configs/r7780mp.h
@@ -1,7 +1,7 @@
/*
* Configuation settings for the Renesas R7780MP board
*
- * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
*
* See file CREDITS for list of people who contributed to this
@@ -31,7 +31,8 @@
#define CONFIG_SH4A 1
#define CONFIG_CPU_SH7780 1
#define CONFIG_R7780MP 1
-#define __LITTLE_ENDIAN 1
+#define CFG_R7780MP_OLD_FLASH 1
+#define __LITTLE_ENDIAN__ 1
/*
* Command line configuration.
@@ -59,12 +60,6 @@
/* check for keypress on bootdelay==0 */
/*#define CONFIG_ZERO_BOOTDELAY_CHECK*/
-/* Network setting */
-#define CONFIG_NETMASK 255.0.0.0
-#define CONFIG_IPADDR 10.0.192.82
-#define CONFIG_SERVERIP 10.0.0.1
-#define CONFIG_GATEWAYIP 10.0.0.1
-
#define CFG_SDRAM_BASE (0x08000000)
#define CFG_SDRAM_SIZE (128 * 1024 * 1024)
@@ -80,22 +75,30 @@
#define CFG_MEMTEST_START (CFG_SDRAM_BASE)
#define CFG_MEMTEST_END (TEXT_BASE - 0x100000)
-/* NOR Flash (S29PL127J60TFI130) */
+/* Flash board support */
#define CFG_FLASH_BASE (0xA0000000)
-#define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT
-#define CFG_MAX_FLASH_BANKS (2)
-#define CFG_MAX_FLASH_SECT 270
-#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\
+#ifdef CFG_R7780MP_OLD_FLASH
+/* NOR Flash (S29PL127J60TFI130) */
+# define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT
+# define CFG_MAX_FLASH_BANKS (2)
+# define CFG_MAX_FLASH_SECT 270
+# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\
CFG_FLASH_BASE + 0x100000,\
CFG_FLASH_BASE + 0x400000,\
CFG_FLASH_BASE + 0x700000, }
+#else /* CFG_R7780MP_OLD_FLASH */
+/* NOR Flash (Spantion S29GL256P) */
+# define CFG_MAX_FLASH_BANKS (1)
+# define CFG_MAX_FLASH_SECT 256
+# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#endif /* CFG_R7780MP_OLD_FLASH */
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024)
/* Address of u-boot image in Flash */
#define CFG_MONITOR_BASE (CFG_FLASH_BASE)
-#define CFG_MONITOR_LEN (112 * 1024)
+#define CFG_MONITOR_LEN (256 * 1024)
/* Size of DRAM reserved for malloc() use */
-#define CFG_MALLOC_LEN (256 * 1024)
+#define CFG_MALLOC_LEN (1204 * 1024)
/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_SIZE (256)
@@ -110,7 +113,7 @@
#define CFG_FLASH_EMPTY_INFO
#define CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE (16 * 1024)
+#define CFG_ENV_SECT_SIZE (256 * 1024)
#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define CFG_FLASH_ERASE_TOUT 120000
@@ -141,8 +144,10 @@
#endif /* CONFIG_CMD_PCI */
#if defined(CONFIG_CMD_NET)
-/* #define CONFIG_NET_MULTI
- #define CONFIG_RTL8169 */
+/*
+#define CONFIG_NET_MULTI
+#define CONFIG_RTL8169
+*/
/* AX88696L Support(NE2000 base chip) */
#define CONFIG_DRIVER_NE2000
#define CONFIG_DRIVER_AX88796L
diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h
index 4974fb4..2a398e8 100644
--- a/include/configs/sacsng.h
+++ b/include/configs/sacsng.h
@@ -272,10 +272,14 @@
#undef SPI_INIT /* no port initialization needed */
#define SPI_READ ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0)
-#define SPI_SDA(bit) if(bit) immr->im_ioport.iop_pdatd |= I2C_MOSI; \
- else immr->im_ioport.iop_pdatd &= ~I2C_MOSI
-#define SPI_SCL(bit) if(bit) immr->im_ioport.iop_pdatd |= I2C_SCLK; \
- else immr->im_ioport.iop_pdatd &= ~I2C_SCLK
+#define SPI_SDA(bit) do { \
+ if(bit) immr->im_ioport.iop_pdatd |= I2C_MOSI; \
+ else immr->im_ioport.iop_pdatd &= ~I2C_MOSI; \
+ } while (0)
+#define SPI_SCL(bit) do { \
+ if(bit) immr->im_ioport.iop_pdatd |= I2C_SCLK; \
+ else immr->im_ioport.iop_pdatd &= ~I2C_SCLK; \
+ } while (0)
#define SPI_DELAY /* No delay is needed */
#endif /* CONFIG_SOFT_SPI */
diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h
index d537071..7713eaa 100644
--- a/include/configs/sh7763rdp.h
+++ b/include/configs/sh7763rdp.h
@@ -38,11 +38,7 @@
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
#define CONFIG_CMD_ENV
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_JFFS2
#define CONFIG_BOOTDELAY -1
#define CONFIG_BOOTARGS "console=ttySC2,115200 root=1f01"
@@ -66,12 +62,6 @@
#define CFG_BAUDRATE_TABLE { 115200 } /* List of legal baudrate
settings for this board */
-/* Ethernet */
-#define CONFIG_SH_ETHER 1
-#define CONFIG_SH_ETHER_USE_PORT (1)
-#define CONFIG_SH_ETHER_PHY_ADDR (0x01)
-#define CFG_RX_ETH_BUFFER (8)
-
/* SDRAM */
#define CFG_SDRAM_BASE (0x8C000000)
#define CFG_SDRAM_SIZE (64 * 1024 * 1024)
diff --git a/include/environment.h b/include/environment.h
index bf9f669..481ea73 100644
--- a/include/environment.h
+++ b/include/environment.h
@@ -107,8 +107,8 @@ typedef struct environment_s {
unsigned char data[ENV_SIZE]; /* Environment data */
} env_t;
-/* Pointer to function that returns a character from the environment */
-extern unsigned char (*env_get_char)(int);
+/* Function that returns a character from the environment */
+unsigned char env_get_char (int);
/* Function that returns a pointer to a value from the environment */
unsigned char *env_get_addr(int);
@@ -117,4 +117,7 @@ unsigned char env_get_char_memory (int index);
/* Function that updates CRC of the enironment */
void env_crc_update (void);
+/* [re]set to the default environment */
+void set_default_env(void);
+
#endif /* _ENVIRONMENT_H_ */
diff --git a/include/exports.h b/include/exports.h
index d6512cb..6377875 100644
--- a/include/exports.h
+++ b/include/exports.h
@@ -22,7 +22,7 @@ void vprintf(const char *, va_list);
void do_reset (void);
unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base);
char *getenv (char *name);
-void setenv (char *varname, char *varvalue);
+int setenv (char *varname, char *varvalue);
long simple_strtol(const char *cp,char **endp,unsigned int base);
int strcmp(const char * cs,const char * ct);
#ifdef CONFIG_HAS_UID
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 71cb2d5..05ba375 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -201,13 +201,13 @@ static inline void mtd_erase_callback(struct erase_info *instr)
#define MTD_DEBUG_LEVEL3 (3) /* Noisy */
#ifdef CONFIG_MTD_DEBUG
-#define DEBUG(n, args...) \
+#define MTDDEBUG(n, args...) \
do { \
if (n <= CONFIG_MTD_DEBUG_VERBOSE) \
printk(KERN_INFO args); \
} while(0)
#else /* CONFIG_MTD_DEBUG */
-#define DEBUG(n, args...) do { } while(0)
+#define MTDDEBUG(n, args...) do { } while(0)
#endif /* CONFIG_MTD_DEBUG */
diff --git a/include/lmb.h b/include/lmb.h
index 03d7667..14e8727 100644
--- a/include/lmb.h
+++ b/include/lmb.h
@@ -43,6 +43,7 @@ extern phys_addr_t lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align
extern phys_addr_t __lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align,
phys_addr_t max_addr);
extern int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr);
+extern long lmb_free(struct lmb *lmb, phys_addr_t base, phys_size_t size);
extern void lmb_dump_all(struct lmb *lmb);
diff --git a/include/lxt971a.h b/include/lxt971a.h
index f76c336..72145e0 100644
--- a/include/lxt971a.h
+++ b/include/lxt971a.h
@@ -30,15 +30,6 @@
#define __LXT971A_H__
/* PHY definitions (LXT971A) [2] */
-#define PHY_COMMON_CTRL (0x00)
-#define PHY_COMMON_STAT (0x01)
-#define PHY_COMMON_ID1 (0x02)
-#define PHY_COMMON_ID2 (0x03)
-#define PHY_COMMON_AUTO_ADV (0x04)
-#define PHY_COMMON_AUTO_LNKB (0x05)
-#define PHY_COMMON_AUTO_EXP (0x06)
-#define PHY_COMMON_AUTO_NEXT (0x07)
-#define PHY_COMMON_AUTO_LNKN (0x08)
#define PHY_LXT971_PORT_CFG (0x10)
#define PHY_LXT971_STAT2 (0x11)
#define PHY_LXT971_INT_ENABLE (0x12)
@@ -47,97 +38,6 @@
#define PHY_LXT971_DIG_CFG (0x1A)
#define PHY_LXT971_TX_CTRL (0x1E)
-/* CTRL PHY Control Register Bit Fields */
-#define PHY_COMMON_CTRL_RESET (0x8000)
-#define PHY_COMMON_CTRL_LOOPBACK (0x4000)
-#define PHY_COMMON_CTRL_SPD_MA (0x2040)
-#define PHY_COMMON_CTRL_SPD_10 (0x0000)
-#define PHY_COMMON_CTRL_SPD_100 (0x2000)
-#define PHY_COMMON_CTRL_SPD_1000 (0x0040)
-#define PHY_COMMON_CTRL_SPD_RES (0x2040)
-#define PHY_COMMON_CTRL_AUTO_NEG (0x1000)
-#define PHY_COMMON_CTRL_POWER_DN (0x0800)
-#define PHY_COMMON_CTRL_ISOLATE (0x0400)
-#define PHY_COMMON_CTRL_RES_AUTO (0x0200)
-#define PHY_COMMON_CTRL_DUPLEX (0x0100)
-#define PHY_COMMON_CTRL_COL_TEST (0x0080)
-#define PHY_COMMON_CTRL_RES1 (0x003F)
-
-/* STAT Status Register Bit Fields */
-#define PHY_COMMON_STAT_100BT4 (0x8000)
-#define PHY_COMMON_STAT_100BXFD (0x4000)
-#define PHY_COMMON_STAT_100BXHD (0x2000)
-#define PHY_COMMON_STAT_10BTFD (0x1000)
-#define PHY_COMMON_STAT_10BTHD (0x0800)
-#define PHY_COMMON_STAT_100BT2FD (0x0400)
-#define PHY_COMMON_STAT_100BT2HD (0x0200)
-#define PHY_COMMON_STAT_EXT_STAT (0x0100)
-#define PHY_COMMON_STAT_RES1 (0x0080)
-#define PHY_COMMON_STAT_MF_PSUP (0x0040)
-#define PHY_COMMON_STAT_AN_COMP (0x0020)
-#define PHY_COMMON_STAT_RMT_FLT (0x0010)
-#define PHY_COMMON_STAT_AN_CAP (0x0008)
-#define PHY_COMMON_STAT_LNK_STAT (0x0004)
-#define PHY_COMMON_STAT_JAB_DTCT (0x0002)
-#define PHY_COMMON_STAT_EXT_CAP (0x0001)
-
-/* AUTO_ADV Auto-neg Advert Register Bit Fields */
-#define PHY_COMMON_AUTO_ADV_NP (0x8000)
-#define PHY_COMMON_AUTO_ADV_RES1 (0x4000)
-#define PHY_COMMON_AUTO_ADV_RMT_FLT (0x2000)
-#define PHY_COMMON_AUTO_ADV_RES2 (0x1000)
-#define PHY_COMMON_AUTO_ADV_AS_PAUSE (0x0800)
-#define PHY_COMMON_AUTO_ADV_PAUSE (0x0400)
-#define PHY_COMMON_AUTO_ADV_100BT4 (0x0200)
-#define PHY_COMMON_AUTO_ADV_100BTXFD (0x0100)
-#define PHY_COMMON_AUTO_ADV_100BTX (0x0080)
-#define PHY_COMMON_AUTO_ADV_10BTFD (0x0040)
-#define PHY_COMMON_AUTO_ADV_10BT (0x0020)
-#define PHY_COMMON_AUTO_ADV_SEL_FLD_MA (0x001F)
-#define PHY_COMMON_AUTO_ADV_802_9 (0x0002)
-#define PHY_COMMON_AUTO_ADV_802_3 (0x0001)
-
-/* AUTO_LNKB Auto-neg Link Ability Register Bit Fields */
-#define PHY_COMMON_AUTO_LNKB_NP (0x8000)
-#define PHY_COMMON_AUTO_LNKB_ACK (0x4000)
-#define PHY_COMMON_AUTO_LNKB_RMT_FLT (0x2000)
-#define PHY_COMMON_AUTO_LNKB_RES2 (0x1000)
-#define PHY_COMMON_AUTO_LNKB_AS_PAUSE (0x0800)
-#define PHY_COMMON_AUTO_LNKB_PAUSE (0x0400)
-#define PHY_COMMON_AUTO_LNKB_100BT4 (0x0200)
-#define PHY_COMMON_AUTO_LNKB_100BTXFD (0x0100)
-#define PHY_COMMON_AUTO_LNKB_100BTX (0x0080)
-#define PHY_COMMON_AUTO_LNKB_10BTFD (0x0040)
-#define PHY_COMMON_AUTO_LNKB_10BT (0x0020)
-#define PHY_COMMON_AUTO_LNKB_SEL_FLD_MA (0x001F)
-#define PHY_COMMON_AUTO_LNKB_802_9 (0x0002)
-#define PHY_COMMON_AUTO_LNKB_802_3 (0x0001)
-
-/* AUTO_EXP Auto-neg Expansion Register Bit Fields */
-#define PHY_COMMON_AUTO_EXP_RES1 (0xFFC0)
-#define PHY_COMMON_AUTO_EXP_BASE_PAGE (0x0020)
-#define PHY_COMMON_AUTO_EXP_PAR_DT_FLT (0x0010)
-#define PHY_COMMON_AUTO_EXP_LNK_NP_CAP (0x0008)
-#define PHY_COMMON_AUTO_EXP_NP_CAP (0x0004)
-#define PHY_COMMON_AUTO_EXP_PAGE_REC (0x0002)
-#define PHY_COMMON_AUTO_EXP_LNK_AN_CAP (0x0001)
-
-/* AUTO_NEXT Aut-neg Next Page Tx Register Bit Fields */
-#define PHY_COMMON_AUTO_NEXT_NP (0x8000)
-#define PHY_COMMON_AUTO_NEXT_RES1 (0x4000)
-#define PHY_COMMON_AUTO_NEXT_MSG_PAGE (0x2000)
-#define PHY_COMMON_AUTO_NEXT_ACK_2 (0x1000)
-#define PHY_COMMON_AUTO_NEXT_TOGGLE (0x0800)
-#define PHY_COMMON_AUTO_NEXT_MSG (0x07FF)
-
-/* AUTO_LNKN Auto-neg Link Partner Rx Reg Bit Fields */
-#define PHY_COMMON_AUTO_LNKN_NP (0x8000)
-#define PHY_COMMON_AUTO_LNKN_ACK (0x4000)
-#define PHY_COMMON_AUTO_LNKN_MSG_PAGE (0x2000)
-#define PHY_COMMON_AUTO_LNKN_ACK_2 (0x1000)
-#define PHY_COMMON_AUTO_LNKN_TOGGLE (0x0800)
-#define PHY_COMMON_AUTO_LNKN_MSG (0x07FF)
-
/* PORT_CFG Port Configuration Register Bit Fields */
#define PHY_LXT971_PORT_CFG_RES1 (0x8000)
#define PHY_LXT971_PORT_CFG_FORCE_LNK (0x4000)
diff --git a/include/mmc.h b/include/mmc.h
index a271695..19c76fe 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -25,6 +25,30 @@
#define _MMC_H_
#include <asm/arch/mmc.h>
+/* MMC command numbers */
+#define MMC_CMD_GO_IDLE_STATE 0
+#define MMC_CMD_SEND_OP_COND 1
+#define MMC_CMD_ALL_SEND_CID 2
+#define MMC_CMD_SET_RELATIVE_ADDR 3
+#define MMC_CMD_SET_DSR 4
+#define MMC_CMD_SELECT_CARD 7
+#define MMC_CMD_SEND_CSD 9
+#define MMC_CMD_SEND_CID 10
+#define MMC_CMD_SEND_STATUS 13
+#define MMC_CMD_SET_BLOCKLEN 16
+#define MMC_CMD_READ_SINGLE_BLOCK 17
+#define MMC_CMD_READ_MULTIPLE_BLOCK 18
+#define MMC_CMD_WRITE_BLOCK 24
+#define MMC_CMD_APP_CMD 55
+
+/* SD Card command numbers */
+#define SD_CMD_SEND_RELATIVE_ADDR 3
+#define SD_CMD_SWITCH 6
+#define SD_CMD_SEND_IF_COND 8
+
+#define SD_CMD_APP_SET_BUS_WIDTH 6
+#define SD_CMD_APP_SEND_OP_COND 41
+
int mmc_init(int verbose);
int mmc_read(ulong src, uchar *dst, int size);
int mmc_write(uchar *src, ulong dst, int size);
diff --git a/include/nand.h b/include/nand.h
index 247d346..e1285cd 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -24,6 +24,9 @@
#ifndef _NAND_H_
#define _NAND_H_
+extern void nand_init(void);
+
+#ifndef CFG_NAND_LEGACY
#include <linux/mtd/compat.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
@@ -32,7 +35,6 @@ typedef struct mtd_info nand_info_t;
extern int nand_curr_device;
extern nand_info_t nand_info[];
-extern void nand_init(void);
static inline int nand_read(nand_info_t *info, off_t ofs, size_t *len, u_char *buf)
{
@@ -122,4 +124,5 @@ int nand_get_lock_status(nand_info_t *meminfo, ulong offset);
void board_nand_select_device(struct nand_chip *nand, int chip);
#endif
+#endif /* !CFG_NAND_LEGACY */
#endif
diff --git a/include/ns7520_eth.h b/include/ns7520_eth.h
index 123e6f4..b509697 100644
--- a/include/ns7520_eth.h
+++ b/include/ns7520_eth.h
@@ -24,6 +24,7 @@
#ifdef CONFIG_DRIVER_NS7520_ETHERNET
+#include <miiphy.h>
#include "lxt971a.h"
/* The port addresses */
diff --git a/include/ns9750_eth.h b/include/ns9750_eth.h
index a6e5889..80c721b 100644
--- a/include/ns9750_eth.h
+++ b/include/ns9750_eth.h
@@ -31,6 +31,7 @@
#ifdef CONFIG_DRIVER_NS9750_ETHERNET
+#include <miiphy.h>
#include "lxt971a.h"
#define NS9750_ETH_MODULE_BASE (0xA0600000)
diff --git a/include/pci_ids.h b/include/pci_ids.h
index d061017..165456b 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -1827,6 +1827,7 @@
#define PCI_DEVICE_ID_INTEL_82545EM_FIBER 0x1011
#define PCI_DEVICE_ID_INTEL_82546EB_FIBER 0x1012
#define PCI_DEVICE_ID_INTEL_82540EM_LOM 0x1015
+#define PCI_DEVICE_ID_INTEL_82545GM_COPPER 0x1026
#define PCI_DEVICE_ID_INTEL_82559 0x1030
#define PCI_DEVICE_ID_INTEL_82562ET 0x1031
diff --git a/include/ppc440.h b/include/ppc440.h
index 62f1680..c581f1b 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -2471,6 +2471,8 @@
#define AHB_TOP 0xA4
#define AHB_BOT 0xA5
+#define SDR0_AHB_CFG 0x370
+#define SDR0_USB2HOST_CFG 0x371
#endif /* CONFIG_460EX || CONFIG_460GT */
#define SDR0_SDCS_SDD (0x80000000 >> 31)
diff --git a/include/sha256.h b/include/sha256.h
new file mode 100644
index 0000000..e38ea89
--- /dev/null
+++ b/include/sha256.h
@@ -0,0 +1,16 @@
+#ifndef _SHA256_H
+#define _SHA256_H
+
+#define SHA256_SUM_LEN 32
+
+typedef struct {
+ uint32_t total[2];
+ uint32_t state[8];
+ uint8_t buffer[64];
+} sha256_context;
+
+void sha256_starts(sha256_context * ctx);
+void sha256_update(sha256_context * ctx, uint8_t * input, uint32_t length);
+void sha256_finish(sha256_context * ctx, uint8_t digest[SHA256_SUM_LEN]);
+
+#endif /* _SHA256_H */
diff --git a/include/spi.h b/include/spi.h
index 7744c2e..320e50e 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -24,6 +24,15 @@
#ifndef _SPI_H_
#define _SPI_H_
+/* Controller-specific definitions: */
+
+/* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */
+#ifdef CONFIG_MPC8XXX_SPI
+# ifndef CONFIG_HARD_SPI
+# define CONFIG_HARD_SPI
+# endif
+#endif
+
/* SPI mode flags */
#define SPI_CPHA 0x01 /* clock phase */
#define SPI_CPOL 0x02 /* clock polarity */