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authorZang Roy-r61911 <tie-fei.zang@freescale.com>2006-12-14 14:14:55 +0800
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2007-04-23 19:58:27 -0500
commit41fb7e0f1ec9b91bdae2565bab5f2e3ee15039c7 (patch)
tree3df6ad3139523edfe2943901d1f761a15ebbd3b3 /include
parent14da5f7675bbb427c469e3f45006e027b6e21db9 (diff)
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u-boot: Enable PCI function and add PEX & rapidio memory map on MPC8548CDS board
Enable PCI function and add PEX & rapidio memory map on MPC8548CDS board. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Diffstat (limited to 'include')
-rw-r--r--include/asm-ppc/mmu.h1
-rw-r--r--include/configs/MPC8548CDS.h28
2 files changed, 21 insertions, 8 deletions
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index b226825..67c2c57 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -413,6 +413,7 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
#define LAWAR_TRGT_IF_PCI1 0x00000000
#define LAWAR_TRGT_IF_PCIX 0x00000000
#define LAWAR_TRGT_IF_PCI2 0x00100000
+#define LAWAR_TRGT_IF_PEX 0x00200000
#define LAWAR_TRGT_IF_LBC 0x00400000
#define LAWAR_TRGT_IF_CCSR 0x00800000
#define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 7c4849f..bfd316c 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -36,7 +36,7 @@
#define CONFIG_MPC8548 1 /* MPC8548 specific */
#define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */
-#undef CONFIG_PCI
+#define CONFIG_PCI
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
@@ -344,18 +344,30 @@ extern unsigned long get_clock_freq(void);
*/
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
#define CFG_PCI1_IO_BASE 0x00000000
#define CFG_PCI1_IO_PHYS 0xe2000000
-#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
+#define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */
-#define CFG_PCI2_MEM_BASE 0xa0000000
+#define CFG_PCI2_MEM_BASE 0x90000000
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
-#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
-#define CFG_PCI2_IO_BASE 0x00000000
-#define CFG_PCI2_IO_PHYS 0xe2100000
-#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
+#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCI2_IO_BASE 0xe2800000
+#define CFG_PCI2_IO_PHYS 0xe2800000
+#define CFG_PCI2_IO_SIZE 0x00800000 /* 8M */
+
+#define CFG_PEX_MEM_BASE 0xa0000000
+#define CFG_PEX_MEM_PHYS CFG_PEX_MEM_BASE
+#define CFG_PEX_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PEX_IO_BASE 0xe3000000
+#define CFG_PEX_IO_PHYS CFG_PEX_IO_BASE
+#define CFG_PEX_IO_SIZE 0x1000000 /* 16M */
+/*
+ * RapidIO MMU
+ */
+#define CFG_RIO_MEM_BASE 0xC0000000
+#define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */
#if defined(CONFIG_PCI)