Merge branch 'uboot'

author: Minkyu Kang <mk7.kang@samsung.com> 2014-10-07 19:14:03 +0900
committer: Minkyu Kang <mk7.kang@samsung.com> 2014-10-07 19:14:03 +0900
commit: 3cc83f9d08a80fddf4c1e8e766eff8273f30814c (patch)
tree: 831246a1b77d26d0296a84c90684e0fee0368737 /include
parent: 64f41212d880f3d00c6994d973aadeec5bda1b65 (diff)
parent: 6dd0e7c00bfa5ce861a72b8e4a3ef9e787306125 (diff)
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118 files changed, 1033 insertions, 291 deletions
diff --git a/include/common.h b/include/common.h
index 97c04df..d5020c8 100644
--- a/include/common.h
+++ b/include/common.h
@@ -181,9 +181,6 @@ typedef void (interrupt_handler_t)(void *);
 		typeof(Y) __y = (Y);		\
 		(__x > __y) ? __x : __y; })
 
-#define MIN(x, y)  min(x, y)
-#define MAX(x, y)  max(x, y)
-
 #define min3(X, Y, Z)				\
 	({ typeof(X) __x = (X);			\
 		typeof(Y) __y = (Y);		\
@@ -198,9 +195,6 @@ typedef void (interrupt_handler_t)(void *);
 		__x > __y ? (__x > __z ? __x : __z) :	\
 		(__y > __z ? __y : __z); })
 
-#define MIN3(x, y, z)  min3(x, y, z)
-#define MAX3(x, y, z)  max3(x, y, z)
-
 /*
  * Return the absolute value of a number.
  *
diff --git a/include/compiler.h b/include/compiler.h
index 9afc11b..1451916 100644
--- a/include/compiler.h
+++ b/include/compiler.h
@@ -129,9 +129,6 @@ typedef unsigned long int uintptr_t;
 
 #endif /* USE_HOSTCC */
 
-/* compiler options */
-#define uninitialized_var(x)		x = x
-
 #define likely(x)	__builtin_expect(!!(x), 1)
 #define unlikely(x)	__builtin_expect(!!(x), 0)
 
diff --git a/include/config_cmd_defaults.h b/include/config_cmd_defaults.h
deleted file mode 100644
index a55b268..0000000
--- a/include/config_cmd_defaults.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * config_cmd_defaults.h - sane defaults for everyone
- *
- * Copyright (c) 2010-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CONFIG_CMD_DEFAULTS_H_
-#define _CONFIG_CMD_DEFAULTS_H_
-
-#define CONFIG_CMD_BOOTM 1
-#define CONFIG_CMD_CRC32 1
-#define CONFIG_CMD_EXPORTENV 1
-#define CONFIG_CMD_GO 1
-#define CONFIG_CMD_IMPORTENV 1
-
-#endif
diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
index 90d9901..be616e8 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -53,10 +53,23 @@
 #endif
 
 #ifdef CONFIG_CMD_SCSI
-#define BOOTENV_SHARED_SCSI	BOOTENV_SHARED_BLKDEV(scsi)
+#define BOOTENV_RUN_SCSI_INIT "run scsi_init; "
+#define BOOTENV_SET_SCSI_NEED_INIT "setenv scsi_need_init; "
+#define BOOTENV_SHARED_SCSI \
+	"scsi_init=" \
+		"if ${scsi_need_init}; then " \
+			"setenv scsi_need_init false; " \
+			"scsi scan; " \
+		"fi\0" \
+	\
+	"scsi_boot=" \
+		BOOTENV_RUN_SCSI_INIT \
+		BOOTENV_SHARED_BLKDEV_BODY(scsi)
 #define BOOTENV_DEV_SCSI	BOOTENV_DEV_BLKDEV
 #define BOOTENV_DEV_NAME_SCSI	BOOTENV_DEV_NAME_BLKDEV
 #else
+#define BOOTENV_RUN_SCSI_INIT
+#define BOOTENV_SET_SCSI_NEED_INIT
 #define BOOTENV_SHARED_SCSI
 #define BOOTENV_DEV_SCSI \
 	BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_CMD_SCSI
@@ -189,7 +202,7 @@
 	\
 	BOOT_TARGET_DEVICES(BOOTENV_DEV)                                  \
 	\
-	"bootcmd=" BOOTENV_SET_USB_NEED_INIT                              \
+	"bootcmd=" BOOTENV_SET_USB_NEED_INIT BOOTENV_SET_SCSI_NEED_INIT   \
 		"for target in ${boot_targets}; do "                      \
 			"run bootcmd_${target}; "                         \
 		"done\0"
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 953d06b..9063c57 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -227,6 +227,7 @@ unsigned long get_board_ddr_clk(void);
 #endif
 
 /* EEPROM */
+#define CONFIG_ID_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_EEPROM_BUS_NUM	0
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
@@ -819,9 +820,16 @@ unsigned long get_board_ddr_clk(void);
 
 #define __USB_PHY_TYPE	ulpi
 
+#ifdef CONFIG_PPC_B4860
+#define HWCONFIG	"hwconfig=fsl_ddr:ctlr_intlv=null,"	\
+			"bank_intlv=cs0_cs1;"	\
+			"en_cpc:cpc2;"
+#else
+#define	HWCONFIG	"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
+#endif
+
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
-	"hwconfig=fsl_ddr:ctlr_intlv=null,"		\
-	"bank_intlv=cs0_cs1;"					\
+	HWCONFIG						\
 	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 	"netdev=eth0\0"						\
 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 0ee0ff2..5e2c100 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -19,6 +19,9 @@
 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg
 #endif
 #ifdef CONFIG_T1042RDB_PI
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_rcw.cfg
+#endif
+#ifdef CONFIG_T1042RDB
 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg
 #endif
 
@@ -477,7 +480,7 @@
 
 /* I2C bus multiplexer */
 #define I2C_MUX_PCA_ADDR                0x70
-#ifdef CONFIG_T1040RDB
+#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
 #define I2C_MUX_CH_DEFAULT      0x8
 #endif
 
@@ -503,6 +506,7 @@
 #define CONFIG_FSL_ESPI
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_BAR
 #define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED         10000000
 #define CONFIG_SF_DEFAULT_MODE          0
@@ -633,7 +637,7 @@
 #define CONFIG_SYS_DPAA_FMAN
 #define CONFIG_SYS_DPAA_PME
 
-#ifdef CONFIG_T1040RDB
+#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
 #define CONFIG_QE
 #define CONFIG_U_QE
 #endif
@@ -662,7 +666,7 @@
 #define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
 #endif
 
-#ifdef CONFIG_T1040RDB
+#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
 #if defined(CONFIG_SPIFLASH)
 #define CONFIG_SYS_QE_FW_ADDR		0x130000
 #elif defined(CONFIG_SDCARD)
@@ -686,7 +690,7 @@
 #endif
 
 #ifdef CONFIG_FMAN_ENET
-#ifdef CONFIG_T1040RDB
+#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
 #define CONFIG_SYS_SGMII1_PHY_ADDR		0x03
 #endif
 #define CONFIG_SYS_RGMII1_PHY_ADDR		0x01
@@ -788,13 +792,14 @@
 #define CONFIG_BAUDRATE	115200
 
 #define __USB_PHY_TYPE	utmi
+#define RAMDISKFILE	"t104xrdb/ramdisk.uboot"
 
 #ifdef CONFIG_T1040RDB
 #define FDTFILE		"t1040rdb/t1040rdb.dtb"
-#define RAMDISKFILE	"t1040rdb/ramdisk.uboot"
-#elif CONFIG_T1042RDB_PI
-#define FDTFILE		"t1040rdb_pi/t1040rdb_pi.dtb"
-#define RAMDISKFILE	"t1040rdb_pi/ramdisk.uboot"
+#elif defined(CONFIG_T1042RDB_PI)
+#define FDTFILE		"t1042rdb_pi/t1042rdb_pi.dtb"
+#elif defined(CONFIG_T1042RDB)
+#define FDTFILE		"t1042rdb/t1042rdb.dtb"
 #endif
 
 #ifdef CONFIG_FSL_DIU_FB
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index df1a6fc..e2f7ead 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -23,9 +23,6 @@
 # define CONFIG_TIMESTAMP
 # define CONFIG_LZO
 # ifdef CONFIG_ENABLE_VBOOT
-#  define CONFIG_OF_CONTROL
-#  define CONFIG_OF_SEPARATE
-#  define CONFIG_DEFAULT_DEVICE_TREE am335x-boneblack
 #  define CONFIG_FIT_SIGNATURE
 #  define CONFIG_RSA
 # endif
@@ -115,6 +112,9 @@
 		"nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
 		"ip=dhcp\0" \
 	"bootenv=uEnv.txt\0" \
+	"loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
+		"source ${loadaddr}\0" \
 	"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
 	"importbootenv=echo Importing environment from mmc ...; " \
 		"env import -t -r $loadaddr $filesize\0" \
@@ -142,17 +142,21 @@
 	"mmcboot=mmc dev ${mmcdev}; " \
 		"if mmc rescan; then " \
 			"echo SD/MMC found on device ${mmcdev};" \
-			"if run loadbootenv; then " \
-				"echo Loaded environment from ${bootenv};" \
-				"run importbootenv;" \
-			"fi;" \
-			"if test -n $uenvcmd; then " \
-				"echo Running uenvcmd ...;" \
-				"run uenvcmd;" \
-			"fi;" \
-			"if run loadimage; then " \
-				"run mmcloados;" \
-			"fi;" \
+			"if run loadbootscript; then " \
+				"run bootscript;" \
+			"else " \
+				"if run loadbootenv; then " \
+					"echo Loaded environment from ${bootenv};" \
+					"run importbootenv;" \
+				"fi;" \
+				"if test -n $uenvcmd; then " \
+					"echo Running uenvcmd ...;" \
+					"run uenvcmd;" \
+				"fi;" \
+				"if run loadimage; then " \
+					"run mmcloados;" \
+				"fi;" \
+			"fi ;" \
 		"fi;\0" \
 	"spiboot=echo Booting from spi ...; " \
 		"run spiargs; " \
@@ -398,8 +402,6 @@
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS		0
-#define CONFIG_SPL_SPI_CS		0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
 
 #define CONFIG_ENV_IS_IN_SPI_FLASH
diff --git a/include/configs/arndale.h b/include/configs/arndale.h
index 75f9933..43077cf 100644
--- a/include/configs/arndale.h
+++ b/include/configs/arndale.h
@@ -22,8 +22,6 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
 
 /* Allow tracing to be enabled */
 #define CONFIG_TRACE
@@ -226,7 +224,6 @@
 #define CONFIG_POWER_I2C
 #define CONFIG_POWER_MAX77686
 
-#define CONFIG_DEFAULT_DEVICE_TREE	exynos5250-arndale
 
 #define CONFIG_PREBOOT
 
diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h
index 9b0e588..f02fce9 100644
--- a/include/configs/at91sam9n12ek.h
+++ b/include/configs/at91sam9n12ek.h
@@ -31,6 +31,7 @@
 #define CONFIG_DISPLAY_CPUINFO
 
 #define CONFIG_OF_LIBFDT
+#define CONFIG_SYS_GENERIC_BOARD
 
 /* general purpose I/O */
 #define CONFIG_AT91_GPIO
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index 3747098..b8d5dd1 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -34,6 +34,8 @@
 #define CONFIG_CMD_BOOTZ
 #define CONFIG_OF_LIBFDT
 
+#define CONFIG_SYS_GENERIC_BOARD
+
 #define CONFIG_ATMEL_LEGACY
 #define CONFIG_AT91_GPIO		1
 #define CONFIG_AT91_GPIO_PULLUP		1
diff --git a/include/configs/bct-brettl2.h b/include/configs/bct-brettl2.h
index c1eda96..d0828d5 100644
--- a/include/configs/bct-brettl2.h
+++ b/include/configs/bct-brettl2.h
@@ -137,7 +137,6 @@
 #define CONFIG_MTD_DEVICE
 #define CONFIG_MTD_PARTITIONS
 #define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/beaver.h b/include/configs/beaver.h
index d8ed717..164b2dd 100644
--- a/include/configs/beaver.h
+++ b/include/configs/beaver.h
@@ -24,11 +24,6 @@
 /* VDD core PMIC */
 #define CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1
 
-/* Enable fdt support for Beaver. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra30-beaver
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* High-level configuration options */
 #define V_PROMPT		"Tegra30 (Beaver) # "
 #define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Beaver"
diff --git a/include/configs/bf506f-ezkit.h b/include/configs/bf506f-ezkit.h
index 5db1819..0b66cdb 100644
--- a/include/configs/bf506f-ezkit.h
+++ b/include/configs/bf506f-ezkit.h
@@ -85,8 +85,6 @@
  */
 #define CONFIG_ENV_IS_NOWHERE
 #define CONFIG_ENV_SIZE 0x400
-#undef CONFIG_CMD_EXPORTENV
-#undef CONFIG_CMD_IMPORTENV
 
 
 /*
@@ -102,7 +100,6 @@
 #define CONFIG_CMD_MEMORY
 #undef CONFIG_GZIP
 #undef CONFIG_ZLIB
-#undef CONFIG_CMD_BOOTM
 #undef CONFIG_BOOTM_RTEMS
 #undef CONFIG_BOOTM_LINUX
 
diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h
index 9e374c4..20f6ed1 100644
--- a/include/configs/bf518f-ezbrd.h
+++ b/include/configs/bf518f-ezbrd.h
@@ -155,7 +155,6 @@
 #define CONFIG_MISC_INIT_R
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	0
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h
index 972eca9..c33d035 100644
--- a/include/configs/bf526-ezbrd.h
+++ b/include/configs/bf526-ezbrd.h
@@ -153,7 +153,6 @@
 #define CONFIG_MISC_INIT_R
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	1
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /* define to enable run status via led */
 /* #define CONFIG_STATUS_LED */
diff --git a/include/configs/bf527-ad7160-eval.h b/include/configs/bf527-ad7160-eval.h
index c0dfe26..b497f26 100644
--- a/include/configs/bf527-ad7160-eval.h
+++ b/include/configs/bf527-ad7160-eval.h
@@ -136,7 +136,6 @@
  */
 #define CONFIG_MISC_INIT_R
 #define CONFIG_UART_CONSOLE	0
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h
index 92c183e..0bca53f 100644
--- a/include/configs/bf527-ezkit.h
+++ b/include/configs/bf527-ezkit.h
@@ -179,7 +179,6 @@
 #define CONFIG_MISC_INIT_R
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	1
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf527-sdp.h b/include/configs/bf527-sdp.h
index 458868a..9d43b81 100644
--- a/include/configs/bf527-sdp.h
+++ b/include/configs/bf527-sdp.h
@@ -112,7 +112,6 @@
  */
 #define CONFIG_MISC_INIT_R
 #define CONFIG_UART_CONSOLE	0
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h
index b503528..0fda967 100644
--- a/include/configs/bf533-ezkit.h
+++ b/include/configs/bf533-ezkit.h
@@ -110,7 +110,6 @@
 #define CONFIG_MISC_INIT_R
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	0
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
index 3d36d84..ae4d83a 100644
--- a/include/configs/bf533-stamp.h
+++ b/include/configs/bf533-stamp.h
@@ -186,7 +186,6 @@
  */
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	0
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /* FLASH/ETHERNET uses the same async bank */
 #define SHARED_RESOURCES 	1
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index a302f83..29f9316 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -254,7 +254,6 @@
 #define CONFIG_MISC_INIT_R
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	0
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /* Define if want to do post memory test */
 #undef CONFIG_POST
diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h
index 32df5ec..a655282 100644
--- a/include/configs/bf538f-ezkit.h
+++ b/include/configs/bf538f-ezkit.h
@@ -135,7 +135,6 @@
  */
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	0
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h
index 1a245a2..da5f029 100644
--- a/include/configs/bf548-ezkit.h
+++ b/include/configs/bf548-ezkit.h
@@ -181,7 +181,6 @@
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	1
 #define CONFIG_BFIN_SPI_IMG_SIZE 0x50000
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 #define CONFIG_ADI_GPIO2
 
diff --git a/include/configs/bf561-acvilon.h b/include/configs/bf561-acvilon.h
index 3db917e..6871d8c 100644
--- a/include/configs/bf561-acvilon.h
+++ b/include/configs/bf561-acvilon.h
@@ -160,7 +160,6 @@
 #define CONFIG_UART_CONSOLE			0
 #define CONFIG_BAUDRATE				57600
 #define CONFIG_SYS_PROMPT "Acvilon> "
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h
index 0a309d9..fb6f948 100644
--- a/include/configs/bf561-ezkit.h
+++ b/include/configs/bf561-ezkit.h
@@ -102,7 +102,6 @@
  * Misc Settings
  */
 #define CONFIG_UART_CONSOLE	0
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Run core 1 from L1 SRAM start address when init uboot on core 0
diff --git a/include/configs/br4.h b/include/configs/br4.h
index f8d3158..3f24008 100644
--- a/include/configs/br4.h
+++ b/include/configs/br4.h
@@ -135,7 +135,6 @@
 #define CONFIG_BOOTCOMMAND	"run nandboot"
 #define CONFIG_BOOTDELAY	2
 #define CONFIG_LOADADDR		0x2000000
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h
index 3f889f8..e9d5d01 100644
--- a/include/configs/bur_am335x_common.h
+++ b/include/configs/bur_am335x_common.h
@@ -151,7 +151,6 @@
 #undef CONFIG_CMD_NFS
 #undef CONFIG_CMD_SETGETDCR
 #undef CONFIG_CMD_XIMG
-#undef CONFIG_CMD_CRC32
 /* define command we need always */
 #define CONFIG_CMD_ECHO
 #define CONFIG_CMD_SOURCE
diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h
index 59f429c..09129c7 100644
--- a/include/configs/cardhu.h
+++ b/include/configs/cardhu.h
@@ -24,11 +24,6 @@
 /* VDD core PMIC */
 #define CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3
 
-/* Enable fdt support for Cardhu. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra30-cardhu
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* High-level configuration options */
 #define V_PROMPT		"Tegra30 (Cardhu) # "
 #define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Cardhu"
diff --git a/include/configs/cm-bf527.h b/include/configs/cm-bf527.h
index 8d3ae49..f5351ad 100644
--- a/include/configs/cm-bf527.h
+++ b/include/configs/cm-bf527.h
@@ -128,7 +128,6 @@
 #define FLASHBOOT_ENV_SETTINGS \
 	"flashboot=flread 20040000 1000000 300000;" \
 	"bootm 0x1000000\0"
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/cm-bf533.h b/include/configs/cm-bf533.h
index 8bd499a..485f01a 100644
--- a/include/configs/cm-bf533.h
+++ b/include/configs/cm-bf533.h
@@ -97,7 +97,6 @@
 #define CONFIG_UART_CONSOLE	0
 #define CONFIG_BOOTCOMMAND	"run flashboot"
 #define FLASHBOOT_ENV_SETTINGS	"flashboot=bootm 0x20040000\0"
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h
index 47967d7..1729b44 100644
--- a/include/configs/cm-bf537e.h
+++ b/include/configs/cm-bf537e.h
@@ -146,7 +146,6 @@
 	"flashboot=flread 20040000 1000000 3c0000;" \
 	"bootm 0x1000000\0"
 #define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h
index 88c9982..272aa74 100644
--- a/include/configs/cm-bf537u.h
+++ b/include/configs/cm-bf537u.h
@@ -143,7 +143,6 @@
 	"flashboot=flread 20040000 1000000 300000;" \
 	"bootm 0x1000000\0"
 #define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h
index 346e27f..7f27eda 100644
--- a/include/configs/cm-bf548.h
+++ b/include/configs/cm-bf548.h
@@ -117,7 +117,6 @@
 #define CONFIG_UART_CONSOLE	1
 #define CONFIG_BOOTCOMMAND	"run flashboot"
 #define FLASHBOOT_ENV_SETTINGS	"flashboot=bootm 0x20040000\0"
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 #define CONFIG_ADI_GPIO2
 
diff --git a/include/configs/cm-bf561.h b/include/configs/cm-bf561.h
index 5265e5f..96910a7 100644
--- a/include/configs/cm-bf561.h
+++ b/include/configs/cm-bf561.h
@@ -99,7 +99,6 @@
 #define CONFIG_UART_CONSOLE	0
 #define CONFIG_BOOTCOMMAND	"run flashboot"
 #define FLASHBOOT_ENV_SETTINGS	"flashboot=bootm 0x20040000\0"
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
new file mode 100644
index 0000000..10d02b4
--- /dev/null
+++ b/include/configs/cm_fx6.h
@@ -0,0 +1,290 @@
+/*
+ * Config file for Compulab CM-FX6 board
+ *
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Nikita Kiryanov <nikita@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_CM_FX6_H
+#define __CONFIG_CM_FX6_H
+
+#include <asm/arch/imx-regs.h>
+#include <config_distro_defaults.h>
+#include "mx6_common.h"
+
+/* Machine config */
+#define CONFIG_MX6
+#define CONFIG_SYS_LITTLE_ENDIAN
+#define CONFIG_MACH_TYPE		4273
+#define CONFIG_SYS_HZ			1000
+
+/* Display information on boot */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_TIMESTAMP
+
+/* CMD */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_GREPENV
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_XIMG
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMLS
+
+/* MMC */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_USDHC_NUM	3
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
+
+/* RAM */
+#define PHYS_SDRAM_1			MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_2			MMDC1_ARB_BASE_ADDR
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_NR_DRAM_BANKS		2
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		0x10010000
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Serial console */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART4_BASE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
+
+/* Shell */
+#define CONFIG_SYS_PROMPT	"CM-FX6 # "
+#define CONFIG_SYS_CBSIZE	1024
+#define CONFIG_SYS_MAXARGS	16
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* SPI flash */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_BUS		0
+#define CONFIG_SF_DEFAULT_CS		0
+#define CONFIG_SF_DEFAULT_SPEED		25000000
+#define CONFIG_SF_DEFAULT_MODE		(SPI_MODE_0)
+
+/* Environment */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_BUS		CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
+#define CONFIG_ENV_SIZE			(8 * 1024)
+#define CONFIG_ENV_OFFSET		(768 * 1024)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"kernel=uImage-cm-fx6\0" \
+	"autoload=no\0" \
+	"loadaddr=0x10800000\0" \
+	"fdtaddr=0x11000000\0" \
+	"console=ttymxc3,115200\0" \
+	"ethprime=FEC0\0" \
+	"bootscr=boot.scr\0" \
+	"bootm_low=18000000\0" \
+	"video_hdmi=mxcfb0:dev=hdmi,1920x1080M-32@50,if=RGB32\0" \
+	"video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \
+	"fdtfile=cm-fx6.dtb\0" \
+	"doboot=bootm ${loadaddr}\0" \
+	"loadfdt=false\0" \
+	"setboottypez=setenv kernel zImage-cm-fx6;" \
+		"setenv doboot bootz ${loadaddr} - ${fdtaddr};" \
+		"setenv loadfdt true;\0" \
+	"setboottypem=setenv kernel uImage-cm-fx6;" \
+		"setenv doboot bootm ${loadaddr};" \
+		"setenv loadfdt false;\0"\
+	"run_eboot=echo Starting EBOOT ...; "\
+		"mmc dev ${mmcdev} && " \
+		"mmc rescan && mmc read 10042000 a 400 && go 10042000\0" \
+	"mmcdev=2\0" \
+	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
+	"loadmmcbootscript=load mmc ${mmcdev} ${loadaddr} ${bootscr}\0" \
+	"mmcbootscript=echo Running bootscript from mmc ...; "\
+		"source ${loadaddr}\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"root=${mmcroot} " \
+		"${video}\0" \
+	"mmcloadkernel=load mmc ${mmcdev} ${loadaddr} ${kernel}\0" \
+	"mmcloadfdt=load mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"run doboot\0" \
+	"satadev=0\0" \
+	"sataroot=/dev/sda2 rw rootwait\0" \
+	"sataargs=setenv bootargs console=${console} " \
+		"root=${sataroot} " \
+		"${video}\0" \
+	"loadsatabootscript=load sata ${satadev} ${loadaddr} ${bootscr}\0" \
+	"satabootscript=echo Running bootscript from sata ...; " \
+		"source ${loadaddr}\0" \
+	"sataloadkernel=load sata ${satadev} ${loadaddr} ${kernel}\0" \
+	"sataloadfdt=load sata ${satadev} ${fdtaddr} ${fdtfile}\0" \
+	"sataboot=echo Booting from sata ...; "\
+		"run sataargs; " \
+		"run doboot\0" \
+	"nandroot=/dev/mtdblock4 rw\0" \
+	"nandrootfstype=ubifs\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype} " \
+		"${video}\0" \
+	"nandloadfdt=nand read ${fdtaddr} 780000 80000;\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 0 780000; " \
+		"if ${loadfdt}; then " \
+			"run nandloadfdt;" \
+		"fi; " \
+		"run doboot\0" \
+	"boot=mmc dev ${mmcdev}; " \
+		"if mmc rescan; then " \
+			"if run loadmmcbootscript; then " \
+				"run mmcbootscript;" \
+			"else " \
+				"if run mmcloadkernel; then " \
+					"if ${loadfdt}; then " \
+						"run mmcloadfdt;" \
+					"fi;" \
+					"run mmcboot;" \
+				"fi;" \
+			"fi;" \
+		"fi;" \
+		"if sata init; then " \
+			"if run loadsatabootscript; then " \
+				"run satabootscript;" \
+			"else "\
+				"if run sataloadkernel; then " \
+					"if ${loadfdt}; then " \
+						"run sataloadfdt; " \
+					"fi;" \
+					"run sataboot;" \
+				"fi;" \
+			"fi;" \
+		"fi;" \
+		"run nandboot\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"run setboottypem; run boot"
+
+/* SPI */
+#define CONFIG_SPI
+#define CONFIG_MXC_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ATMEL
+#define CONFIG_SPI_FLASH_EON
+#define CONFIG_SPI_FLASH_GIGADEVICE
+#define CONFIG_SPI_FLASH_MACRONIX
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_WINBOND
+
+/* NAND */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_MAX_CHIPS	1
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_NAND_MXS
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+/* APBH DMA is required for NAND support */
+#define CONFIG_APBH_DMA
+#define CONFIG_APBH_DMA_BURST
+#define CONFIG_APBH_DMA_BURST8
+#endif
+
+/* Ethernet */
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_PHYADDR		0
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+#define CONFIG_MII
+#define CONFIG_ETHPRIME			"FEC0"
+#define CONFIG_ARP_TIMEOUT		200UL
+#define CONFIG_NETMASK			255.255.255.0
+#define CONFIG_NET_RETRY_COUNT		5
+
+/* USB */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET	/* For OTG port */
+
+/* I2C */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_MXC_I2C3_SPEED	400000
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_I2C_EEPROM_BUS	2
+
+/* SATA */
+#define CONFIG_CMD_SATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_LIBATA
+#define CONFIG_LBA48
+#define CONFIG_DWC_AHSATA
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+
+/* GPIO */
+#define CONFIG_MXC_GPIO
+
+/* Boot */
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_LOADADDR			0x10800000
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SYS_BOOTMAPSZ	        (8 << 20)
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SERIAL_TAG
+
+/* misc */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_STACKSIZE			(128 * 1024)
+#define CONFIG_SYS_MALLOC_LEN			(2 * 1024 * 1024)
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	800 /* 400 KB */
+#define CONFIG_OF_BOARD_SETUP
+
+/* SPL */
+#include "imx6_spl.h"
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x80 /* offset 64 kb */
+#define CONFIG_SYS_MONITOR_LEN	(CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS / 2 * 1024)
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	(64 * 1024)
+#define CONFIG_SPL_SPI_LOAD
+
+#endif	/* __CONFIG_CM_FX6_H */
diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h
index a3e6452..767ef3a 100644
--- a/include/configs/cm_t335.h
+++ b/include/configs/cm_t335.h
@@ -107,6 +107,7 @@
 /* I2C Configuration */
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_I2C_EEPROM_BUS	0
 
 /* SPL */
 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index 70df1eb..6f4d97f 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -135,6 +135,7 @@
 #define CONFIG_SYS_I2C_OMAP34XX
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_I2C_EEPROM_BUS	0
 #define CONFIG_I2C_MULTI_BUS
 
 /*
diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h
index df93a59..641ab48 100644
--- a/include/configs/cm_t54.h
+++ b/include/configs/cm_t54.h
@@ -30,6 +30,7 @@
 #define CONFIG_SYS_I2C_OMAP34XX
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_I2C_EEPROM_BUS	0
 
 /* Enable SD/MMC CD and WP GPIOs */
 #define OMAP_HSMMC_USE_GPIO
diff --git a/include/configs/colibri_t20_iris.h b/include/configs/colibri_t20_iris.h
index 6f9e08c..2b876fe 100644
--- a/include/configs/colibri_t20_iris.h
+++ b/include/configs/colibri_t20_iris.h
@@ -9,11 +9,6 @@
 
 #include "tegra20-common.h"
 
-/* Enable FDT support */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra20-colibri_t20_iris
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* High-level configuration options */
 #define V_PROMPT                   "Tegra20 (Colibri) # "
 #define CONFIG_TEGRA_BOARD_STRING  "Toradex Colibri T20 on Iris"
diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h
index eacff5b..782b9d1 100644
--- a/include/configs/colibri_t30.h
+++ b/include/configs/colibri_t30.h
@@ -11,9 +11,6 @@
 
 #include "tegra30-common.h"
 
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra30-colibri
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
 
 #define V_PROMPT			"Colibri T30 # "
 #define CONFIG_TEGRA_BOARD_STRING	"Toradex Colibri T30"
diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h
index 7eaaf69..bfcfa0c 100644
--- a/include/configs/controlcenterd.h
+++ b/include/configs/controlcenterd.h
@@ -434,7 +434,6 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_LAST_STAGE_INIT
-#undef CONFIG_CMD_BOOTM
 
 #endif /* CONFIG_TRAILBLAZER */
 
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index a1a63a0..936be14 100644
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -28,9 +28,6 @@
 
 #define CONFIG_LMB
 #define CONFIG_OF_LIBFDT
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-#define CONFIG_DEFAULT_DEVICE_TREE	link
 
 #define CONFIG_BOOTSTAGE
 #define CONFIG_BOOTSTAGE_REPORT
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 1252d7a..5f85755 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -157,8 +157,6 @@
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS 0
-#define CONFIG_SPL_SPI_CS 0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8000
 #define CONFIG_SYS_SPI_U_BOOT_SIZE	0x30000
 #endif
@@ -376,8 +374,6 @@
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS 0
-#define CONFIG_SPL_SPI_CS 0
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h
index fd774a3..ff7ec4a 100644
--- a/include/configs/dalmore.h
+++ b/include/configs/dalmore.h
@@ -21,11 +21,6 @@
 
 #include "tegra114-common.h"
 
-/* Enable fdt support for Dalmore. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra114-dalmore
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* High-level configuration options */
 #define V_PROMPT		"Tegra114 (Dalmore) # "
 #define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Dalmore"
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 4143a4d..2eaabde 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -116,8 +116,6 @@
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
-#define CONFIG_SPL_SPI_BUS             0
-#define CONFIG_SPL_SPI_CS              0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x40000
 
 #define CONFIG_SUPPORT_EMMC_BOOT
diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h
index a7fd43b..185edbe 100644
--- a/include/configs/embestmx6boards.h
+++ b/include/configs/embestmx6boards.h
@@ -102,7 +102,7 @@
 #define CONFIG_SPI_FLASH_SST
 #define CONFIG_MXC_SPI
 #define CONFIG_SF_DEFAULT_BUS		0
-#define CONFIG_SF_DEFAULT_CS		(0 | (IMX_GPIO_NR(2, 30) << 8))
+#define CONFIG_SF_DEFAULT_CS		0
 #define CONFIG_SF_DEFAULT_SPEED		20000000
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
 #endif
diff --git a/include/configs/exynos4-dt.h b/include/configs/exynos4-dt.h
index 7dac1a3..99472ac 100644
--- a/include/configs/exynos4-dt.h
+++ b/include/configs/exynos4-dt.h
@@ -22,10 +22,6 @@
 #define CONFIG_BOARD_COMMON
 #define CONFIG_SYS_GENERIC_BOARD
 
-/* Enable fdt support */
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 #define CONFIG_SYS_CACHELINE_SIZE	32
 
 /* input clock of PLL: EXYNOS4 boards have 24MHz input clock */
diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h
index a7c6292..1dc3002 100644
--- a/include/configs/exynos5-dt.h
+++ b/include/configs/exynos5-dt.h
@@ -24,10 +24,6 @@
 #define CONFIG_ARCH_EARLY_INIT_R
 #define CONFIG_EXYNOS_SPL
 
-/* Enable fdt support for Exynos5250 */
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* Allow tracing to be enabled */
 #define CONFIG_TRACE
 #define CONFIG_CMD_TRACE
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index b991b09..620f950 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -61,7 +61,7 @@
   #define CONFIG_SPI_FLASH_BAR
   #define CONFIG_SPI_FLASH_WINBOND
   #define CONFIG_SF_DEFAULT_BUS              0
-  #define CONFIG_SF_DEFAULT_CS               (0|(IMX_GPIO_NR(3, 19)<<8))
+  #define CONFIG_SF_DEFAULT_CS               0
 					     /* GPIO 3-19 (21248) */
   #define CONFIG_SF_DEFAULT_SPEED            30000000
   #define CONFIG_SF_DEFAULT_MODE             (SPI_MODE_0)
@@ -141,6 +141,7 @@
 #define CONFIG_PCI
 #define CONFIG_PCI_PNP
 #define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCI_FIXUP_DEV
 #define CONFIG_PCIE_IMX
 #endif
 
diff --git a/include/configs/h2200.h b/include/configs/h2200.h
index 9470ad6..109cee9 100644
--- a/include/configs/h2200.h
+++ b/include/configs/h2200.h
@@ -116,7 +116,6 @@
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 38400, 115200 }
 
-#define CONFIG_CMD_IMPORTENV		1
 #define CONFIG_CMD_LOADB
 #define CONFIG_CMD_SOURCE
 #define CONFIG_CMD_RUN
diff --git a/include/configs/harmony.h b/include/configs/harmony.h
index 3ec0e41..ff9fbc9 100644
--- a/include/configs/harmony.h
+++ b/include/configs/harmony.h
@@ -11,11 +11,6 @@
 #include <linux/sizes.h>
 #include "tegra20-common.h"
 
-/* Enable fdt support for Harmony. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra20-harmony
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* High-level configuration options */
 #define V_PROMPT		"Tegra20 (Harmony) # "
 #define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Harmony"
diff --git a/include/configs/ip04.h b/include/configs/ip04.h
index 3767502..ec510bd 100644
--- a/include/configs/ip04.h
+++ b/include/configs/ip04.h
@@ -133,7 +133,6 @@
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_MISC_INIT_R	/* needed for MAC address */
 #define CONFIG_UART_CONSOLE	0
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 #undef CONFIG_SHOW_BOOT_PROGRESS
 /* Enable this if bootretry required; currently it's disabled */
diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h
index d03a66c..d67c025 100644
--- a/include/configs/jetson-tk1.h
+++ b/include/configs/jetson-tk1.h
@@ -12,11 +12,6 @@
 
 #include "tegra124-common.h"
 
-/* Enable fdt support for Jetson TK1. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra124-jetson-tk1
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* High-level configuration options */
 #define V_PROMPT			"Tegra124 (Jetson TK1) # "
 #define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Jetson TK1"
diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h
index 43db581..51926f7 100644
--- a/include/configs/ks2_evm.h
+++ b/include/configs/ks2_evm.h
@@ -58,8 +58,6 @@
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_BOARD_INIT
 #define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS		0
-#define CONFIG_SPL_SPI_CS		0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
 #define CONFIG_SPL_FRAMEWORK
 
diff --git a/include/configs/kwb.h b/include/configs/kwb.h
index 0860434..29b263f 100644
--- a/include/configs/kwb.h
+++ b/include/configs/kwb.h
@@ -89,7 +89,6 @@
 #undef	CONFIG_BOOTM_RTEMS
 #undef	CONFIG_GZIP
 #undef	CONFIG_ZLIB
-#undef CONFIG_CMD_CRC32
 
 /* USB configuration */
 #define CONFIG_USB_MUSB_DSPS
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 657e3b6..bb47813 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -49,10 +49,12 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_DDR_SPD
 #define SPD_EEPROM_ADDRESS		0x51
 #define CONFIG_SYS_SPD_BUS_NUM		0
-#define CONFIG_SYS_DDR_RAW_TIMING
 
 #define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */
+#ifndef CONFIG_SYS_FSL_DDR4
 #define CONFIG_SYS_FSL_DDR3		/* Use DDR3 memory */
+#define CONFIG_SYS_DDR_RAW_TIMING
+#endif
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	4
 
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index 2bd5a47..a72e1f3 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -15,9 +15,11 @@
 #define CONFIG_GICV3
 
 /* Link Definitions */
-#define CONFIG_SYS_TEXT_BASE		0x30000000
+#define CONFIG_SYS_TEXT_BASE		0x30001000
 
+#ifdef CONFIG_EMU
 #define CONFIG_SYS_NO_FLASH
+#endif
 
 #define CONFIG_SUPPORT_RAW_INITRD
 
@@ -45,13 +47,27 @@
 
 #define CONFIG_SYS_FSL_DDR_INTLV_256B	/* force 256 byte interleaving */
 
-/* SMP Definitions */
-#define CPU_RELEASE_ADDR		CONFIG_SYS_INIT_SP_ADDR
-
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_SYS_DDR_BLOCK2_BASE	0x8080000000ULL
+#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS	2
+
+/*
+ * SMP Definitinos
+ */
+#define CPU_RELEASE_ADDR		secondary_boot_func
+
+#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
+#define CONFIG_SYS_DP_DDR_BASE		0x6000000000ULL
+/*
+ * DDR controller use 0 as the base address for binding.
+ * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
+ */
+#define CONFIG_SYS_DP_DDR_BASE_PHY	0
+#define CONFIG_DP_DDR_CTRL		2
+#define CONFIG_DP_DDR_NUM_CTRLS		1
+#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
 
 /* Generic Timer Definitions */
 #define COUNTER_FREQUENCY		12000000	/* 12MHz */
@@ -118,6 +134,66 @@
 #define CONFIG_SYS_NOR_FTIM3	0x04000000
 #define CONFIG_SYS_IFC_CCR	0x01000000
 
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#endif
+
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_MAX_ECCPOS	256
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+#define CONFIG_SYS_NAND_BASE		0x520000000
+#define CONFIG_SYS_NAND_BASE_PHYS	0x20000000
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 2Byes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
 #define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
@@ -167,6 +243,7 @@
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+#define CONFIG_ARCH_EARLY_INIT_R
 
 /* Physical Memory Map */
 /* fixme: these need to be checked against the board */
@@ -174,7 +251,7 @@
 #define CONFIG_SYS_CLK_FREQ	133333333
 
 
-#define CONFIG_NR_DRAM_BANKS		2
+#define CONFIG_NR_DRAM_BANKS		3
 
 #define CONFIG_SYS_HZ			1000
 
diff --git a/include/configs/ls2085a_emu.h b/include/configs/ls2085a_emu.h
index a5cea63..487cd99 100644
--- a/include/configs/ls2085a_emu.h
+++ b/include/configs/ls2085a_emu.h
@@ -13,6 +13,7 @@
 #define CONFIG_SYS_FSL_DDR_EMU		/* Support emulator */
 #define SPD_EEPROM_ADDRESS1	0x51
 #define SPD_EEPROM_ADDRESS2	0x52
+#define SPD_EEPROM_ADDRESS3	0x53
 #define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
 #define CONFIG_SYS_SPD_BUS_NUM	1	/* SPD on I2C bus 1 */
 
diff --git a/include/configs/ls2085a_simu.h b/include/configs/ls2085a_simu.h
index 46d47b0..0f40b78 100644
--- a/include/configs/ls2085a_simu.h
+++ b/include/configs/ls2085a_simu.h
@@ -13,4 +13,13 @@
 #define CONFIG_SMC91111
 #define CONFIG_SMC91111_BASE	(0x2210000)
 
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+
 #endif /* __LS2_SIMU_H */
diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h
index 40155c3..ac5208f 100644
--- a/include/configs/medcom-wide.h
+++ b/include/configs/medcom-wide.h
@@ -12,11 +12,6 @@
 
 #include "tegra20-common.h"
 
-/* Enable fdt support for Medcom-Wide. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra20-medcom-wide
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* High-level configuration options */
 #define V_PROMPT			"Tegra20 (Medcom-Wide) # "
 #define CONFIG_TEGRA_BOARD_STRING	"Avionic Design Medcom-Wide"
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index 1a82a57..bb07060 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -14,11 +14,6 @@
 /* MicroBlaze CPU */
 #define	MICROBLAZE_V5		1
 
-/* Open Firmware DTS */
-#define CONFIG_OF_CONTROL	1
-#define CONFIG_OF_EMBED		1
-#define CONFIG_DEFAULT_DEVICE_TREE microblaze-generic
-
 /* linear and spi flash memory */
 #ifdef XILINX_FLASH_START
 #define	FLASH
diff --git a/include/configs/mx51_efikamx.h b/include/configs/mx51_efikamx.h
index 0f2a4ef..fce7ead 100644
--- a/include/configs/mx51_efikamx.h
+++ b/include/configs/mx51_efikamx.h
@@ -96,11 +96,11 @@
 
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_SST
-#define CONFIG_SF_DEFAULT_CS		(1 | 121 << 8)
+#define CONFIG_SF_DEFAULT_CS		1
 #define CONFIG_SF_DEFAULT_MODE		(SPI_MODE_0)
 #define CONFIG_SF_DEFAULT_SPEED		25000000
 
-#define CONFIG_ENV_SPI_CS		(1 | 121 << 8)
+#define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
 #define CONFIG_ENV_SPI_BUS		0
 #define CONFIG_ENV_SPI_MAX_HZ		25000000
 #define CONFIG_ENV_SPI_MODE		(SPI_MODE_0)
diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h
index fd651cf..35c0a85 100644
--- a/include/configs/mx6qarm2.h
+++ b/include/configs/mx6qarm2.h
@@ -23,6 +23,8 @@
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
 
+#define CONFIG_SYS_GENERIC_BOARD
+
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
 
diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h
index d1639c4..0ab3127 100644
--- a/include/configs/mx6qsabreauto.h
+++ b/include/configs/mx6qsabreauto.h
@@ -45,7 +45,4 @@
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_SPEED		100000
 
-#define CONFIG_OF_SEPARATE
-#define CONFIG_DEFAULT_DEVICE_TREE   imx6q-sabreauto
-
 #endif                         /* __MX6QSABREAUTO_CONFIG_H */
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index e59a3b4..2d93d6c 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -74,7 +74,7 @@
 #define CONFIG_SPI_FLASH_STMICRO
 #define CONFIG_MXC_SPI
 #define CONFIG_SF_DEFAULT_BUS		0
-#define CONFIG_SF_DEFAULT_CS		(0 | (IMX_GPIO_NR(4, 9) << 8))
+#define CONFIG_SF_DEFAULT_CS		0
 #define CONFIG_SF_DEFAULT_SPEED		20000000
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
 #endif
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index 3d05a64..4208ba1 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -26,6 +26,8 @@
 #define CONFIG_INITRD_TAG
 #define CONFIG_REVISION_TAG
 
+#define CONFIG_SYS_GENERIC_BOARD
+
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(3 * SZ_1M)
 
@@ -203,7 +205,7 @@
 #define CONFIG_SPI_FLASH_STMICRO
 #define CONFIG_MXC_SPI
 #define CONFIG_SF_DEFAULT_BUS		0
-#define CONFIG_SF_DEFAULT_CS		(0 | (IMX_GPIO_NR(4, 11) << 8))
+#define CONFIG_SF_DEFAULT_CS		0
 #define CONFIG_SF_DEFAULT_SPEED		20000000
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
 #endif
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 1eda65e..b92d944 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -198,6 +198,16 @@
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 
+#define CONFIG_CMD_PCI
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+#define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(2, 1)
+#define CONFIG_PCIE_IMX_POWER_GPIO	IMX_GPIO_NR(2, 0)
+#endif
+
 /* FLASH and environment organization */
 #define CONFIG_SYS_NO_FLASH
 
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index b2b17ce..39d5bb3 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -53,7 +53,7 @@
 #define CONFIG_SPI_FLASH_SST
 #define CONFIG_MXC_SPI
 #define CONFIG_SF_DEFAULT_BUS  0
-#define CONFIG_SF_DEFAULT_CS   (0|(IMX_GPIO_NR(3, 19)<<8))
+#define CONFIG_SF_DEFAULT_CS   0
 #define CONFIG_SF_DEFAULT_SPEED 25000000
 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
 #endif
@@ -192,11 +192,11 @@
 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
 		"root=${mmcroot}\0" \
 	"loadbootscript=" \
-		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+		"load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source\0" \
-	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
-	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"loaduimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
diff --git a/include/configs/odroid.h b/include/configs/odroid.h
index 29dcc4a..b616ac2 100644
--- a/include/configs/odroid.h
+++ b/include/configs/odroid.h
@@ -16,8 +16,6 @@
 
 #define CONFIG_SYS_PROMPT	"Odroid # "	/* Monitor Command Prompt */
 
-#undef CONFIG_DEFAULT_DEVICE_TREE
-#define CONFIG_DEFAULT_DEVICE_TREE	exynos4412-odroid
 
 #define CONFIG_SYS_L2CACHE_OFF
 #ifndef CONFIG_SYS_L2CACHE_OFF
diff --git a/include/configs/origen.h b/include/configs/origen.h
index 5d24916..fb1536c 100644
--- a/include/configs/origen.h
+++ b/include/configs/origen.h
@@ -13,8 +13,6 @@
 
 #define CONFIG_SYS_PROMPT		"ORIGEN # "
 
-#undef CONFIG_DEFAULT_DEVICE_TREE
-#define CONFIG_DEFAULT_DEVICE_TREE	exynos4210-origen
 
 /* High Level Configuration Options */
 #define CONFIG_EXYNOS4210		1	/* which is a EXYNOS4210 SoC */
diff --git a/include/configs/paz00.h b/include/configs/paz00.h
index dd0abf8..45bb470 100644
--- a/include/configs/paz00.h
+++ b/include/configs/paz00.h
@@ -20,11 +20,6 @@
 #include <linux/sizes.h>
 #include "tegra20-common.h"
 
-/* Enable fdt support for Paz00. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra20-paz00
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* High-level configuration options */
 #define V_PROMPT		"Tegra20 (Paz00) MOD # "
 #define CONFIG_TEGRA_BOARD_STRING	"Compal Paz00"
diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
index 5efcd76..7d102a4 100644
--- a/include/configs/pcm051.h
+++ b/include/configs/pcm051.h
@@ -128,8 +128,6 @@
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS		0
-#define CONFIG_SPL_SPI_CS		0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
 #define CONFIG_SYS_SPI_U_BOOT_SIZE	0x40000
 #endif
diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h
index 88c093f..987cef5 100644
--- a/include/configs/peach-pit.h
+++ b/include/configs/peach-pit.h
@@ -13,8 +13,6 @@
 
 #include <configs/exynos5420.h>
 
-#undef CONFIG_DEFAULT_DEVICE_TREE
-#define CONFIG_DEFAULT_DEVICE_TREE	exynos5420-peach-pit
 
 /* select serial console configuration */
 #define CONFIG_SERIAL3		/* use SERIAL 3 */
diff --git a/include/configs/ph1_ld4.h b/include/configs/ph1_ld4.h
new file mode 100644
index 0000000..a28d7b5
--- /dev/null
+++ b/include/configs/ph1_ld4.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __PH1_XXX_H
+#define __PH1_XXX_H
+
+/*
+ * Support Card Select
+ *
+ *  CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC.
+ *  CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card.
+ *                       CPLD is re-programmed for ARIMA board compatibility.
+ *  No define                     - No support card.
+ */
+
+#if 0
+#define CONFIG_PFC_MICRO_SUPPORT_CARD
+#else
+#define CONFIG_DCC_MICRO_SUPPORT_CARD
+#endif
+
+/*
+ * Serial Configuration
+ *   SoC UART     : enable CONFIG_UNIPHIER_SERIAL
+ *   On-board UART: enable CONFIG_SYS_NS16550_SERIAL
+ */
+#if 1
+#define CONFIG_UNIPHIER_SERIAL
+#else
+#define CONFIG_SYS_NS16550_SERIAL
+#endif
+
+#define CONFIG_SYS_UNIPHIER_UART_CLK    36864000
+
+#define CONFIG_SMC911X
+
+#define CONFIG_DDR_NUM_CH0 1
+#define CONFIG_DDR_NUM_CH1 1
+
+#define CONFIG_DDR_FREQ 1600
+
+/*
+ * Memory Size & Mapping
+ */
+/* Physical start address of SDRAM */
+#define CONFIG_SDRAM0_BASE	0x80000000
+#define CONFIG_SDRAM0_SIZE	0x10000000
+#define CONFIG_SDRAM1_BASE	0x90000000
+#define CONFIG_SDRAM1_SIZE	0x10000000
+
+#define CONFIG_SPL_TEXT_BASE 0x40000
+
+#include "uniphier-common.h"
+
+#endif /* __PH1_XXX_H */
diff --git a/include/configs/ph1_pro4.h b/include/configs/ph1_pro4.h
new file mode 100644
index 0000000..b79967f
--- /dev/null
+++ b/include/configs/ph1_pro4.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __PH1_XXX_H
+#define __PH1_XXX_H
+
+/*
+ * Support Card Select
+ *
+ *  CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC.
+ *  CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card.
+ *                       CPLD is re-programmed for ARIMA board compatibility.
+ *  No define                     - No support card.
+ */
+
+#if 0
+#define CONFIG_PFC_MICRO_SUPPORT_CARD
+#else
+#define CONFIG_DCC_MICRO_SUPPORT_CARD
+#endif
+
+/*
+ * Serial Configuration
+ *   SoC UART     : enable CONFIG_UNIPHIER_SERIAL
+ *   On-board UART: enable CONFIG_SYS_NS16550_SERIAL
+ */
+#if 1
+#define CONFIG_UNIPHIER_SERIAL
+#else
+#define CONFIG_SYS_NS16550_SERIAL
+#endif
+
+#define CONFIG_SYS_UNIPHIER_UART_CLK    73728000
+
+#define CONFIG_SMC911X
+
+#define CONFIG_DDR_NUM_CH0 2
+#define CONFIG_DDR_NUM_CH1 2
+
+#define CONFIG_DDR_FREQ 1600
+
+#define CONFIG_UNIPHIER_SMP
+
+/*
+ * Memory Size & Mapping
+ */
+/* Physical start address of SDRAM */
+#define CONFIG_SDRAM0_BASE	0x80000000
+#define CONFIG_SDRAM0_SIZE	0x20000000
+#define CONFIG_SDRAM1_BASE	0xa0000000
+#define CONFIG_SDRAM1_SIZE	0x20000000
+
+#define CONFIG_SPL_TEXT_BASE 0x100000
+
+#include "uniphier-common.h"
+
+#endif /* __PH1_XXX_H */
diff --git a/include/configs/ph1_sld8.h b/include/configs/ph1_sld8.h
new file mode 100644
index 0000000..9d391f1
--- /dev/null
+++ b/include/configs/ph1_sld8.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __PH1_XXX_H
+#define __PH1_XXX_H
+
+/*
+ * Support Card Select
+ *
+ *  CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC.
+ *  CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card.
+ *                       CPLD is re-programmed for ARIMA board compatibility.
+ *  No define                     - No support card.
+ */
+
+#if 0
+#define CONFIG_PFC_MICRO_SUPPORT_CARD
+#else
+#define CONFIG_DCC_MICRO_SUPPORT_CARD
+#endif
+
+/*
+ * Serial Configuration
+ *   SoC UART     : enable CONFIG_UNIPHIER_SERIAL
+ *   On-board UART: enable CONFIG_SYS_NS16550_SERIAL
+ */
+#if 1
+#define CONFIG_UNIPHIER_SERIAL
+#else
+#define CONFIG_SYS_NS16550_SERIAL
+#endif
+
+#define CONFIG_SYS_UNIPHIER_UART_CLK    80000000
+
+#define CONFIG_SMC911X
+
+#define CONFIG_DDR_NUM_CH0 1
+#define CONFIG_DDR_NUM_CH1 1
+
+#define CONFIG_DDR_FREQ 1333
+
+/* #define CONFIG_DDR_STANDARD */
+
+/*
+ * Memory Size & Mapping
+ */
+/* Physical start address of SDRAM */
+#define CONFIG_SDRAM0_BASE	0x80000000
+#define CONFIG_SDRAM0_SIZE	0x10000000
+#define CONFIG_SDRAM1_BASE	0x90000000
+#define CONFIG_SDRAM1_SIZE	0x10000000
+
+#define CONFIG_SPL_TEXT_BASE 0x40000
+
+#include "uniphier-common.h"
+
+#endif /* __PH1_XXX_H */
diff --git a/include/configs/plutux.h b/include/configs/plutux.h
index a473f23..b663b89 100644
--- a/include/configs/plutux.h
+++ b/include/configs/plutux.h
@@ -12,11 +12,6 @@
 
 #include "tegra20-common.h"
 
-/* Enable fdt support for Plutux. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra20-plutux
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* High-level configuration options */
 #define V_PROMPT			"Tegra20 (Plutux) # "
 #define CONFIG_TEGRA_BOARD_STRING	"Avionic Design Plutux"
diff --git a/include/configs/pr1.h b/include/configs/pr1.h
index e96ed4b..0f57e86 100644
--- a/include/configs/pr1.h
+++ b/include/configs/pr1.h
@@ -135,7 +135,6 @@
 #define CONFIG_BOOTCOMMAND	"run nandboot"
 #define CONFIG_BOOTDELAY	2
 #define CONFIG_LOADADDR		0x2000000
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h
index 20985da..082d51c 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -14,8 +14,6 @@
 
 #define CONFIG_SYS_PROMPT	"Universal # "	/* Monitor Command Prompt */
 
-#undef CONFIG_DEFAULT_DEVICE_TREE
-#define CONFIG_DEFAULT_DEVICE_TREE	exynos4210-universal_c210
 
 #define CONFIG_TIZEN			/* TIZEN lib */
 
diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h
index 56c2454..c46baf2 100644
--- a/include/configs/sama5d3xek.h
+++ b/include/configs/sama5d3xek.h
@@ -79,8 +79,19 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-/* No NOR flash */
+/* NOR flash */
+#define CONFIG_CMD_FLASH
+
+#ifdef CONFIG_CMD_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_BASE		0x10000000
+#define CONFIG_SYS_MAX_FLASH_SECT	131
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#else
 #define CONFIG_SYS_NO_FLASH
+#endif
 
 /*
  * Command line configuration.
@@ -287,8 +298,6 @@
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS		0
-#define CONFIG_SPL_SPI_CS		0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8400
 
 #endif
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index f5fa4b3..6972643 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -38,15 +38,12 @@
 /* Number of bits in a C 'long' on this architecture */
 #define CONFIG_SANDBOX_BITS_PER_LONG	64
 
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_HOSTFILE
 #define CONFIG_OF_LIBFDT
 #define CONFIG_LMB
 #define CONFIG_FIT
 #define CONFIG_FIT_SIGNATURE
 #define CONFIG_RSA
 #define CONFIG_CMD_FDT
-#define CONFIG_DEFAULT_DEVICE_TREE	sandbox
 #define CONFIG_ANDROID_BOOT_IMAGE
 
 #define CONFIG_FS_FAT
@@ -94,7 +91,7 @@
 #define CONFIG_ENV_SIZE		8192
 #define CONFIG_ENV_IS_NOWHERE
 
-/* SPI */
+/* SPI - enable all SPI flash types for testing purposes */
 #define CONFIG_SANDBOX_SPI
 #define CONFIG_CMD_SF
 #define CONFIG_CMD_SF_TEST
@@ -102,7 +99,13 @@
 #define CONFIG_SPI_FLASH
 #define CONFIG_OF_SPI
 #define CONFIG_OF_SPI_FLASH
+#define CONFIG_SPI_FLASH_ATMEL
+#define CONFIG_SPI_FLASH_EON
+#define CONFIG_SPI_FLASH_GIGADEVICE
+#define CONFIG_SPI_FLASH_MACRONIX
 #define CONFIG_SPI_FLASH_SANDBOX
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_SST
 #define CONFIG_SPI_FLASH_STMICRO
 #define CONFIG_SPI_FLASH_WINBOND
 
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index fc4f976..04e4f82 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -19,11 +19,6 @@
 
 #include "tegra20-common.h"
 
-/* Enable fdt support for Seaboard. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra20-seaboard
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* High-level configuration options */
 #define V_PROMPT		"Tegra20 (SeaBoard) # "
 #define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Seaboard"
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index b8fb77e..bf9752f 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -167,8 +167,6 @@
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS		0
-#define CONFIG_SPL_SPI_CS		0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
 
 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h
index 66fa179..6117094 100644
--- a/include/configs/smdk5250.h
+++ b/include/configs/smdk5250.h
@@ -11,8 +11,6 @@
 
 #include <configs/exynos5250-dt.h>
 
-#undef CONFIG_DEFAULT_DEVICE_TREE
-#define CONFIG_DEFAULT_DEVICE_TREE	exynos5250-smdk5250
 
 /* Enable FIT support and comparison */
 #define CONFIG_FIT
diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h
index 606739b..36a156f 100644
--- a/include/configs/smdk5420.h
+++ b/include/configs/smdk5420.h
@@ -15,8 +15,6 @@
 
 #define CONFIG_SMDK5420			/* which is in a SMDK5420 */
 
-#undef CONFIG_DEFAULT_DEVICE_TREE
-#define CONFIG_DEFAULT_DEVICE_TREE	exynos5420-smdk5420
 
 /* select serial console configuration */
 #define CONFIG_SERIAL3		/* use SERIAL 3 */
diff --git a/include/configs/snow.h b/include/configs/snow.h
index 673fa14..fbaaa59 100644
--- a/include/configs/snow.h
+++ b/include/configs/snow.h
@@ -11,8 +11,6 @@
 
 #include <configs/exynos5250-dt.h>
 
-#undef CONFIG_DEFAULT_DEVICE_TREE
-#define CONFIG_DEFAULT_DEVICE_TREE	exynos5250-snow
 
 /* Enable FIT support and comparison */
 #define CONFIG_FIT
diff --git a/include/configs/tcm-bf518.h b/include/configs/tcm-bf518.h
index a77ba69..6673026 100644
--- a/include/configs/tcm-bf518.h
+++ b/include/configs/tcm-bf518.h
@@ -116,7 +116,6 @@
 #define CONFIG_UART_CONSOLE	0
 #define CONFIG_BOOTCOMMAND	"run flashboot"
 #define FLASHBOOT_ENV_SETTINGS	"flashboot=bootm 0x20040000\0"
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h
index c4c1c57..9998343 100644
--- a/include/configs/tcm-bf537.h
+++ b/include/configs/tcm-bf537.h
@@ -145,7 +145,6 @@
 	"flashboot=flread 20040000 1000000 300000;" \
 	"bootm 0x1000000\0"
 #define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h
index 13baa76..51f87da 100644
--- a/include/configs/tec-ng.h
+++ b/include/configs/tec-ng.h
@@ -10,11 +10,6 @@
 
 #include "tegra30-common.h"
 
-/* Enable fdt support for tec-ng. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra30-tec-ng
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* High-level configuration options */
 #define V_PROMPT			"Tegra30 (TEC-NG) # "
 #define CONFIG_TEGRA_BOARD_STRING	"Avionic Design Tamonten™ NG Evaluation Carrier"
diff --git a/include/configs/tec.h b/include/configs/tec.h
index 90e7b7a..9ea4ff4 100644
--- a/include/configs/tec.h
+++ b/include/configs/tec.h
@@ -12,11 +12,6 @@
 
 #include "tegra20-common.h"
 
-/* Enable fdt support for TEC. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra20-tec
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* High-level configuration options */
 #define V_PROMPT			"Tegra20 (TEC) # "
 #define CONFIG_TEGRA_BOARD_STRING	"Avionic Design Tamonten Evaluation Carrier"
diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h
index c337e30..23e3c8a 100644
--- a/include/configs/tegra-common-post.h
+++ b/include/configs/tegra-common-post.h
@@ -69,7 +69,6 @@
 
 /* remove devicetree support */
 #ifdef CONFIG_OF_CONTROL
-#undef CONFIG_OF_CONTROL
 #endif
 
 /* remove I2C support */
diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h
index 8c7310c..b0f199e 100644
--- a/include/configs/ti_omap4_common.h
+++ b/include/configs/ti_omap4_common.h
@@ -101,10 +101,10 @@
 		"vram=${vram} " \
 		"root=${mmcroot} " \
 		"rootfstype=${mmcrootfstype}\0" \
-	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 	"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
 		"source ${loadaddr}\0" \
-	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
+	"loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
 	"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
 		"env import -t ${loadaddr} ${filesize}\0" \
 	"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
diff --git a/include/configs/trats.h b/include/configs/trats.h
index 6fa646b..43751e7 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -16,8 +16,6 @@
 
 #define CONFIG_TRATS
 
-#undef CONFIG_DEFAULT_DEVICE_TREE
-#define CONFIG_DEFAULT_DEVICE_TREE	exynos4210-trats
 
 #define CONFIG_TIZEN			/* TIZEN lib */
 
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index 1450865..e9a04f7 100644
--- a/include/configs/trats2.h
+++ b/include/configs/trats2.h
@@ -15,8 +15,6 @@
 
 #define CONFIG_SYS_PROMPT	"Trats2 # "	/* Monitor Command Prompt */
 
-#undef CONFIG_DEFAULT_DEVICE_TREE
-#define CONFIG_DEFAULT_DEVICE_TREE	exynos4412-trats2
 
 #define CONFIG_TIZEN			/* TIZEN lib */
 
diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h
index f81cfa2..7c00642 100644
--- a/include/configs/trimslice.h
+++ b/include/configs/trimslice.h
@@ -11,11 +11,6 @@
 #include <linux/sizes.h>
 #include "tegra20-common.h"
 
-/* Enable fdt support for TrimSlice. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra20-trimslice
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* High-level configuration options */
 #define V_PROMPT		"Tegra20 (TrimSlice) # "
 #define CONFIG_TEGRA_BOARD_STRING	"Compulab Trimslice"
diff --git a/include/configs/tseries.h b/include/configs/tseries.h
index 1dd13fd..9a62070 100644
--- a/include/configs/tseries.h
+++ b/include/configs/tseries.h
@@ -222,8 +222,6 @@
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS		0
-#define CONFIG_SPL_SPI_CS		0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
 #undef CONFIG_ENV_IS_NOWHERE
 #define CONFIG_ENV_IS_IN_SPI_FLASH
diff --git a/include/configs/uniphier-common.h b/include/configs/uniphier-common.h
new file mode 100644
index 0000000..18fe277
--- /dev/null
+++ b/include/configs/uniphier-common.h
@@ -0,0 +1,266 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* U-boot - Common settings for UniPhier Family */
+
+#ifndef __CONFIG_UNIPHIER_COMMON_H__
+#define __CONFIG_UNIPHIER_COMMON_H__
+
+#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) &&	\
+				defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
+# error "Both CONFIG_PFC_MICRO_SUPPORT_CARD and CONFIG_DCC_MICRO_SUPPORT_CARD \
+are defined. Select only one of them."
+#endif
+
+/*
+ * Support card address map
+ */
+#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
+# define CONFIG_SUPPORT_CARD_BASE	0x03f00000
+# define CONFIG_SUPPORT_CARD_ETHER_BASE	(CONFIG_SUPPORT_CARD_BASE + 0x00000000)
+# define CONFIG_SUPPORT_CARD_LED_BASE	(CONFIG_SUPPORT_CARD_BASE + 0x00090000)
+# define CONFIG_SUPPORT_CARD_UART_BASE	(CONFIG_SUPPORT_CARD_BASE + 0x000b0000)
+#endif
+
+#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
+# define CONFIG_SUPPORT_CARD_BASE	0x08000000
+# define CONFIG_SUPPORT_CARD_ETHER_BASE	(CONFIG_SUPPORT_CARD_BASE + 0x00000000)
+# define CONFIG_SUPPORT_CARD_LED_BASE	(CONFIG_SUPPORT_CARD_BASE + 0x00401630)
+# define CONFIG_SUPPORT_CARD_UART_BASE	(CONFIG_SUPPORT_CARD_BASE + 0x00200000)
+#endif
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_COM1		CONFIG_SUPPORT_CARD_UART_BASE
+#define CONFIG_SYS_NS16550_CLK		12288000
+#define CONFIG_SYS_NS16550_REG_SIZE	-2
+
+#define CONFIG_SMC911X_BASE		CONFIG_SUPPORT_CARD_ETHER_BASE
+#define CONFIG_SMC911X_32_BIT
+
+#define CONFIG_SYS_UNIPHIER_SERIAL_BASE0 0x54006800
+#define CONFIG_SYS_UNIPHIER_SERIAL_BASE1 0x54006900
+#define CONFIG_SYS_UNIPHIER_SERIAL_BASE2 0x54006a00
+#define CONFIG_SYS_UNIPHIER_SERIAL_BASE3 0x54006b00
+
+/*-----------------------------------------------------------------------
+ * MMU and Cache Setting
+ *----------------------------------------------------------------------*/
+
+/* Comment out the following to enable L1 cache */
+/* #define CONFIG_SYS_ICACHE_OFF */
+/* #define CONFIG_SYS_DCACHE_OFF */
+
+/* Comment out the following to enable L2 cache */
+#define CONFIG_UNIPHIER_L2CACHE_ON
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+#define CONFIG_TIMESTAMP
+
+/* FLASH related */
+#define CONFIG_MTD_DEVICE
+
+/*
+ * uncomment the following to disable FLASH related code.
+ */
+/* #define CONFIG_SYS_NO_FLASH */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+#define CONFIG_SYS_MONITOR_BASE		0
+#define CONFIG_SYS_FLASH_BASE		0
+
+/*
+ * flash_toggle does not work for out supoort card.
+ * We need to use flash_status_poll.
+ */
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
+
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
+# define CONFIG_SYS_MAX_FLASH_BANKS	1
+# define CONFIG_SYS_FLASH_BANKS_LIST	{0x00000000}
+# define CONFIG_SYS_FLASH_BANKS_SIZES	{0x02000000}
+#endif
+
+#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
+# define CONFIG_SYS_MAX_FLASH_BANKS	1
+# define CONFIG_SYS_FLASH_BANKS_LIST	{0x04000000}
+# define CONFIG_SYS_FLASH_BANKS_SIZES	{0x04000000}
+#endif
+
+/* serial console configuration */
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+#if !defined(CONFIG_SPL_BUILD)
+#define CONFIG_USE_ARCH_MEMSET
+#define CONFIG_USE_ARCH_MEMCPY
+#endif
+
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+
+#define CONFIG_CMDLINE_EDITING		/* add command line history	*/
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+
+#define CONFIG_CONS_INDEX		1
+
+/*
+ * For NAND booting the environment is embedded in the U-Boot image. Please take
+ * look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
+ */
+/* #define CONFIG_ENV_IS_IN_NAND */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE				0x2000
+#define CONFIG_ENV_OFFSET			0x0
+/* #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
+
+/* Time clock 1MHz */
+#define CONFIG_SYS_TIMER_RATE			1000000
+
+/*
+ * By default, ARP timeout is 5 sec.
+ * The first ARP request does not seem to work.
+ * So we need to retry ARP request anyway.
+ * We want to shrink the interval until the second ARP request.
+ */
+#define CONFIG_ARP_TIMEOUT	500UL  /* 0.5 msec */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_TIME
+#define CONFIG_CMD_NAND		/* NAND flash suppport */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE			1
+#define CONFIG_SYS_NAND_MAX_CHIPS			2
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#define CONFIG_NAND_DENALI_ECC_SIZE			1024
+
+#define CONFIG_SYS_NAND_REGS_BASE			0x68100000
+#define CONFIG_SYS_NAND_DATA_BASE			0x68000000
+
+#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_DATA_BASE + 0x10)
+
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS			0
+
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x01000000)
+
+#define CONFIG_BOOTDELAY			3
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_AUTOBOOT_KEYED			1
+#define CONFIG_AUTOBOOT_PROMPT	\
+	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR		"d"
+#define CONFIG_AUTOBOOT_STOP_STR		" "
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_ETHADDR			00:21:83:24:00:00
+#define CONFIG_SERVERIP			192.168.11.1
+#define CONFIG_IPADDR			192.168.11.10
+#define CONFIG_GATEWAYIP		192.168.11.1
+#define CONFIG_NETMASK			255.255.255.0
+
+#define CONFIG_LOADADDR			0x84000000
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_BOOTFILE			"fit.itb"
+
+#define CONFIG_CMDLINE_EDITING		/* add command line history	*/
+
+#define CONFIG_BOOTCOMMAND		"run $bootmode"
+
+#define CONFIG_ROOTPATH			"/nfs/root/path"
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs $bootargs root=/dev/nfs rw "			\
+	"nfsroot=$serverip:$rootpath "					\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
+	"tftpboot; bootm;"
+
+#define CONFIG_BOOTARGS		" user_debug=0x1f init=/sbin/init"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"image_offset=0x00080000\0"		\
+	"image_size=0x00f00000\0"		\
+	"verify=n\0"				\
+	"autostart=yes\0"			\
+	"norboot=run add_default_bootargs;"				\
+		"bootm $image_offset\0"					\
+	"nandboot=run add_default_bootargs;"				\
+		"nand read $loadaddr $image_offset $image_size;"	\
+		"bootm\0"						\
+	"add_default_bootargs=setenv bootargs $bootargs"		\
+		" console=ttyS0,$baudrate\0"				\
+
+/* FIT support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
+
+/* Open Firmware flat tree */
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_HAVE_ARM_SECURE
+
+/* Memory Size & Mapping */
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SDRAM0_BASE
+
+#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE >= CONFIG_SDRAM1_BASE
+/* Thre is no memory hole */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_SIZE	(CONFIG_SDRAM0_SIZE + CONFIG_SDRAM1_SIZE)
+#else
+#define CONFIG_NR_DRAM_BANKS		2
+#define CONFIG_SYS_SDRAM_SIZE	(CONFIG_SDRAM0_SIZE)
+#endif
+
+#define CONFIG_SYS_TEXT_BASE		0x84000000
+
+#if defined(CONFIG_SPL_BUILD)
+#define CONFIG_BOARD_POSTCLK_INIT
+#else
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#define CONFIG_SYS_SPL_MALLOC_START	(0x0ff00000)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	(0x00004000)
+
+#define CONFIG_SYS_INIT_SP_ADDR		(0x0ff08000)
+
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_NAND_SUPPORT
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT	/* for mem_malloc_init */
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+
+#define CONFIG_SPL_BOARD_INIT
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS		0x10000
+
+#endif /* __CONFIG_UNIPHIER_COMMON_H__ */
diff --git a/include/configs/vct.h b/include/configs/vct.h
index 5ab4de3..217ba2f 100644
--- a/include/configs/vct.h
+++ b/include/configs/vct.h
@@ -296,7 +296,6 @@ int vct_gpio_get(int pin);
 #undef CONFIG_CMD_BEDBUG
 #undef CONFIG_CMD_CACHE
 #undef CONFIG_CMD_CONSOLE
-#undef CONFIG_CMD_CRC32
 #undef CONFIG_CMD_DHCP
 #undef CONFIG_CMD_EEPROM
 #undef CONFIG_CMD_EEPROM
diff --git a/include/configs/venice2.h b/include/configs/venice2.h
index 6d4e999..6897aa8 100644
--- a/include/configs/venice2.h
+++ b/include/configs/venice2.h
@@ -12,11 +12,6 @@
 
 #include "tegra124-common.h"
 
-/* Enable fdt support for Venice2. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra124-venice2
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* High-level configuration options */
 #define V_PROMPT			"Tegra124 (Venice2) # "
 #define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Venice2"
diff --git a/include/configs/ventana.h b/include/configs/ventana.h
index edf3720..f195f8a 100644
--- a/include/configs/ventana.h
+++ b/include/configs/ventana.h
@@ -11,11 +11,6 @@
 #include <linux/sizes.h>
 #include "tegra20-common.h"
 
-/* Enable fdt support for Ventana. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra20-ventana
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* High-level configuration options */
 #define V_PROMPT		"Tegra20 (Ventana) # "
 #define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Ventana"
diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h
index 0897932..f3af971 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -51,7 +51,6 @@
 /* Flat Device Tree Definitions */
 #define CONFIG_OF_LIBFDT
 
-#define CONFIG_DEFAULT_DEVICE_TREE	vexpress64
 
 /* SMP Spin Table Definitions */
 #ifdef CONFIG_BASE_FVP
diff --git a/include/configs/vision2.h b/include/configs/vision2.h
index 6891bf8..3f35076 100644
--- a/include/configs/vision2.h
+++ b/include/configs/vision2.h
@@ -57,11 +57,11 @@
  * Use gpio 4 pin 25 as chip select for SPI flash
  * This corresponds to gpio 121
  */
-#define CONFIG_SF_DEFAULT_CS	(1 | (121 << 8))
+#define CONFIG_SF_DEFAULT_CS	 1
 #define CONFIG_SF_DEFAULT_MODE   SPI_MODE_0
 #define CONFIG_SF_DEFAULT_SPEED  25000000
 
-#define CONFIG_ENV_SPI_CS	(1 | (121 << 8))
+#define CONFIG_ENV_SPI_CS	CONFIG_SF_DEFAULT_CS
 #define CONFIG_ENV_SPI_BUS      0
 #define CONFIG_ENV_SPI_MAX_HZ	25000000
 #define CONFIG_ENV_SPI_MODE	SPI_MODE_0
diff --git a/include/configs/whistler.h b/include/configs/whistler.h
index 9e09f03..10e70d2 100644
--- a/include/configs/whistler.h
+++ b/include/configs/whistler.h
@@ -11,11 +11,6 @@
 #include <linux/sizes.h>
 #include "tegra20-common.h"
 
-/* Enable fdt support for Whistler. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra20-whistler
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* High-level configuration options */
 #define V_PROMPT		"Tegra20 (Whistler) # "
 #define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Whistler"
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 875cb43..0b4dd66 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -227,8 +227,6 @@
 #define CONFIG_IMAGE_FORMAT_LEGACY /* enable also legacy image format */
 
 /* FDT support */
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
 #define CONFIG_DISPLAY_BOARDINFO_LATE
 
 /* RSA support */
@@ -273,18 +271,13 @@
 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION    1
 #define CONFIG_SPL_LIBDISK_SUPPORT
 #define CONFIG_SPL_FAT_SUPPORT
-#if defined(CONFIG_OF_CONTROL) && defined(CONFIG_OF_SEPARATE)
-# define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME     "u-boot-dtb.img"
-#else
-# define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME     "u-boot.img"
-#endif
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME     "u-boot-dtb.img"
 #endif
 
 /* Disable dcache for SPL just for sure */
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_DCACHE_OFF
 #undef CONFIG_FPGA
-#undef CONFIG_OF_CONTROL
 #endif
 
 /* Address in RAM where the parameters must be copied by SPL. */
@@ -303,9 +296,7 @@
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
-#define CONFIG_SPL_SPI_BUS	0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x100000
-#define CONFIG_SPL_SPI_CS	0
 #endif
 
 /* for booting directly linux */
diff --git a/include/configs/zynq_microzed.h b/include/configs/zynq_microzed.h
index b0328a2..549a664 100644
--- a/include/configs/zynq_microzed.h
+++ b/include/configs/zynq_microzed.h
@@ -19,7 +19,6 @@
 #define CONFIG_SYS_NO_FLASH
 
 #define CONFIG_ZYNQ_SDHCI0
-#define CONFIG_DEFAULT_DEVICE_TREE	zynq-microzed
 
 #include <configs/zynq-common.h>
 
diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h
index 291a5fe..b659054 100644
--- a/include/configs/zynq_zc70x.h
+++ b/include/configs/zynq_zc70x.h
@@ -23,7 +23,6 @@
 #define CONFIG_ZYNQ_I2C0
 #define CONFIG_ZYNQ_EEPROM
 #define CONFIG_ZYNQ_BOOT_FREEBSD
-#define CONFIG_DEFAULT_DEVICE_TREE	zynq-zc702
 
 #include <configs/zynq-common.h>
 
diff --git a/include/configs/zynq_zc770.h b/include/configs/zynq_zc770.h
index 8aa96e7..16b9047 100644
--- a/include/configs/zynq_zc770.h
+++ b/include/configs/zynq_zc770.h
@@ -20,18 +20,15 @@
 # define CONFIG_ZYNQ_GEM_PHY_ADDR0	7
 # define CONFIG_ZYNQ_SDHCI0
 # define CONFIG_ZYNQ_SPI
-# define CONFIG_DEFAULT_DEVICE_TREE	zynq-zc770-xm010
 
 #elif defined(CONFIG_ZC770_XM012)
 # define CONFIG_ZYNQ_SERIAL_UART1
 # undef CONFIG_SYS_NO_FLASH
-# define CONFIG_DEFAULT_DEVICE_TREE	zynq-zc770-xm012
 
 #elif defined(CONFIG_ZC770_XM013)
 # define CONFIG_ZYNQ_SERIAL_UART0
 # define CONFIG_ZYNQ_GEM1
 # define CONFIG_ZYNQ_GEM_PHY_ADDR1	7
-# define CONFIG_DEFAULT_DEVICE_TREE	zynq-zc770-xm013
 
 #else
 # define CONFIG_ZYNQ_SERIAL_UART0
diff --git a/include/configs/zynq_zed.h b/include/configs/zynq_zed.h
index ce17d40..946de95 100644
--- a/include/configs/zynq_zed.h
+++ b/include/configs/zynq_zed.h
@@ -21,7 +21,6 @@
 #define CONFIG_ZYNQ_USB
 #define CONFIG_ZYNQ_SDHCI0
 #define CONFIG_ZYNQ_BOOT_FREEBSD
-#define CONFIG_DEFAULT_DEVICE_TREE	zynq-zed
 
 #include <configs/zynq-common.h>
 
diff --git a/include/fb_mmc.h b/include/fb_mmc.h
new file mode 100644
index 0000000..1ad1d13
--- /dev/null
+++ b/include/fb_mmc.h
@@ -0,0 +1,8 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+void fb_mmc_flash_write(const char *cmd, void *download_buffer,
+			unsigned int download_bytes, char *response);
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 1bda686..c3d1fbc 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -133,6 +133,18 @@ static inline int fdt_status_fail_by_alias(void *fdt, const char *alias)
 	return fdt_set_status_by_alias(fdt, alias, FDT_STATUS_FAIL, 0);
 }
 
+/* Helper to read a big number; size is in cells (not bytes) */
+static inline u64 of_read_number(const fdt32_t *cell, int size)
+{
+	u64 r = 0;
+	while (size--)
+		r = (r << 32) | fdt32_to_cpu(*(cell++));
+	return r;
+}
+
+void of_bus_default_count_cells(void *blob, int parentoffset,
+					int *addrc, int *sizec);
+
 #endif /* ifdef CONFIG_OF_LIBFDT */
 
 #ifdef USE_HOSTCC
diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h
index 5c49b22..675557a 100644
--- a/include/fsl_ddr.h
+++ b/include/fsl_ddr.h
@@ -15,6 +15,11 @@
 
 #include <common_timing_params.h>
 
+#ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
+/* All controllers are for main memory */
+#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS	CONFIG_NUM_DDR_CONTROLLERS
+#endif
+
 #ifdef CONFIG_SYS_FSL_DDR_LE
 #define ddr_in32(a)	in_le32(a)
 #define ddr_out32(a, v)	out_le32(a, v)
@@ -57,6 +62,13 @@ typedef struct {
 	memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS];
 	common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS];
 	fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS];
+	unsigned int first_ctrl;
+	unsigned int num_ctrls;
+	unsigned long long mem_base;
+	unsigned int dimm_slots_per_ctrl;
+	int (*board_need_mem_reset)(void);
+	void (*board_mem_reset)(void);
+	void (*board_mem_de_reset)(void);
 } fsl_ddr_info_t;
 
 /* Compute steps */
@@ -72,7 +84,6 @@ typedef struct {
 unsigned long long
 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 				       unsigned int size_only);
-
 const char *step_to_string(unsigned int step);
 
 unsigned int compute_fsl_memctl_config_regs(const memctl_options_t *popts,
@@ -102,7 +113,7 @@ void fsl_ddr_set_lawbar(
 int fsl_ddr_interactive_env_var_exists(void);
 unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set);
 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
-			   unsigned int ctrl_num);
+		     unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
 unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr);
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index 987119b..5b03c14 100644
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -51,7 +51,6 @@ typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
 #define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR2
 #endif
 #elif defined(CONFIG_SYS_FSL_DDR3)
-#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(3)	/* FIXME */
 typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
 #ifndef CONFIG_FSL_SDRAM_TYPE
 #define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR3
@@ -352,7 +351,6 @@ typedef struct memctl_options_s {
 	unsigned int twot_en;
 	unsigned int threet_en;
 	unsigned int bstopre;
-	unsigned int tcke_clock_pulse_width_ps;	/* tCKE */
 	unsigned int tfaw_window_four_activates_ps;	/* tFAW --  FOUR_ACT */
 
 	/* Rtt impedance */
@@ -379,12 +377,20 @@ typedef struct memctl_options_s {
 	unsigned int trwt;			/* read-to-write turnaround */
 } memctl_options_t;
 
-extern phys_size_t fsl_ddr_sdram(void);
-extern phys_size_t fsl_ddr_sdram_size(void);
+phys_size_t fsl_ddr_sdram(void);
+phys_size_t fsl_ddr_sdram_size(void);
+phys_size_t fsl_other_ddr_sdram(unsigned long long base,
+				unsigned int first_ctrl,
+				unsigned int num_ctrls,
+				unsigned int dimm_slots_per_ctrl,
+				int (*board_need_reset)(void),
+				void (*board_reset)(void),
+				void (*board_de_reset)(void));
 extern int fsl_use_spd(void);
-extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
-					unsigned int ctrl_num, int step);
+void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+			     unsigned int ctrl_num, int step);
 u32 fsl_ddr_get_intl3r(void);
+void print_ddr_info(unsigned int start_ctrl);
 
 static void __board_assert_mem_reset(void)
 {
diff --git a/include/linker_lists.h b/include/linker_lists.h
index 557e627..507d61b 100644
--- a/include/linker_lists.h
+++ b/include/linker_lists.h
@@ -28,11 +28,11 @@
  * together. Assuming _list and _entry are the list and entry names,
  * then the corresponding input section name is
  *
- *   _u_boot_list + _2_ + @_list + _2_ + @_entry
+ *   .u_boot_list_ + 2_ + @_list + _2_ + @_entry
  *
  * and the C variable name is
  *
- *   .u_boot_list_ + 2_ + @_list + _2_ + @_entry
+ *   _u_boot_list + _2_ + @_list + _2_ + @_entry
  *
  * This ensures uniqueness for both input section and C variable name.
  *
diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h
index 02ae99e..e057bd2 100644
--- a/include/linux/compiler-gcc.h
+++ b/include/linux/compiler-gcc.h
@@ -64,8 +64,12 @@
 #endif
 
 #define __deprecated			__attribute__((deprecated))
+#ifndef __packed
 #define __packed			__attribute__((packed))
+#endif
+#ifndef __weak
 #define __weak				__attribute__((weak))
+#endif
 
 /*
  * it doesn't make sense on ARM (currently the only user of __naked) to trace
@@ -91,8 +95,12 @@
  * would be.
  * [...]
  */
+#ifndef __pure
 #define __pure				__attribute__((pure))
+#endif
+#ifndef __aligned
 #define __aligned(x)			__attribute__((aligned(x)))
+#endif
 #define __printf(a, b)			__attribute__((format(printf, a, b)))
 #define __scanf(a, b)			__attribute__((format(scanf, a, b)))
 #define  noinline			__attribute__((noinline))
@@ -115,4 +123,6 @@
  */
 #define uninitialized_var(x) x = x
 
+#ifndef __always_inline
 #define __always_inline		inline __attribute__((always_inline))
+#endif
diff --git a/include/pci.h b/include/pci.h
index 461f17c..2ff7365 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -659,6 +659,13 @@ extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
 extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos,
 			int cap);
 
+#ifdef CONFIG_PCI_FIXUP_DEV
+extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
+				unsigned short vendor,
+				unsigned short device,
+				unsigned short class);
+#endif
+
 const char * pci_class_str(u8 class);
 int pci_last_busno(void);
 
diff --git a/include/sata.h b/include/sata.h
index c95dc56..38f4b4a 100644
--- a/include/sata.h
+++ b/include/sata.h
@@ -9,6 +9,7 @@ ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer);
 
 int sata_initialize(void);
 int __sata_initialize(void);
+int sata_port_status(int dev, int port);
 
 extern block_dev_desc_t sata_dev_desc[];
 
diff --git a/include/spi.h b/include/spi.h
index ffd6647..b673be2 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -30,24 +30,24 @@
 #define SPI_XFER_MMAP		0x08	/* Memory Mapped start */
 #define SPI_XFER_MMAP_END	0x10	/* Memory Mapped End */
 #define SPI_XFER_ONCE		(SPI_XFER_BEGIN | SPI_XFER_END)
-#define SPI_XFER_U_PAGE		(1 << 5)
+#define SPI_XFER_U_PAGE	(1 << 5)
 
 /* SPI TX operation modes */
-#define SPI_OPM_TX_QPP		1 << 0
+#define SPI_OPM_TX_QPP		(1 << 0)
 
 /* SPI RX operation modes */
-#define SPI_OPM_RX_AS		1 << 0
-#define SPI_OPM_RX_DOUT		1 << 1
-#define SPI_OPM_RX_DIO		1 << 2
-#define SPI_OPM_RX_QOF		1 << 3
-#define SPI_OPM_RX_QIOF		1 << 4
-#define SPI_OPM_RX_EXTN		SPI_OPM_RX_AS | SPI_OPM_RX_DOUT | \
+#define SPI_OPM_RX_AS		(1 << 0)
+#define SPI_OPM_RX_DOUT	(1 << 1)
+#define SPI_OPM_RX_DIO		(1 << 2)
+#define SPI_OPM_RX_QOF		(1 << 3)
+#define SPI_OPM_RX_QIOF	(1 << 4)
+#define SPI_OPM_RX_EXTN	(SPI_OPM_RX_AS | SPI_OPM_RX_DOUT | \
 				SPI_OPM_RX_DIO | SPI_OPM_RX_QOF | \
-				SPI_OPM_RX_QIOF
+				SPI_OPM_RX_QIOF)
 
-/* SPI bus connection options */
-#define SPI_CONN_DUAL_SHARED	1 << 0
-#define SPI_CONN_DUAL_SEPARATED	1 << 1
+/* SPI bus connection options - see enum spi_dual_flash */
+#define SPI_CONN_DUAL_SHARED		(1 << 0)
+#define SPI_CONN_DUAL_SEPARATED	(1 << 1)
 
 /* Header byte that marks the start of the message */
 #define SPI_PREAMBLE_END_BYTE	0xec
diff --git a/include/spi_flash.h b/include/spi_flash.h
index 2db53c7..408a5b4 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -19,6 +19,19 @@
 #include <linux/types.h>
 #include <linux/compiler.h>
 
+#ifndef CONFIG_SF_DEFAULT_SPEED
+# define CONFIG_SF_DEFAULT_SPEED	1000000
+#endif
+#ifndef CONFIG_SF_DEFAULT_MODE
+# define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
+#endif
+#ifndef CONFIG_SF_DEFAULT_CS
+# define CONFIG_SF_DEFAULT_CS		0
+#endif
+#ifndef CONFIG_SF_DEFAULT_BUS
+# define CONFIG_SF_DEFAULT_BUS		0
+#endif
+
 /* sf param flags */
 #define SECT_4K		1 << 1
 #define SECT_32K	1 << 2
author	Minkyu Kang <mk7.kang@samsung.com>	2014-10-07 19:14:03 +0900
committer	Minkyu Kang <mk7.kang@samsung.com>	2014-10-07 19:14:03 +0900
commit	3cc83f9d08a80fddf4c1e8e766eff8273f30814c (patch)
tree	831246a1b77d26d0296a84c90684e0fee0368737 /include
parent	64f41212d880f3d00c6994d973aadeec5bda1b65 (diff)
parent	6dd0e7c00bfa5ce861a72b8e4a3ef9e787306125 (diff)
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