Merge git://www.denx.de/git/u-boot into uboot

62 files changed, 2247 insertions, 645 deletions

diff --git a/include/asm-i386/zimage.h b/include/asm-i386/zimage.h
index c7103b1..b6266e4 100644
--- a/include/asm-i386/zimage.h
+++ b/include/asm-i386/zimage.h
@@ -70,6 +70,5 @@ void *load_zimage(char *image, unsigned long kernel_size,
 		  int auto_boot);
 
 void boot_zimage(void *setup_base);
-image_header_t *fake_zimage_header(image_header_t *hdr, void *ptr, int size);
 
 #endif
diff --git a/include/asm-mips/asm.h b/include/asm-mips/asm.h
new file mode 100644
index 0000000..608cfcf
--- /dev/null
+++ b/include/asm-mips/asm.h
@@ -0,0 +1,409 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
+ * Copyright (C) 1999 by Silicon Graphics, Inc.
+ * Copyright (C) 2001 MIPS Technologies, Inc.
+ * Copyright (C) 2002  Maciej W. Rozycki
+ *
+ * Some useful macros for MIPS assembler code
+ *
+ * Some of the routines below contain useless nops that will be optimized
+ * away by gas in -O mode. These nops are however required to fill delay
+ * slots in noreorder mode.
+ */
+#ifndef __ASM_ASM_H
+#define __ASM_ASM_H
+
+#include <asm/sgidefs.h>
+
+#ifndef CAT
+#ifdef __STDC__
+#define __CAT(str1, str2) str1##str2
+#else
+#define __CAT(str1, str2) str1/**/str2
+#endif
+#define CAT(str1, str2) __CAT(str1, str2)
+#endif
+
+/*
+ * PIC specific declarations
+ * Not used for the kernel but here seems to be the right place.
+ */
+#ifdef __PIC__
+#define CPRESTORE(register)                             \
+		.cprestore register
+#define CPADD(register)                                 \
+		.cpadd	register
+#define CPLOAD(register)                                \
+		.cpload	register
+#else
+#define CPRESTORE(register)
+#define CPADD(register)
+#define CPLOAD(register)
+#endif
+
+/*
+ * LEAF - declare leaf routine
+ */
+#define	LEAF(symbol)                                    \
+		.globl	symbol;                         \
+		.align	2;                              \
+		.type	symbol, @function;              \
+		.ent	symbol, 0;                      \
+symbol:		.frame	sp, 0, ra
+
+/*
+ * NESTED - declare nested routine entry point
+ */
+#define	NESTED(symbol, framesize, rpc)                  \
+		.globl	symbol;                         \
+		.align	2;                              \
+		.type	symbol, @function;              \
+		.ent	symbol, 0;                       \
+symbol:		.frame	sp, framesize, rpc
+
+/*
+ * END - mark end of function
+ */
+#define	END(function)                                   \
+		.end	function;		        \
+		.size	function, .-function
+
+/*
+ * EXPORT - export definition of symbol
+ */
+#define EXPORT(symbol)					\
+		.globl	symbol;                         \
+symbol:
+
+/*
+ * FEXPORT - export definition of a function symbol
+ */
+#define FEXPORT(symbol)					\
+		.globl	symbol;				\
+		.type	symbol, @function;		\
+symbol:
+
+/*
+ * ABS - export absolute symbol
+ */
+#define	ABS(symbol,value)                               \
+		.globl	symbol;                         \
+symbol		=	value
+
+#define	PANIC(msg)                                      \
+		.set	push;				\
+		.set	reorder;                        \
+		PTR_LA	a0, 8f;                          \
+		jal	panic;                          \
+9:		b	9b;                             \
+		.set	pop;				\
+		TEXT(msg)
+
+/*
+ * Print formatted string
+ */
+#ifdef CONFIG_PRINTK
+#define PRINT(string)                                   \
+		.set	push;				\
+		.set	reorder;                        \
+		PTR_LA	a0, 8f;                          \
+		jal	printk;                         \
+		.set	pop;				\
+		TEXT(string)
+#else
+#define PRINT(string)
+#endif
+
+#define	TEXT(msg)                                       \
+		.pushsection .data;			\
+8:		.asciiz	msg;                            \
+		.popsection;
+
+/*
+ * Build text tables
+ */
+#define TTABLE(string)                                  \
+		.pushsection .text;			\
+		.word	1f;                             \
+		.popsection				\
+		.pushsection .data;			\
+1:		.asciiz	string;                         \
+		.popsection
+
+/*
+ * MIPS IV pref instruction.
+ * Use with .set noreorder only!
+ *
+ * MIPS IV implementations are free to treat this as a nop.  The R5000
+ * is one of them.  So we should have an option not to use this instruction.
+ */
+#ifdef CONFIG_CPU_HAS_PREFETCH
+
+#define PREF(hint,addr)                                 \
+		.set	push;				\
+		.set	mips4;				\
+		pref	hint, addr;			\
+		.set	pop
+
+#define PREFX(hint,addr)                                \
+		.set	push;				\
+		.set	mips4;				\
+		prefx	hint, addr;			\
+		.set	pop
+
+#else /* !CONFIG_CPU_HAS_PREFETCH */
+
+#define PREF(hint, addr)
+#define PREFX(hint, addr)
+
+#endif /* !CONFIG_CPU_HAS_PREFETCH */
+
+/*
+ * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
+ */
+#if (_MIPS_ISA == _MIPS_ISA_MIPS1)
+#define MOVN(rd, rs, rt)                                \
+		.set	push;				\
+		.set	reorder;			\
+		beqz	rt, 9f;                         \
+		move	rd, rs;                         \
+		.set	pop;				\
+9:
+#define MOVZ(rd, rs, rt)                                \
+		.set	push;				\
+		.set	reorder;			\
+		bnez	rt, 9f;                         \
+		move	rd, rs;                         \
+		.set	pop;				\
+9:
+#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
+#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
+#define MOVN(rd, rs, rt)                                \
+		.set	push;				\
+		.set	noreorder;			\
+		bnezl	rt, 9f;                         \
+		 move	rd, rs;                         \
+		.set	pop;				\
+9:
+#define MOVZ(rd, rs, rt)                                \
+		.set	push;				\
+		.set	noreorder;			\
+		beqzl	rt, 9f;                         \
+		 move	rd, rs;                         \
+		.set	pop;				\
+9:
+#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
+#if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
+    (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
+#define MOVN(rd, rs, rt)                                \
+		movn	rd, rs, rt
+#define MOVZ(rd, rs, rt)                                \
+		movz	rd, rs, rt
+#endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
+
+/*
+ * Stack alignment
+ */
+#if (_MIPS_SIM == _MIPS_SIM_ABI32)
+#define ALSZ	7
+#define ALMASK	~7
+#endif
+#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
+#define ALSZ	15
+#define ALMASK	~15
+#endif
+
+/*
+ * Macros to handle different pointer/register sizes for 32/64-bit code
+ */
+
+/*
+ * Size of a register
+ */
+#ifdef __mips64
+#define SZREG	8
+#else
+#define SZREG	4
+#endif
+
+/*
+ * Use the following macros in assemblercode to load/store registers,
+ * pointers etc.
+ */
+#if (_MIPS_SIM == _MIPS_SIM_ABI32)
+#define REG_S		sw
+#define REG_L		lw
+#define REG_SUBU	subu
+#define REG_ADDU	addu
+#endif
+#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
+#define REG_S		sd
+#define REG_L		ld
+#define REG_SUBU	dsubu
+#define REG_ADDU	daddu
+#endif
+
+/*
+ * How to add/sub/load/store/shift C int variables.
+ */
+#if (_MIPS_SZINT == 32)
+#define INT_ADD		add
+#define INT_ADDU	addu
+#define INT_ADDI	addi
+#define INT_ADDIU	addiu
+#define INT_SUB		sub
+#define INT_SUBU	subu
+#define INT_L		lw
+#define INT_S		sw
+#define INT_SLL		sll
+#define INT_SLLV	sllv
+#define INT_SRL		srl
+#define INT_SRLV	srlv
+#define INT_SRA		sra
+#define INT_SRAV	srav
+#endif
+
+#if (_MIPS_SZINT == 64)
+#define INT_ADD		dadd
+#define INT_ADDU	daddu
+#define INT_ADDI	daddi
+#define INT_ADDIU	daddiu
+#define INT_SUB		dsub
+#define INT_SUBU	dsubu
+#define INT_L		ld
+#define INT_S		sd
+#define INT_SLL		dsll
+#define INT_SLLV	dsllv
+#define INT_SRL		dsrl
+#define INT_SRLV	dsrlv
+#define INT_SRA		dsra
+#define INT_SRAV	dsrav
+#endif
+
+/*
+ * How to add/sub/load/store/shift C long variables.
+ */
+#if (_MIPS_SZLONG == 32)
+#define LONG_ADD	add
+#define LONG_ADDU	addu
+#define LONG_ADDI	addi
+#define LONG_ADDIU	addiu
+#define LONG_SUB	sub
+#define LONG_SUBU	subu
+#define LONG_L		lw
+#define LONG_S		sw
+#define LONG_SLL	sll
+#define LONG_SLLV	sllv
+#define LONG_SRL	srl
+#define LONG_SRLV	srlv
+#define LONG_SRA	sra
+#define LONG_SRAV	srav
+
+#define LONG		.word
+#define LONGSIZE	4
+#define LONGMASK	3
+#define LONGLOG		2
+#endif
+
+#if (_MIPS_SZLONG == 64)
+#define LONG_ADD	dadd
+#define LONG_ADDU	daddu
+#define LONG_ADDI	daddi
+#define LONG_ADDIU	daddiu
+#define LONG_SUB	dsub
+#define LONG_SUBU	dsubu
+#define LONG_L		ld
+#define LONG_S		sd
+#define LONG_SLL	dsll
+#define LONG_SLLV	dsllv
+#define LONG_SRL	dsrl
+#define LONG_SRLV	dsrlv
+#define LONG_SRA	dsra
+#define LONG_SRAV	dsrav
+
+#define LONG		.dword
+#define LONGSIZE	8
+#define LONGMASK	7
+#define LONGLOG		3
+#endif
+
+/*
+ * How to add/sub/load/store/shift pointers.
+ */
+#if (_MIPS_SZPTR == 32)
+#define PTR_ADD		add
+#define PTR_ADDU	addu
+#define PTR_ADDI	addi
+#define PTR_ADDIU	addiu
+#define PTR_SUB		sub
+#define PTR_SUBU	subu
+#define PTR_L		lw
+#define PTR_S		sw
+#define PTR_LA		la
+#define PTR_LI		li
+#define PTR_SLL		sll
+#define PTR_SLLV	sllv
+#define PTR_SRL		srl
+#define PTR_SRLV	srlv
+#define PTR_SRA		sra
+#define PTR_SRAV	srav
+
+#define PTR_SCALESHIFT	2
+
+#define PTR		.word
+#define PTRSIZE		4
+#define PTRLOG		2
+#endif
+
+#if (_MIPS_SZPTR == 64)
+#define PTR_ADD		dadd
+#define PTR_ADDU	daddu
+#define PTR_ADDI	daddi
+#define PTR_ADDIU	daddiu
+#define PTR_SUB		dsub
+#define PTR_SUBU	dsubu
+#define PTR_L		ld
+#define PTR_S		sd
+#define PTR_LA		dla
+#define PTR_LI		dli
+#define PTR_SLL		dsll
+#define PTR_SLLV	dsllv
+#define PTR_SRL		dsrl
+#define PTR_SRLV	dsrlv
+#define PTR_SRA		dsra
+#define PTR_SRAV	dsrav
+
+#define PTR_SCALESHIFT	3
+
+#define PTR		.dword
+#define PTRSIZE		8
+#define PTRLOG		3
+#endif
+
+/*
+ * Some cp0 registers were extended to 64bit for MIPS III.
+ */
+#if (_MIPS_SIM == _MIPS_SIM_ABI32)
+#define MFC0		mfc0
+#define MTC0		mtc0
+#endif
+#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
+#define MFC0		dmfc0
+#define MTC0		dmtc0
+#endif
+
+#define SSNOP		sll zero, zero, 1
+
+#ifdef CONFIG_SGI_IP28
+/* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
+#include <asm/cacheops.h>
+#define R10KCBARRIER(addr)  cache   Cache_Barrier, addr;
+#else
+#define R10KCBARRIER(addr)
+#endif
+
+#endif /* __ASM_ASM_H */
diff --git a/include/asm-mips/byteorder.h b/include/asm-mips/byteorder.h
index b9604cf..b5e685f 100644
--- a/include/asm-mips/byteorder.h
+++ b/include/asm-mips/byteorder.h
@@ -1,18 +1,62 @@
-/* $Id: byteorder.h,v 1.8 1998/11/02 09:29:32 ralf Exp $
- *
+/*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) by Ralf Baechle
+ * Copyright (C) 1996, 99, 2003 by Ralf Baechle
  */
-#ifndef _MIPS_BYTEORDER_H
-#define _MIPS_BYTEORDER_H
+#ifndef _ASM_BYTEORDER_H
+#define _ASM_BYTEORDER_H
 
 #include <asm/types.h>
 
 #ifdef __GNUC__
 
+#ifdef CONFIG_CPU_MIPSR2
+
+static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
+{
+	__asm__(
+	"	wsbh	%0, %1			\n"
+	: "=r" (x)
+	: "r" (x));
+
+	return x;
+}
+#define __arch__swab16(x)	___arch__swab16(x)
+
+static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
+{
+	__asm__(
+	"	wsbh	%0, %1			\n"
+	"	rotr	%0, %0, 16		\n"
+	: "=r" (x)
+	: "r" (x));
+
+	return x;
+}
+#define __arch__swab32(x)	___arch__swab32(x)
+
+#ifdef CONFIG_CPU_MIPS64_R2
+
+static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
+{
+	__asm__(
+	"	dsbh	%0, %1			\n"
+	"	dshd	%0, %0			\n"
+	"	drotr	%0, %0, 32		\n"
+	: "=r" (x)
+	: "r" (x));
+
+	return x;
+}
+
+#define __arch__swab64(x)	___arch__swab64(x)
+
+#endif /* CONFIG_CPU_MIPS64_R2 */
+
+#endif /* CONFIG_CPU_MIPSR2 */
+
 #if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
 #  define __BYTEORDER_HAS_U64__
 #  define __SWAB_64_THRU_32__
@@ -20,12 +64,12 @@
 
 #endif /* __GNUC__ */
 
-#if defined (__MIPSEB__)
+#if defined(__MIPSEB__)
 #  include <linux/byteorder/big_endian.h>
-#elif defined (__MIPSEL__)
+#elif defined(__MIPSEL__)
 #  include <linux/byteorder/little_endian.h>
 #else
 #  error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
 #endif
 
-#endif /* _MIPS_BYTEORDER_H */
+#endif /* _ASM_BYTEORDER_H */
diff --git a/include/asm-mips/cachectl.h b/include/asm-mips/cachectl.h
index 9cc2b87..f3ce721 100644
--- a/include/asm-mips/cachectl.h
+++ b/include/asm-mips/cachectl.h
@@ -1,10 +1,12 @@
 /*
- * cachectl.h -- defines for MIPS cache control system calls
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
  *
  * Copyright (C) 1994, 1995, 1996 by Ralf Baechle
  */
-#ifndef	__ASM_MIPS_CACHECTL
-#define	__ASM_MIPS_CACHECTL
+#ifndef	_ASM_CACHECTL
+#define	_ASM_CACHECTL
 
 /*
  * Options for cacheflush system call
@@ -21,4 +23,4 @@
 #define CACHEABLE	0	/* make pages cacheable */
 #define UNCACHEABLE	1	/* make pages uncacheable */
 
-#endif	/* __ASM_MIPS_CACHECTL */
+#endif	/* _ASM_CACHECTL */
diff --git a/include/asm-mips/cacheops.h b/include/asm-mips/cacheops.h
index 66b0b36..256ad2c 100644
--- a/include/asm-mips/cacheops.h
+++ b/include/asm-mips/cacheops.h
@@ -5,43 +5,81 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * (C) Copyright 1996, 1997 by Ralf Baechle
+ * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
+ * (C) Copyright 1999 Silicon Graphics, Inc.
  */
-#ifndef	__ASM_MIPS_CACHEOPS_H
-#define	__ASM_MIPS_CACHEOPS_H
+#ifndef	__ASM_CACHEOPS_H
+#define	__ASM_CACHEOPS_H
 
 /*
- * Cache Operations
+ * Cache Operations available on all MIPS processors with R4000-style caches
  */
 #define Index_Invalidate_I      0x00
 #define Index_Writeback_Inv_D   0x01
-#define Index_Invalidate_SI     0x02
-#define Index_Writeback_Inv_SD  0x03
 #define Index_Load_Tag_I	0x04
 #define Index_Load_Tag_D	0x05
-#define Index_Load_Tag_SI	0x06
-#define Index_Load_Tag_SD	0x07
 #define Index_Store_Tag_I	0x08
 #define Index_Store_Tag_D	0x09
+#if defined(CONFIG_CPU_LOONGSON2)
+#define Hit_Invalidate_I    	0x00
+#else
+#define Hit_Invalidate_I	0x10
+#endif
+#define Hit_Invalidate_D	0x11
+#define Hit_Writeback_Inv_D	0x15
+
+/*
+ * R4000-specific cacheops
+ */
+#define Create_Dirty_Excl_D	0x0d
+#define Fill			0x14
+#define Hit_Writeback_I		0x18
+#define Hit_Writeback_D		0x19
+
+/*
+ * R4000SC and R4400SC-specific cacheops
+ */
+#define Index_Invalidate_SI     0x02
+#define Index_Writeback_Inv_SD  0x03
+#define Index_Load_Tag_SI	0x06
+#define Index_Load_Tag_SD	0x07
 #define Index_Store_Tag_SI	0x0A
 #define Index_Store_Tag_SD	0x0B
-#define Create_Dirty_Excl_D	0x0d
 #define Create_Dirty_Excl_SD	0x0f
-#define Hit_Invalidate_I	0x10
-#define Hit_Invalidate_D	0x11
 #define Hit_Invalidate_SI	0x12
 #define Hit_Invalidate_SD	0x13
-#define Fill			0x14
-#define Hit_Writeback_Inv_D	0x15
-					/* 0x16 is unused */
 #define Hit_Writeback_Inv_SD	0x17
-#define Hit_Writeback_I		0x18
-#define Hit_Writeback_D		0x19
-					/* 0x1a is unused */
 #define Hit_Writeback_SD	0x1b
-					/* 0x1c is unused */
-					/* 0x1e is unused */
 #define Hit_Set_Virtual_SI	0x1e
 #define Hit_Set_Virtual_SD	0x1f
 
-#endif	/* __ASM_MIPS_CACHEOPS_H */
+/*
+ * R5000-specific cacheops
+ */
+#define R5K_Page_Invalidate_S	0x17
+
+/*
+ * RM7000-specific cacheops
+ */
+#define Page_Invalidate_T	0x16
+
+/*
+ * R10000-specific cacheops
+ *
+ * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
+ * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
+ */
+#define Index_Writeback_Inv_S	0x03
+#define Index_Load_Tag_S	0x07
+#define Index_Store_Tag_S	0x0B
+#define Hit_Invalidate_S	0x13
+#define Cache_Barrier		0x14
+#define Hit_Writeback_Inv_S	0x17
+#define Index_Load_Data_I	0x18
+#define Index_Load_Data_D	0x19
+#define Index_Load_Data_S	0x1b
+#define Index_Store_Data_I	0x1c
+#define Index_Store_Data_D	0x1d
+#define Index_Store_Data_S	0x1f
+
+#endif	/* __ASM_CACHEOPS_H */
diff --git a/include/asm-mips/isadep.h b/include/asm-mips/isadep.h
index 3cd1eb8..24c6cda 100644
--- a/include/asm-mips/isadep.h
+++ b/include/asm-mips/isadep.h
@@ -1,16 +1,15 @@
 /*
- * Various ISA level dependant constants.
+ * Various ISA level dependent constants.
  * Most of the following constants reflect the different layout
  * of Coprocessor 0 registers.
  *
  * Copyright (c) 1998 Harald Koerfgen
  */
-#include <linux/config.h>
 
 #ifndef __ASM_ISADEP_H
 #define __ASM_ISADEP_H
 
-#if defined(CONFIG_CPU_R3000)
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
 /*
  * R2000 or R3000
  */
diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h
index 6838aee..24858dd 100644
--- a/include/asm-mips/processor.h
+++ b/include/asm-mips/processor.h
@@ -4,9 +4,9 @@
  * for more details.
  *
  * Copyright (C) 1994 Waldorf GMBH
- * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001 Ralf Baechle
+ * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
  * Copyright (C) 1996 Paul M. Antoine
- * Copyright (C) 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  */
 #ifndef _ASM_PROCESSOR_H
 #define _ASM_PROCESSOR_H
@@ -15,92 +15,26 @@
 
 #include <asm/isadep.h>
 
-/*
- * Default implementation of macro that returns current
- * instruction pointer ("program counter").
- */
-#define current_text_addr() ({ __label__ _l; _l: &&_l;})
-
-#if !defined (_LANGUAGE_ASSEMBLY)
-#if 0
-#include <linux/threads.h>
-#endif
 #include <asm/cachectl.h>
 #include <asm/mipsregs.h>
 #include <asm/reg.h>
 #include <asm/system.h>
 
-struct mips_cpuinfo {
-	unsigned long udelay_val;
-	unsigned long *pgd_quick;
-	unsigned long *pte_quick;
-	unsigned long pgtable_cache_sz;
-};
-
-/*
- * System setup and hardware flags..
- * XXX: Should go into mips_cpuinfo.
- */
-extern void (*cpu_wait)(void);	/* only available on R4[26]00 and R3081 */
-extern void r3081_wait(void);
-extern void r4k_wait(void);
-extern char cyclecounter_available;	/* only available from R4000 upwards. */
-
-extern struct mips_cpuinfo boot_cpu_data;
-extern unsigned int vced_count, vcei_count;
-
-#ifdef CONFIG_SMP
-extern struct mips_cpuinfo cpu_data[];
-#define current_cpu_data cpu_data[smp_processor_id()]
-#else
-#define cpu_data &boot_cpu_data
-#define current_cpu_data boot_cpu_data
-#endif
-
-/*
- * Bus types (default is ISA, but people can check others with these..)
- * MCA_bus hardcoded to 0 for now.
- *
- * This needs to be extended since MIPS systems are being delivered with
- * numerous different types of bus systems.
- */
-extern int EISA_bus;
-#define MCA_bus 0
-#define MCA_bus__is_a_macro /* for versions in ksyms.c */
-
 /*
- * MIPS has no problems with write protection
+ * Return current * instruction pointer ("program counter").
  */
-#define wp_works_ok 1
-#define wp_works_ok__is_a_macro /* for versions in ksyms.c */
-
-/* Lazy FPU handling on uni-processor */
-extern struct task_struct *last_task_used_math;
+#define current_text_addr() ({ __label__ _l; _l: &&_l;})
 
 /*
- * User space process size: 2GB. This is hardcoded into a few places,
- * so don't change it unless you know what you are doing.  TASK_SIZE
- * for a 64 bit kernel expandable to 8192EB, of which the current MIPS
- * implementations will "only" be able to use 1TB ...
- */
-#define TASK_SIZE	(0x7fff8000UL)
-
-/* This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
+ * System setup and hardware flags..
  */
-#define TASK_UNMAPPED_BASE	(TASK_SIZE / 3)
+extern void (*cpu_wait)(void);
 
-/*
- * Size of io_bitmap in longwords: 32 is ports 0-0x3ff.
- */
-#define IO_BITMAP_SIZE	32
+extern unsigned int vced_count, vcei_count;
 
 #define NUM_FPU_REGS	32
 
-struct mips_fpu_hard_struct {
-	double fp_regs[NUM_FPU_REGS];
-	unsigned int control;
-};
+typedef __u64 fpureg_t;
 
 /*
  * It would be nice to add some more fields for emulator statistics, but there
@@ -108,25 +42,29 @@ struct mips_fpu_hard_struct {
  * be recalculated by hand.  So the additional information will be private to
  * the FPU emulator for now.  See asm-mips/fpu_emulator.h.
  */
-typedef u64 fpureg_t;
-struct mips_fpu_soft_struct {
-	fpureg_t	regs[NUM_FPU_REGS];
-	unsigned int	sr;
-};
 
-union mips_fpu_union {
-	struct mips_fpu_hard_struct hard;
-	struct mips_fpu_soft_struct soft;
+struct mips_fpu_struct {
+	fpureg_t	fpr[NUM_FPU_REGS];
+	unsigned int	fcr31;
 };
 
-#define INIT_FPU { \
-	{{0,},} \
-}
+#define NUM_DSP_REGS   6
+
+typedef __u32 dspreg_t;
+
+struct mips_dsp_state {
+	dspreg_t        dspr[NUM_DSP_REGS];
+	unsigned int    dspcontrol;
+};
 
 typedef struct {
 	unsigned long seg;
 } mm_segment_t;
 
+#define ARCH_MIN_TASKALIGN	8
+
+struct mips_abi;
+
 /*
  * If you change thread_struct remember to change the #defines below too!
  */
@@ -140,131 +78,36 @@ struct thread_struct {
 	unsigned long cp0_status;
 
 	/* Saved fpu/fpu emulator stuff. */
-	union mips_fpu_union fpu;
+	struct mips_fpu_struct fpu;
+#ifdef CONFIG_MIPS_MT_FPAFF
+	/* Emulated instruction count */
+	unsigned long emulated_fp;
+	/* Saved per-thread scheduler affinity mask */
+	cpumask_t user_cpus_allowed;
+#endif /* CONFIG_MIPS_MT_FPAFF */
+
+	/* Saved state of the DSP ASE, if available. */
+	struct mips_dsp_state dsp;
 
 	/* Other stuff associated with the thread. */
 	unsigned long cp0_badvaddr;	/* Last user fault */
 	unsigned long cp0_baduaddr;	/* Last kernel fault accessing USEG */
 	unsigned long error_code;
 	unsigned long trap_no;
-#define MF_FIXADE 1			/* Fix address errors in software */
-#define MF_LOGADE 2			/* Log address errors to syslog */
-	unsigned long mflags;
-	mm_segment_t current_ds;
 	unsigned long irix_trampoline;  /* Wheee... */
 	unsigned long irix_oldctx;
-
-	/*
-	 * These are really only needed if the full FPU emulator is configured.
-	 * Would be made conditional on MIPS_FPU_EMULATOR if it weren't for the
-	 * fact that having offset.h rebuilt differently for different config
-	 * options would be asking for trouble.
-	 *
-	 * Saved EPC during delay-slot emulation (see math-emu/cp1emu.c)
-	 */
-	unsigned long dsemul_epc;
-
-	/*
-	 * Pointer to instruction used to induce address error
-	 */
-	unsigned long dsemul_aerpc;
+	struct mips_abi *abi;
 };
 
-#endif /* !defined (_LANGUAGE_ASSEMBLY) */
-
-#define INIT_THREAD  { \
-	/* \
-	 * saved main processor registers \
-	 */ \
-	0, 0, 0, 0, 0, 0, 0, 0, \
-		       0, 0, 0, \
-	/* \
-	 * saved cp0 stuff \
-	 */ \
-	0, \
-	/* \
-	 * saved fpu/fpu emulator stuff \
-	 */ \
-	INIT_FPU, \
-	/* \
-	 * Other stuff associated with the process \
-	 */ \
-	0, 0, 0, 0, \
-	/* \
-	 * For now the default is to fix address errors \
-	 */ \
-	MF_FIXADE, { 0 }, 0, 0, \
-	/* \
-	 * dsemul_epc and dsemul_aerpc should never be used uninitialized, \
-	 * but... \
-	 */ \
-	0 ,0 \
-}
-
-#ifdef __KERNEL__
-
-#define KERNEL_STACK_SIZE 8192
-
-#if !defined (_LANGUAGE_ASSEMBLY)
+struct task_struct;
 
 /* Free all resources held by a thread. */
 #define release_thread(thread) do { } while(0)
 
-extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
-
-/* Copy and release all segment info associated with a VM */
-#define copy_segments(p, mm) do { } while(0)
-#define release_segments(mm) do { } while(0)
-
-/*
- * Return saved PC of a blocked thread.
- */
-extern inline unsigned long thread_saved_pc(struct thread_struct *t)
-{
-	extern void ret_from_fork(void);
-
-	/* New born processes are a special case */
-	if (t->reg31 == (unsigned long) ret_from_fork)
-		return t->reg31;
-
-	return ((unsigned long *)t->reg29)[10];
-}
-
-/*
- * Do necessary setup to start up a newly executed thread.
- */
-#define start_thread(regs, new_pc, new_sp) do {				\
-	/* New thread looses kernel privileges. */			\
-	regs->cp0_status = (regs->cp0_status & ~(ST0_CU0|ST0_KSU)) | KU_USER;\
-	regs->cp0_epc = new_pc;						\
-	regs->regs[29] = new_sp;					\
-	current->thread.current_ds = USER_DS;				\
-} while (0)
+/* Prepare to copy thread state - unlazy all lazy status */
+#define prepare_to_copy(tsk)	do { } while (0)
 
-unsigned long get_wchan(struct task_struct *p);
-
-#define __PT_REG(reg) ((long)&((struct pt_regs *)0)->reg - sizeof(struct pt_regs))
-#define __KSTK_TOS(tsk) ((unsigned long)(tsk) + KERNEL_STACK_SIZE - 32)
-#define KSTK_EIP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(cp0_epc)))
-#define KSTK_ESP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(regs[29])))
-
-/* Allocation and freeing of basic task resources. */
-/*
- * NOTE! The task struct and the stack go together
- */
-#define THREAD_SIZE (2*PAGE_SIZE)
-#define alloc_task_struct() \
-	((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
-#define free_task_struct(p)	free_pages((unsigned long)(p),1)
-#define get_task_struct(tsk)      atomic_inc(&virt_to_page(tsk)->count)
-
-#define init_task	(init_task_union.task)
-#define init_stack	(init_task_union.stack)
-
-#define cpu_relax()	do { } while (0)
-
-#endif /* !defined (_LANGUAGE_ASSEMBLY) */
-#endif /* __KERNEL__ */
+#define cpu_relax()	barrier()
 
 /*
  * Return_address is a replacement for __builtin_return_address(count)
@@ -280,4 +123,20 @@ unsigned long get_wchan(struct task_struct *p);
  */
 #define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
 
+#ifdef CONFIG_CPU_HAS_PREFETCH
+
+#define ARCH_HAS_PREFETCH
+
+static inline void prefetch(const void *addr)
+{
+	__asm__ __volatile__(
+	"	.set	mips4		\n"
+	"	pref	%0, (%1)	\n"
+	"	.set	mips0		\n"
+	:
+	: "i" (Pref_Load), "r" (addr));
+}
+
+#endif
+
 #endif /* _ASM_PROCESSOR_H */
diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h
index 2517adb..5659c0c 100644
--- a/include/asm-mips/ptrace.h
+++ b/include/asm-mips/ptrace.h
@@ -3,17 +3,12 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000 by Ralf Baechle
- *
- * Machine dependent structs and defines to help the user use
- * the ptrace system call.
+ * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  */
 #ifndef _ASM_PTRACE_H
 #define _ASM_PTRACE_H
 
-#include <asm/isadep.h>
-#include <linux/types.h>
-
 /* 0 - 31 are integer registers, 32 - 63 are fp registers.  */
 #define FPR_BASE	32
 #define PC		64
@@ -23,63 +18,69 @@
 #define MMLO		68
 #define FPC_CSR		69
 #define FPC_EIR		70
+#define DSP_BASE	71		/* 3 more hi / lo register pairs */
+#define DSP_CONTROL	77
+#define ACX		78
 
-#ifndef _LANGUAGE_ASSEMBLY
 /*
  * This struct defines the way the registers are stored on the stack during a
  * system call/exception. As usual the registers k0/k1 aren't being saved.
  */
 struct pt_regs {
+#ifdef CONFIG_32BIT
 	/* Pad bytes for argument save space on the stack. */
 	unsigned long pad0[6];
+#endif
 
 	/* Saved main processor registers. */
 	unsigned long regs[32];
 
-	/* Other saved registers. */
-	unsigned long lo;
+	/* Saved special registers. */
+	unsigned long cp0_status;
 	unsigned long hi;
-
-	/*
-	 * saved cp0 registers
-	 */
-	unsigned long cp0_epc;
+	unsigned long lo;
+#ifdef CONFIG_CPU_HAS_SMARTMIPS
+	unsigned long acx;
+#endif
 	unsigned long cp0_badvaddr;
-	unsigned long cp0_status;
 	unsigned long cp0_cause;
-};
-
-#endif /* !(_LANGUAGE_ASSEMBLY) */
+	unsigned long cp0_epc;
+#ifdef CONFIG_MIPS_MT_SMTC
+	unsigned long cp0_tcstatus;
+#endif /* CONFIG_MIPS_MT_SMTC */
+} __attribute__ ((aligned (8)));
 
 /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
-/* #define PTRACE_GETREGS		12 */
-/* #define PTRACE_SETREGS		13 */
-/* #define PTRACE_GETFPREGS		14 */
-/* #define PTRACE_SETFPREGS		15 */
+#define PTRACE_GETREGS		12
+#define PTRACE_SETREGS		13
+#define PTRACE_GETFPREGS		14
+#define PTRACE_SETFPREGS		15
 /* #define PTRACE_GETFPXREGS		18 */
 /* #define PTRACE_SETFPXREGS		19 */
 
-#define PTRACE_SETOPTIONS	21
+#define PTRACE_OLDSETOPTIONS	21
 
-/* options set using PTRACE_SETOPTIONS */
-#define PTRACE_O_TRACESYSGOOD	0x00000001
+#define PTRACE_GET_THREAD_AREA	25
+#define PTRACE_SET_THREAD_AREA	26
 
-#if 0 /* def _LANGUAGE_ASSEMBLY */
-#include <asm/offset.h>
-#endif
+/* Calls to trace a 64bit program from a 32bit program.  */
+#define PTRACE_PEEKTEXT_3264	0xc0
+#define PTRACE_PEEKDATA_3264	0xc1
+#define PTRACE_POKETEXT_3264	0xc2
+#define PTRACE_POKEDATA_3264	0xc3
+#define PTRACE_GET_THREAD_AREA_3264	0xc4
 
 #ifdef __KERNEL__
 
-#ifndef _LANGUAGE_ASSEMBLY
+#include <asm/isadep.h>
+
 /*
  * Does the process account for user or for system time?
  */
 #define user_mode(regs) (((regs)->cp0_status & KU_MASK) == KU_USER)
 
 #define instruction_pointer(regs) ((regs)->cp0_epc)
-
-extern void show_regs(struct pt_regs *);
-#endif /* !(_LANGUAGE_ASSEMBLY) */
+#define profile_pc(regs) instruction_pointer(regs)
 
 #endif
 
diff --git a/include/asm-mips/reboot.h b/include/asm-mips/reboot.h
new file mode 100644
index 0000000..978d206
--- /dev/null
+++ b/include/asm-mips/reboot.h
@@ -0,0 +1,14 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997, 1999, 2001, 06 by Ralf Baechle
+ * Copyright (C) 2001 MIPS Technologies, Inc.
+ */
+#ifndef _ASM_REBOOT_H
+#define _ASM_REBOOT_H
+
+extern void _machine_restart(void);
+
+#endif /* _ASM_REBOOT_H */
diff --git a/include/asm-mips/reg.h b/include/asm-mips/reg.h
index 35505b7..fc6bc0c 100644
--- a/include/asm-mips/reg.h
+++ b/include/asm-mips/reg.h
@@ -7,48 +7,50 @@
  * for more details.
  *
  * Copyright (C) 1995, 1999 by Ralf Baechle
+ * Copyright (C) 1995, 1999 Silicon Graphics
  */
 #ifndef __ASM_MIPS_REG_H
 #define __ASM_MIPS_REG_H
 
-/*
- * This defines/structures correspond to the register layout on stack -
- * if the order here is changed, it needs to be updated in
- * include/asm-mips/stackframe.h
- */
-#define EF_REG0			6
-#define EF_REG1			7
-#define EF_REG2			8
-#define EF_REG3			9
-#define EF_REG4			10
-#define EF_REG5			11
-#define EF_REG6			12
-#define EF_REG7			13
-#define EF_REG8			14
-#define EF_REG9			15
-#define EF_REG10		16
-#define EF_REG11		17
-#define EF_REG12		18
-#define EF_REG13		19
-#define EF_REG14		20
-#define EF_REG15		21
-#define EF_REG16		22
-#define EF_REG17		23
-#define EF_REG18		24
-#define EF_REG19		25
-#define EF_REG20		26
-#define EF_REG21		27
-#define EF_REG22		28
-#define EF_REG23		29
-#define EF_REG24		30
-#define EF_REG25		31
+#if defined(CONFIG_32BIT) || defined(WANT_COMPAT_REG_H)
+
+#define EF_R0			6
+#define EF_R1			7
+#define EF_R2			8
+#define EF_R3			9
+#define EF_R4			10
+#define EF_R5			11
+#define EF_R6			12
+#define EF_R7			13
+#define EF_R8			14
+#define EF_R9			15
+#define EF_R10			16
+#define EF_R11			17
+#define EF_R12			18
+#define EF_R13			19
+#define EF_R14			20
+#define EF_R15			21
+#define EF_R16			22
+#define EF_R17			23
+#define EF_R18			24
+#define EF_R19			25
+#define EF_R20			26
+#define EF_R21			27
+#define EF_R22			28
+#define EF_R23			29
+#define EF_R24			30
+#define EF_R25			31
+
 /*
  * k0/k1 unsaved
  */
-#define EF_REG28		34
-#define EF_REG29		35
-#define EF_REG30		36
-#define EF_REG31		37
+#define EF_R26			32
+#define EF_R27			33
+
+#define EF_R28			34
+#define EF_R29			35
+#define EF_R30			36
+#define EF_R31			37
 
 /*
  * Saved special registers
@@ -59,8 +61,66 @@
 #define EF_CP0_EPC		40
 #define EF_CP0_BADVADDR		41
 #define EF_CP0_STATUS		42
-#define EF_CP0_CAUSE		44
+#define EF_CP0_CAUSE		43
+#define EF_UNUSED0		44
+
+#define EF_SIZE			180
+
+#endif
+
+#ifdef CONFIG_64BIT
+
+#define EF_R0			 0
+#define EF_R1			 1
+#define EF_R2			 2
+#define EF_R3			 3
+#define EF_R4			 4
+#define EF_R5			 5
+#define EF_R6			 6
+#define EF_R7			 7
+#define EF_R8			 8
+#define EF_R9			 9
+#define EF_R10			10
+#define EF_R11			11
+#define EF_R12			12
+#define EF_R13			13
+#define EF_R14			14
+#define EF_R15			15
+#define EF_R16			16
+#define EF_R17			17
+#define EF_R18			18
+#define EF_R19			19
+#define EF_R20			20
+#define EF_R21			21
+#define EF_R22			22
+#define EF_R23			23
+#define EF_R24			24
+#define EF_R25			25
+
+/*
+ * k0/k1 unsaved
+ */
+#define EF_R26			26
+#define EF_R27			27
+
+#define EF_R28			28
+#define EF_R29			29
+#define EF_R30			30
+#define EF_R31			31
+
+/*
+ * Saved special registers
+ */
+#define EF_LO			32
+#define EF_HI			33
+
+#define EF_CP0_EPC		34
+#define EF_CP0_BADVADDR		35
+#define EF_CP0_STATUS		36
+#define EF_CP0_CAUSE		37
+
+#define EF_SIZE			304	/* size in bytes */
 
-#define EF_SIZE			180	/* size in bytes */
+#endif /* CONFIG_64BIT */
 
 #endif /* __ASM_MIPS_REG_H */
diff --git a/include/asm-mips/regdef.h b/include/asm-mips/regdef.h
index 691d047..2e65cc3 100644
--- a/include/asm-mips/regdef.h
+++ b/include/asm-mips/regdef.h
@@ -1,52 +1,100 @@
 /*
- * include/asm-mips/regdefs.h
- *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1994, 1995 by Ralf Baechle
+ * Copyright (C) 1985 MIPS Computer Systems, Inc.
+ * Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle
+ * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
  */
+#ifndef _ASM_REGDEF_H
+#define _ASM_REGDEF_H
+
+#include <asm/sgidefs.h>
 
-#ifndef __ASM_MIPS_REGDEF_H
-#define __ASM_MIPS_REGDEF_H
+#if _MIPS_SIM == _MIPS_SIM_ABI32
 
 /*
  * Symbolic register names for 32 bit ABI
  */
-#define zero    $0      /* wired zero */
-#define AT      $1      /* assembler temp  - uppercase because of ".set at" */
-#define v0      $2      /* return value */
-#define v1      $3
-#define a0      $4      /* argument registers */
-#define a1      $5
-#define a2      $6
-#define a3      $7
-#define t0      $8      /* caller saved */
-#define t1      $9
-#define t2      $10
-#define t3      $11
-#define t4      $12
-#define t5      $13
-#define t6      $14
-#define t7      $15
-#define s0      $16     /* callee saved */
-#define s1      $17
-#define s2      $18
-#define s3      $19
-#define s4      $20
-#define s5      $21
-#define s6      $22
-#define s7      $23
-#define t8      $24     /* caller saved */
-#define t9      $25
-#define jp      $25     /* PIC jump register */
-#define k0      $26     /* kernel scratch */
-#define k1      $27
-#define gp      $28     /* global pointer */
-#define sp      $29     /* stack pointer */
-#define fp      $30     /* frame pointer */
+#define zero	$0	/* wired zero */
+#define AT	$1	/* assembler temp  - uppercase because of ".set at" */
+#define v0	$2	/* return value */
+#define v1	$3
+#define a0	$4	/* argument registers */
+#define a1	$5
+#define a2	$6
+#define a3	$7
+#define t0	$8	/* caller saved */
+#define t1	$9
+#define t2	$10
+#define t3	$11
+#define t4	$12
+#define t5	$13
+#define t6	$14
+#define t7	$15
+#define s0	$16	/* callee saved */
+#define s1	$17
+#define s2	$18
+#define s3	$19
+#define s4	$20
+#define s5	$21
+#define s6	$22
+#define s7	$23
+#define t8	$24	/* caller saved */
+#define t9	$25
+#define jp	$25	/* PIC jump register */
+#define k0	$26	/* kernel scratch */
+#define k1	$27
+#define gp	$28	/* global pointer */
+#define sp	$29	/* stack pointer */
+#define fp	$30	/* frame pointer */
 #define s8	$30	/* same like fp! */
-#define ra      $31     /* return address */
+#define ra	$31	/* return address */
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
+
+#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
+
+#define zero	$0	/* wired zero */
+#define AT	$at	/* assembler temp - uppercase because of ".set at" */
+#define v0	$2	/* return value - caller saved */
+#define v1	$3
+#define a0	$4	/* argument registers */
+#define a1	$5
+#define a2	$6
+#define a3	$7
+#define a4	$8	/* arg reg 64 bit; caller saved in 32 bit */
+#define ta0	$8
+#define a5	$9
+#define ta1	$9
+#define a6	$10
+#define ta2	$10
+#define a7	$11
+#define ta3	$11
+#define t0	$12	/* caller saved */
+#define t1	$13
+#define t2	$14
+#define t3	$15
+#define s0	$16	/* callee saved */
+#define s1	$17
+#define s2	$18
+#define s3	$19
+#define s4	$20
+#define s5	$21
+#define s6	$22
+#define s7	$23
+#define t8	$24	/* caller saved */
+#define t9	$25	/* callee address for PIC/temp */
+#define jp	$25	/* PIC jump register */
+#define k0	$26	/* kernel temporary */
+#define k1	$27
+#define gp	$28	/* global pointer - caller saved for PIC */
+#define sp	$29	/* stack pointer */
+#define fp	$30	/* frame pointer */
+#define s8	$30	/* callee saved */
+#define ra	$31	/* return address */
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
 
-#endif /* __ASM_MIPS_REGDEF_H */
+#endif /* _ASM_REGDEF_H */
diff --git a/include/asm-mips/types.h b/include/asm-mips/types.h
index 707cbf4..f49a217 100644
--- a/include/asm-mips/types.h
+++ b/include/asm-mips/types.h
@@ -1,5 +1,4 @@
-/* $Id: types.h,v 1.3 1999/08/18 23:37:50 ralf Exp $
- *
+/*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
@@ -10,6 +9,8 @@
 #ifndef _ASM_TYPES_H
 #define _ASM_TYPES_H
 
+#ifndef __ASSEMBLY__
+
 typedef unsigned short umode_t;
 
 /*
@@ -40,11 +41,17 @@ __extension__ typedef unsigned long long __u64;
 
 #endif
 
+#endif /* __ASSEMBLY__ */
+
 /*
  * These aren't exported outside the kernel to avoid name space clashes
  */
 #ifdef __KERNEL__
 
+#define BITS_PER_LONG _MIPS_SZLONG
+
+#ifndef __ASSEMBLY__
+
 typedef __signed char s8;
 typedef unsigned char u8;
 
@@ -68,9 +75,24 @@ typedef unsigned long long u64;
 
 #endif
 
-#define BITS_PER_LONG _MIPS_SZLONG
+#if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \
+    || defined(CONFIG_64BIT)
+typedef u64 dma_addr_t;
+#else
+typedef u32 dma_addr_t;
+#endif
+typedef u64 dma64_addr_t;
+
+/*
+ * Don't use phys_t.  You've been warned.
+ */
+#ifdef CONFIG_64BIT_PHYS_ADDR
+typedef unsigned long long phys_t;
+#else
+typedef unsigned long phys_t;
+#endif
 
-typedef unsigned long dma_addr_t;
+#endif /* __ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
 
diff --git a/include/asm-ppc/fsl_serdes.h b/include/asm-ppc/fsl_serdes.h
new file mode 100644
index 0000000..733f919
--- /dev/null
+++ b/include/asm-ppc/fsl_serdes.h
@@ -0,0 +1,21 @@
+#ifndef __FSL_SERDES_H
+#define __FSL_SERDES_H
+
+#include <config.h>
+
+#define FSL_SERDES_CLK_100		0
+#define FSL_SERDES_CLK_125		1
+#define FSL_SERDES_CLK_150		3
+#define FSL_SERDES_PROTO_SATA		0
+#define FSL_SERDES_PROTO_PEX		1
+#define FSL_SERDES_PROTO_PEX_X2		2
+#define FSL_SERDES_PROTO_SGMII		3
+#define FSL_SERDES_VDD_1V		1
+
+#ifdef CONFIG_FSL_SERDES
+extern void fsl_setup_serdes(u32 offset, char proto, char rfcks, char vdd);
+#else
+static void fsl_setup_serdes(u32 offset, char proto, char rfcks, char vdd) {}
+#endif /* CONFIG_FSL_SERDES */
+
+#endif /* __FSL_SERDES_H */
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index e07092b..b43dba3 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -40,8 +40,11 @@ typedef	struct	global_data {
 	bd_t		*bd;
 	unsigned long	flags;
 	unsigned long	baudrate;
-	unsigned long	cpu_clk;	/* CPU clock in Hz!		*/
+	unsigned long	cpu_clk;	/* CPU clock in Hz! */
 	unsigned long	bus_clk;
+#if defined(CONFIG_8xx)
+	unsigned long	brg_clk;
+#endif
 #if defined(CONFIG_CPM2)
 	/* There are many clocks on the MPC8260 - see page 9-5 */
 	unsigned long	vco_out;
@@ -49,9 +52,7 @@ typedef	struct	global_data {
 	unsigned long	scc_clk;
 	unsigned long	brg_clk;
 #endif
-#if defined(CONFIG_MPC7448HPC2)
 	unsigned long   mem_clk;
-#endif
 #if defined(CONFIG_MPC83XX)
 	/* There are other clocks in the MPC83XX */
 	u32 csb_clk;
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index d769d70..3506aec 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -57,7 +57,7 @@ typedef struct ccsr_local_ecm {
 	uint	lawbar7;	/* 0xce8 - Local Access Window 7 Base Address Register */
 	char	res19[4];
 	uint	lawar7;		/* 0xcf0 - Local Access Window 7 Attributes Register */
-	char	res20[780];
+	char	res20[780];		// XXX: LAW 8, LAW9 for 8572
 	uint	eebacr;		/* 0x1000 - ECM CCB Address Configuration Register */
 	char	res21[12];
 	uint	eebpcr;		/* 0x1010 - ECM CCB Port Configuration Register */
@@ -86,7 +86,12 @@ typedef struct ccsr_ddr {
 	uint	cs1_config;		/* 0x2084 - DDR Chip Select Configuration */
 	uint	cs2_config;		/* 0x2088 - DDR Chip Select Configuration */
 	uint	cs3_config;		/* 0x208c - DDR Chip Select Configuration */
-	char	res5[112];
+	char	res4a[48];
+	uint	cs0_config_2;		/* 0x20c0 - DDR Chip Select Configuration 2 */
+	uint	cs1_config_2;		/* 0x20c4 - DDR Chip Select Configuration 2 */
+	uint	cs2_config_2;		/* 0x20c8 - DDR Chip Select Configuration 2 */
+	uint	cs3_config_2;		/* 0x20cc - DDR Chip Select Configuration 2 */
+	char	res5[48];
 	uint	ext_refrec;		/* 0x2100 - DDR SDRAM Extended Refresh Recovery */
 	uint	timing_cfg_0;		/* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
 	uint	timing_cfg_1;		/* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
@@ -103,7 +108,17 @@ typedef struct ccsr_ddr {
 	char	res7[20];
 	uint	init_address;		/* 0x2148 - DDR training initialization address */
 	uint	init_ext_address;	/* 0x214C - DDR training initialization extended address */
-	char	res8_1[2728];
+	char	res8_1[16];
+	uint	timing_cfg_4;		/* 0x2160 - DDR SDRAM Timing Configuration Register 4 */
+	uint	timing_cfg_5;		/* 0x2164 - DDR SDRAM Timing Configuration Register 5 */
+	char	reg8_1a[8];
+	uint	ddr_zq_cntl;		/* 0x2170 - DDR ZQ calibration control*/
+	uint	ddr_wrlvl_cntl;		/* 0x2174 - DDR write leveling control*/
+	uint	ddr_pd_cntl;		/* 0x2178 - DDR pre-drive conditioning control*/
+	uint	ddr_sr_cntr;		/* 0x217C - DDR self refresh counter */
+	uint	ddr_sdram_rcw_1;	/* 0x2180 - DDR Register Control Words 1 */
+	uint	ddr_sdram_rcw_2;	/* 0x2184 - DDR Register Control Words 2 */
+	char	res8_1b[2672];
 	uint	ip_rev1;		/* 0x2BF8 - DDR IP Block Revision 1 */
 	uint	ip_rev2;		/* 0x2BFC - DDR IP Block Revision 2 */
 	char	res8_2[512];
@@ -217,7 +232,7 @@ typedef struct ccsr_lbc {
 	char	res7[12];
 	uint	lbcr;		/* 0x50d0 - LBC Configuration Register */
 	uint	lcrr;		/* 0x50d4 - LBC Clock Ratio Register */
-	char	res8[12072];
+	char	res8[3880];
 } ccsr_lbc_t;
 
 /*
@@ -1578,7 +1593,11 @@ typedef struct ccsr_gur {
 #define MPC85xx_DEVDISR_RMSG		0x00040000
 #define MPC85xx_DEVDISR_DDR 		0x00010000
 #define MPC85xx_DEVDISR_CPU 		0x00008000
+#define MPC85xx_DEVDISR_CPU0 		MPC85xx_DEVDISR_CPU
 #define MPC85xx_DEVDISR_TB 		0x00004000
+#define MPC85xx_DEVDISR_TB0 		MPC85xx_DEVDISR_TB
+#define MPC85xx_DEVDISR_CPU1 		0x00002000
+#define MPC85xx_DEVDISR_TB1 		0x00001000
 #define MPC85xx_DEVDISR_DMA		0x00000400
 #define MPC85xx_DEVDISR_TSEC1		0x00000080
 #define MPC85xx_DEVDISR_TSEC2		0x00000040
@@ -1624,6 +1643,8 @@ typedef struct ccsr_gur {
 #define CFG_MPC85xx_ECM_ADDR	(CFG_IMMR + CFG_MPC85xx_ECM_OFFSET)
 #define CFG_MPC85xx_DDR_OFFSET	(0x2000)
 #define CFG_MPC85xx_DDR_ADDR	(CFG_IMMR + CFG_MPC85xx_DDR_OFFSET)
+#define CFG_MPC85xx_DDR2_OFFSET	(0x6000)
+#define CFG_MPC85xx_DDR2_ADDR	(CFG_IMMR + CFG_MPC85xx_DDR2_OFFSET)
 #define CFG_MPC85xx_LBC_OFFSET	(0x5000)
 #define CFG_MPC85xx_LBC_ADDR	(CFG_IMMR + CFG_MPC85xx_LBC_OFFSET)
 #define CFG_MPC85xx_PCIX_OFFSET	(0x8000)
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index b7a5b28..544cc01 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -879,22 +879,42 @@
 #define SVR_MAJ(svr)	(((svr) >>  4) & 0xF)	/* Major revision field*/
 #define SVR_MIN(svr)	(((svr) >>  0) & 0xF)	/* Minor revision field*/
 
+/* Some parts define SVR[0:23] as the SOC version */
+#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF)	/* SOC Version fields */
+
 
 /*
- * SVR_VER() Version Values
+ * SVR_SOC_VER() Version Values
  */
 
-#define SVR_8540	0x8030
-#define SVR_8560	0x8070
-#define SVR_8555	0x8079
-#define SVR_8541	0x807A
-#define SVR_8544	0x8034
-#define SVR_8544_E	0x803C
-#define SVR_8548	0x8031
-#define SVR_8548_E	0x8039
-#define SVR_8610	0x80A0
-#define SVR_8641	0x8090
-#define SVR_8568_E	0x807D
+#define SVR_8533	0x803400
+#define SVR_8533_E	0x803C00
+#define SVR_8540	0x803000
+#define SVR_8541	0x807200
+#define SVR_8541_E	0x807A00
+#define SVR_8543	0x803200
+#define SVR_8543_E	0x803A00
+#define SVR_8544	0x803401
+#define SVR_8544_E	0x803C01
+#define SVR_8545	0x803102
+#define SVR_8545_E	0x803902
+#define SVR_8547_E	0x803901
+#define SVR_8548	0x803100
+#define SVR_8548_E	0x803900
+#define SVR_8555	0x807100
+#define SVR_8555_E	0x807900
+#define SVR_8560	0x807000
+#define SVR_8567	0x807600
+#define SVR_8567_E	0x807E00
+#define SVR_8568	0x807500
+#define SVR_8568_E	0x807D00
+#define SVR_8572	0x80E000
+#define SVR_8572_E	0x80E800
+
+#define SVR_8610	0x80A000
+#define SVR_8641	0x809000
+#define SVR_8641D	0x809001
+
 
 
 /* I am just adding a single entry for 8260 boards.  I think we may be
diff --git a/include/common.h b/include/common.h
index 673afdd..39bcd30 100644
--- a/include/common.h
+++ b/include/common.h
@@ -222,10 +222,7 @@ int mac_read_from_eeprom(void);
 void flash_perror (int);
 
 /* common/cmd_autoscript.c */
-int	autoscript (ulong addr);
-
-/* common/cmd_bootm.c */
-void	print_image_hdr (image_header_t *hdr);
+int	autoscript (ulong addr, const char *fit_uname);
 
 extern ulong load_addr;		/* Default Load Address */
 
@@ -672,4 +669,11 @@ void inline show_boot_progress (int val);
 
 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
 
+/* Multicore arch functions */
+#ifdef CONFIG_MP
+int cpu_status(int nr);
+int cpu_reset(int nr);
+int cpu_release(int nr, int argc, char *argv[]);
+#endif
+
 #endif	/* __COMMON_H_ */
diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h
index f3965ef..69276a3 100644
--- a/include/config_cmd_all.h
+++ b/include/config_cmd_all.h
@@ -70,6 +70,7 @@
 #define CONFIG_CMD_SAVES	/* save S record dump		*/
 #define CONFIG_CMD_SCSI		/* SCSI Support			*/
 #define CONFIG_CMD_SDRAM	/* SDRAM DIMM SPD info printout */
+#define CONFIG_CMD_SETEXPR	/* setexpr support 		*/
 #define CONFIG_CMD_SETGETDCR	/* DCR support on 4xx		*/
 #define CONFIG_CMD_SNTP		/* SNTP support			*/
 #define CONFIG_CMD_SPI		/* SPI utility			*/
diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h
index c14376e..0d644da 100644
--- a/include/configs/ATUM8548.h
+++ b/include/configs/ATUM8548.h
@@ -96,6 +96,7 @@
  */
 #define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 #define PCI_SPEED		33333000        /* CPLD currenlty does not have PCI setup info */
diff --git a/include/configs/Adder.h b/include/configs/Adder.h
index 4304ecc..7919991 100644
--- a/include/configs/Adder.h
+++ b/include/configs/Adder.h
@@ -37,6 +37,8 @@
 
 #define CONFIG_ETHER_ON_FEC1
 #define CONFIG_ETHER_ON_FEC2
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
 
 #if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)
 #define CFG_DISCOVER_PHY
@@ -212,4 +214,8 @@
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from flash	*/
 #define BOOTFLAG_WARM		0x02	/* Software reboot			*/
 
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index f12a3e6..9576fa5 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -38,6 +38,14 @@
 #define CONFIG_PCI
 #define CONFIG_83XX_GENERIC_PCI
 
+#define CONFIG_MISC_INIT_R
+
+/*
+ * On-board devices
+ */
+#define CONFIG_VSC7385_ENET
+
+
 #ifdef CFG_66MHZ
 #define CONFIG_83XX_CLKIN	66666667	/* in Hz */
 #elif defined(CFG_33MHZ)
@@ -65,6 +73,22 @@
 #define CFG_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
 
 /*
+ * Device configurations
+ */
+
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+#define CONFIG_TSEC2
+
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE		0xFE7FE000
+#define CONFIG_VSC7385_IMAGE_SIZE	8192
+
+#endif
+
+/*
  * DDR Setup
  */
 #define CFG_DDR_BASE		0x00000000	/* DDR is system memory*/
@@ -214,19 +238,24 @@
 #define CFG_LBLAWBAR1_PRELIM	CFG_NAND_BASE
 #define CFG_LBLAWAR1_PRELIM	0x8000000E	/* 32KB  */
 
+/* local bus read write buffer mapping */
+#define CFG_BR3_PRELIM		0xFA000801	/* map at 0xFA000000 */
+#define CFG_OR3_PRELIM		0xFFFF8FF7	/* 32kB */
+#define CFG_LBLAWBAR3_PRELIM	0xFA000000
+#define CFG_LBLAWAR3_PRELIM	0x8000000E	/* 32KB  */
+
+/* Vitesse 7385 */
+
 #define CFG_VSC7385_BASE	0xF0000000
 
-#define CONFIG_VSC7385_ENET			/* VSC7385 ethernet support */
+#ifdef CONFIG_VSC7385_ENET
+
 #define CFG_BR2_PRELIM		0xf0000801	/* VSC7385 Base address */
 #define CFG_OR2_PRELIM		0xfffe09ff	/* VSC7385, 128K bytes*/
 #define CFG_LBLAWBAR2_PRELIM	CFG_VSC7385_BASE/* Access window base at VSC7385 base */
 #define CFG_LBLAWAR2_PRELIM	0x80000010	/* Access window size 128K */
 
-/* local bus read write buffer mapping */
-#define CFG_BR3_PRELIM		0xFA000801	/* map at 0xFA000000 */
-#define CFG_OR3_PRELIM		0xFFFF8FF7	/* 32kB */
-#define CFG_LBLAWBAR3_PRELIM	0xFA000000
-#define CFG_LBLAWAR3_PRELIM	0x8000000E	/* 32KB  */
+#endif
 
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
@@ -263,13 +292,6 @@
 #define CFG_I2C_OFFSET		0x3000
 #define CFG_I2C2_OFFSET		0x3100
 
-/* TSEC */
-#define CFG_TSEC1_OFFSET	0x24000
-#define CFG_TSEC1		(CFG_IMMR+CFG_TSEC1_OFFSET)
-#define CFG_TSEC2_OFFSET	0x25000
-#define CFG_TSEC2		(CFG_IMMR+CFG_TSEC2_OFFSET)
-#define CONFIG_NET_MULTI
-
 /*
  * General PCI
  * Addresses are mapped 1-1.
@@ -288,26 +310,31 @@
 #define CFG_PCI_SUBSYS_VENDORID 0x1057	/* Motorola */
 
 /*
- * TSEC configuration
+ * TSEC
  */
 #define CONFIG_TSEC_ENET		/* TSEC ethernet support */
 
-#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI		1
-#endif
-
-#define CONFIG_GMII			1	/* MII PHY management */
-#define CONFIG_TSEC1		1
+#define CONFIG_NET_MULTI
+#define CONFIG_GMII			/* MII PHY management */
 
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
 #define CONFIG_TSEC1_NAME	"TSEC0"
-#define CONFIG_TSEC2		1
+#define CFG_TSEC1_OFFSET	0x24000
+#define TSEC1_PHY_ADDR		0x1c
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC1_PHYIDX		0
+#endif
+
+#ifdef CONFIG_TSEC2
+#define CONFIG_HAS_ETH1
 #define CONFIG_TSEC2_NAME	"TSEC1"
-#define TSEC1_PHY_ADDR			0x1c
-#define TSEC2_PHY_ADDR			4
-#define TSEC1_FLAGS			TSEC_GIGABIT
-#define TSEC2_FLAGS			TSEC_GIGABIT
-#define TSEC1_PHYIDX			0
-#define TSEC2_PHYIDX			0
+#define CFG_TSEC2_OFFSET	0x25000
+#define TSEC2_PHY_ADDR		4
+#define TSEC2_FLAGS		TSEC_GIGABIT
+#define TSEC2_PHYIDX		0
+#endif
+
 
 /* Options are: TSEC[0-1] */
 #define CONFIG_ETHPRIME			"TSEC1"
@@ -496,10 +523,13 @@
  */
 #define CONFIG_ENV_OVERWRITE
 
+#ifdef CONFIG_HAS_ETH0
 #define CONFIG_ETHADDR		00:E0:0C:00:95:01
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH0
+#endif
+
+#ifdef CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR		00:E0:0C:00:95:02
+#endif
 
 #define CONFIG_IPADDR		10.0.0.2
 #define CONFIG_SERVERIP		10.0.0.1
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index ff7101f..af78726 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -299,7 +299,7 @@
 #define CFG_PCI_MMIO_BASE	0x90000000
 #define CFG_PCI_MMIO_PHYS	CFG_PCI_MMIO_BASE
 #define CFG_PCI_MMIO_SIZE	0x10000000 /* 256M */
-#define CFG_PCI_IO_BASE		0xE0300000
+#define CFG_PCI_IO_BASE		0x00000000
 #define CFG_PCI_IO_PHYS		0xE0300000
 #define CFG_PCI_IO_SIZE		0x100000 /* 1M */
 
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index bf5ef4b..94c4c6b 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -66,6 +66,13 @@
 #define CFG_IMMR		0xE0000000
 
 /*
+ * System performance
+ */
+#define CFG_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
+#define CFG_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
+#define CFG_SPCR_OPT		1	/* (0-1) Optimize transactions between  CSB and the SEC and QUICC Engine block */
+
+/*
  * DDR Setup
  */
 #define CFG_DDR_BASE		0x00000000	/* DDR is system memory */
@@ -82,17 +89,51 @@
 /* Manually set up DDR parameters
  */
 #define CFG_DDR_SIZE		64	/* MB */
-#define CFG_DDR_CS0_CONFIG	0x80840101
-#define CFG_DDR_TIMING_0	0x00220802
-#define CFG_DDR_TIMING_1	0x3935d322
-#define CFG_DDR_TIMING_2	0x0f9048ca
+#define CFG_DDR_CS0_CONFIG	( CSCONFIG_EN \
+				| CSCONFIG_ODT_WR_ACS \
+				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9 )
+				/* 0x80010101 */
+#define CFG_DDR_TIMING_0	( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
+				| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
+				| ( 0 << TIMING_CFG0_RRT_SHIFT ) \
+				| ( 0 << TIMING_CFG0_WWT_SHIFT ) \
+				| ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
+				| ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
+				| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
+				| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
+				/* 0x00220802 */
+#define CFG_DDR_TIMING_1	( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \
+				| ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
+				| ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \
+				| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
+				| ( 3 << TIMING_CFG1_REFREC_SHIFT ) \
+				| ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
+				| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
+				| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
+				/* 0x26253222 */
+#define CFG_DDR_TIMING_2	( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
+				| (31 << TIMING_CFG2_CPO_SHIFT ) \
+				| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
+				| ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
+				| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
+				| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
+				| ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) )
+				/* 0x1f9048c7 */
 #define CFG_DDR_TIMING_3	0x00000000
-#define CFG_DDR_CLK_CNTL	0x02000000
-#define CFG_DDR_MODE		0x44400232
+#define CFG_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+				/* 0x02000000 */
+#define CFG_DDR_MODE		( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
+				| ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
+				/* 0x44480232 */
 #define CFG_DDR_MODE2		0x8000c000
-#define CFG_DDR_INTERVAL	0x03200064
+#define CFG_DDR_INTERVAL	( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \
+				| ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
+				/* 0x03200064 */
 #define CFG_DDR_CS0_BNDS	0x00000003
-#define CFG_DDR_SDRAM_CFG	0x43080000
+#define CFG_DDR_SDRAM_CFG	( SDRAM_CFG_SREN \
+				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
+				| SDRAM_CFG_32_BE )
+				/* 0x43080000 */
 #define CFG_DDR_SDRAM_CFG2	0x00401000
 #endif
 
@@ -280,10 +321,10 @@
 #define CFG_I2C_OFFSET	0x3000
 
 /*
- * Config on-board RTC
+ * Config on-board EEPROM
  */
-#define CONFIG_RTC_DS1374		/* use ds1374 rtc via i2c */
-#define CFG_I2C_RTC_ADDR	0x68	/* at address 0x68 */
+#define CFG_I2C_EEPROM_ADDR     0x50
+#define CFG_I2C_EEPROM_ADDR_LEN 2
 
 /*
  * General PCI
@@ -376,6 +417,7 @@
 
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_ASKENV
 
 #if defined(CONFIG_PCI)
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index f32c4f7..be2ab45 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -346,7 +346,7 @@
 #define CFG_PCI_MMIO_BASE	0x90000000
 #define CFG_PCI_MMIO_PHYS	CFG_PCI_MMIO_BASE
 #define CFG_PCI_MMIO_SIZE	0x10000000	/* 256M */
-#define CFG_PCI_IO_BASE		0xE0300000
+#define CFG_PCI_IO_BASE		0x00000000
 #define CFG_PCI_IO_PHYS		0xE0300000
 #define CFG_PCI_IO_SIZE		0x100000	/* 1M */
 
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 48c2736..6b8b74d 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -68,12 +68,16 @@
 
 #define CFG_IMMR		0xE0000000	/* The IMMR is relocated to here */
 
+#define CONFIG_MISC_INIT_F
+#define CONFIG_MISC_INIT_R
 
-/* On-board devices */
+/*
+ * On-board devices
+ */
 
 #ifdef CONFIG_MPC8349ITX
 #define CONFIG_COMPACT_FLASH	/* The CF card interface on the back of the board */
-#define CONFIG_VSC7385		/* The Vitesse 7385 5-port switch */
+#define CONFIG_VSC7385_ENET	/* VSC7385 ethernet support */
 #endif
 
 #define CONFIG_PCI
@@ -88,9 +92,6 @@
 /* I2C */
 #ifdef CONFIG_HARD_I2C
 
-#define CONFIG_MISC_INIT_F
-#define CONFIG_MISC_INIT_R
-
 #define CONFIG_FSL_I2C
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_I2C_CMD_TREE
@@ -155,7 +156,7 @@
 #define CFG_MEMTEST_END		0x2000
 
 #define CFG_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
-				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 
 #ifdef CONFIG_HARD_I2C
 #define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
@@ -190,6 +191,18 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CFG_FLASH_SIZE		16		/* FLASH size in MB */
 #define CFG_FLASH_SIZE_SHIFT	4		/* log2 of the above value */
 
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+#define CONFIG_TSEC2
+
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE		0xFEFFE000
+#define CONFIG_VSC7385_IMAGE_SIZE	8192
+
+#endif
+
 /*
  * BRx, ORx, LBLAWBARx, and LBLAWARx
  */
@@ -205,10 +218,10 @@ boards, we say we have two, but don't display a message if we find only one. */
 
 /* Vitesse 7385 */
 
-#ifdef CONFIG_VSC7385
-
 #define CFG_VSC7385_BASE	0xF8000000
 
+#ifdef CONFIG_VSC7385_ENET
+
 #define CFG_BR1_PRELIM		(CFG_VSC7385_BASE | BR_PS_8 | BR_V)
 #define CFG_OR1_PRELIM		(OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
 				OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
@@ -384,7 +397,7 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CONFIG_HAS_ETH1
 #define CONFIG_TSEC2_NAME  "TSEC1"
 #define CFG_TSEC2_OFFSET	0x25000
-#define CONFIG_UNKNOWN_TSEC	/* TSEC2 is proprietary */
+
 #define TSEC2_PHY_ADDR		4
 #define TSEC2_PHYIDX		0
 #define TSEC2_FLAGS		TSEC_GIGABIT
@@ -619,11 +632,11 @@ boards, we say we have two, but don't display a message if we find only one. */
  */
 #define CONFIG_ENV_OVERWRITE
 
-#ifdef CONFIG_TSEC1
+#ifdef CONFIG_HAS_ETH0
 #define CONFIG_ETHADDR		00:E0:0C:00:8C:01
 #endif
 
-#ifdef CONFIG_TSEC2
+#ifdef CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR		00:E0:0C:00:8C:02
 #endif
 
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index c8dcbc6..46451c4 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -194,6 +194,7 @@
 #define CFG_FLASH_CFI_DRIVER	/* use the CFI driver */
 #define CFG_FLASH_BASE		0xFE000000 /* FLASH base address */
 #define CFG_FLASH_SIZE		32 /* max FLASH size is 32M */
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 
 #define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE /* Window base at flash base */
 #define CFG_LBLAWAR0_PRELIM	0x80000018 /* 32MB window size */
@@ -374,7 +375,7 @@
 #define CFG_PCI_MMIO_BASE	0x90000000
 #define CFG_PCI_MMIO_PHYS	CFG_PCI_MMIO_BASE
 #define CFG_PCI_MMIO_SIZE	0x10000000 /* 256M */
-#define CFG_PCI_IO_BASE		0xE0300000
+#define CFG_PCI_IO_BASE		0x00000000
 #define CFG_PCI_IO_PHYS		0xE0300000
 #define CFG_PCI_IO_SIZE		0x100000 /* 1M */
 
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index 27b037a..a4f6af6 100644
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -30,8 +30,8 @@
  * System Clock Setup
  */
 #ifdef CONFIG_CLKIN_33MHZ
-#define CONFIG_83XX_CLKIN		33000000
-#define CONFIG_SYS_CLK_FREQ		33000000
+#define CONFIG_83XX_CLKIN		33333333
+#define CONFIG_SYS_CLK_FREQ		33333333
 #define PCI_33M				1
 #define HRCWL_CSB_TO_CLKIN_MPC8360ERDK	HRCWL_CSB_TO_CLKIN_10X1
 #else
@@ -89,8 +89,8 @@
 
 #define CFG_83XX_DDR_USES_CS0
 
-#undef CONFIG_DDR_ECC		/* support DDR ECC function */
-#undef CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */
+#define CONFIG_DDR_ECC		/* support DDR ECC function */
+#define CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */
 
 /*
  * DDRCDR - DDR Control Driver Register
@@ -104,20 +104,44 @@
  */
 #define CONFIG_DDR_II
 #define CFG_DDR_SIZE		256 /* MB */
-#define CFG_DDRCDR		0x80080001
 #define CFG_DDR_CS0_BNDS	0x0000000f
 #define CFG_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \
-				 CSCONFIG_COL_BIT_10)
-#define CFG_DDR_TIMING_0	0x00330903
-#define CFG_DDR_TIMING_1	0x3835a322
-#define CFG_DDR_TIMING_2	0x00104909
-#define CFG_DDR_TIMING_3	0x00000000
-#define CFG_DDR_CLK_CNTL	0x02000000
+				 CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
+#define CFG_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | SDRAM_CFG_ECC_EN)
+#define CFG_DDR_SDRAM_CFG2	0x00001000
+#define CFG_DDR_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#define CFG_DDR_INTERVAL	((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
+				 (1115 << SDRAM_INTERVAL_REFINT_SHIFT))
 #define CFG_DDR_MODE		0x47800432
 #define CFG_DDR_MODE2		0x8000c000
-#define CFG_DDR_INTERVAL	0x045b0100
-#define CFG_DDR_SDRAM_CFG	0x03000000
-#define CFG_DDR_SDRAM_CFG2	0x00001000
+
+#define CFG_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
+				 (9 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+				 (3 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
+				 (3 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
+				 (0 << TIMING_CFG0_WWT_SHIFT) | \
+				 (0 << TIMING_CFG0_RRT_SHIFT) | \
+				 (0 << TIMING_CFG0_WRT_SHIFT) | \
+				 (0 << TIMING_CFG0_RWT_SHIFT))
+
+#define CFG_DDR_TIMING_1	((      TIMING_CFG1_CASLAT_30) | \
+				 ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
+				 ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+				 ( 3 << TIMING_CFG1_WRREC_SHIFT) | \
+				 (10 << TIMING_CFG1_REFREC_SHIFT) | \
+				 ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \
+				 ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+				 ( 3 << TIMING_CFG1_PRETOACT_SHIFT))
+
+#define CFG_DDR_TIMING_2	((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+				 (4 << TIMING_CFG2_CKE_PLS_SHIFT) | \
+				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
+				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
+				 (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
+				 (0 << TIMING_CFG2_CPO_SHIFT))
+
+#define CFG_DDR_TIMING_3	0x00000000
 
 /*
  * Memory test
@@ -184,6 +208,11 @@
  * NAND flash on the local bus
  */
 #define CFG_NAND_BASE		0x60000000
+#define CONFIG_CMD_NAND		1
+#define CONFIG_NAND_FSL_UPM	1
+#define CFG_MAX_NAND_DEVICE	1
+#define NAND_MAX_CHIPS		1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
 
 #define CFG_LBLAWBAR1_PRELIM	CFG_NAND_BASE
 #define CFG_LBLAWAR1_PRELIM	0x8000001b /* Access window size 4K */
@@ -230,6 +259,7 @@
 /* Pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_STDOUT_VIA_ALIAS
 
 /* I2C */
 #define CONFIG_HARD_I2C		/* I2C with hardware support */
@@ -290,7 +320,7 @@
 #define CFG_UEC1_TX_CLK		QE_CLK9
 #define CFG_UEC1_ETH_TYPE	GIGA_ETH
 #define CFG_UEC1_PHY_ADDR	2
-#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII
+#define CFG_UEC1_INTERFACE_MODE ENET_1000_RGMII_RXID
 #endif
 
 #define CONFIG_UEC_ETH2		/* GETH2 */
@@ -301,7 +331,7 @@
 #define CFG_UEC2_TX_CLK		QE_CLK4
 #define CFG_UEC2_ETH_TYPE	GIGA_ETH
 #define CFG_UEC2_PHY_ADDR	4
-#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII
+#define CFG_UEC2_INTERFACE_MODE ENET_1000_RGMII_RXID
 #endif
 
 /*
@@ -340,6 +370,7 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
 
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI
@@ -499,27 +530,44 @@
    "consoledev=ttyS0\0"\
    "loadaddr=a00000\0"\
    "fdtaddr=900000\0"\
-   "bootfile=uImage\0"\
    "fdtfile=dtb\0"\
    "fsfile=fs\0"\
    "ubootfile=u-boot.bin\0"\
+   "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),-(rootfs)\0"\
    "setbootargs=setenv bootargs console=$consoledev,$baudrate "\
    		"$mtdparts panic=1\0"\
    "adddhcpargs=setenv bootargs $bootargs ip=on\0"\
    "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:"\
    		"$gatewayip:$netmask:$hostname:$netdev:off "\
    		"root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"\
+   "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 "\
+		"rootfstype=jffs2 rw\0"\
    "tftp_get_uboot=tftp 100000 $ubootfile\0"\
    "tftp_get_kernel=tftp $loadaddr $bootfile\0"\
    "tftp_get_dtb=tftp $fdtaddr $fdtfile\0"\
    "tftp_get_fs=tftp c00000 $fsfile\0"\
+   "nand_erase_kernel=nand erase 0 400000\0"\
+   "nand_erase_dtb=nand erase 400000 20000\0"\
+   "nand_erase_fs=nand erase 420000 3be0000\0"\
+   "nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0"\
+   "nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0"\
+   "nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0"\
+   "nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0"\
+   "nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0"\
    "nor_reflash=protect off ff800000 ff87ffff ; erase ff800000 ff87ffff ; "\
    		"cp.b 100000 ff800000 $filesize\0"\
+   "nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel "\
+		"nand_write_kernel\0"\
+   "nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\
+   "nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0"\
+   "nand_reflash=run nand_reflash_kernel nand_reflash_dtb "\
+		"nand_reflash_fs\0"\
    "boot_m=bootm $loadaddr - $fdtaddr\0"\
-   "dhcpboot=run setbootargs adddhcpargs tftp_get_kernel tftp_get_dtb "\
-   		"boot_m\0"\
+   "dhcpboot=dhcp ; run setbootargs adddhcpargs tftp_get_dtb boot_m\0"\
    "nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\
-   		"boot_m\0"\
+		"boot_m\0"\
+   "nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\
+		"boot_m\0"\
    ""
 
 #define CONFIG_BOOTCOMMAND "run dhcpboot"
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 5586533..b307bf7 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -338,7 +338,7 @@
 #define CFG_PCI_MMIO_BASE	0x90000000
 #define CFG_PCI_MMIO_PHYS	CFG_PCI_MMIO_BASE
 #define CFG_PCI_MMIO_SIZE	0x10000000 /* 256M */
-#define CFG_PCI_IO_BASE		0xE0300000
+#define CFG_PCI_IO_BASE		0x00000000
 #define CFG_PCI_IO_PHYS		0xE0300000
 #define CFG_PCI_IO_SIZE		0x100000 /* 1M */
 
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 1964946..90812e9 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -32,6 +32,15 @@
 
 #define CONFIG_PCI	1
 
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
+
+/*
+ * On-board devices
+ */
+#define CONFIG_TSEC_ENET		/* TSEC Ethernet support */
+#define CONFIG_VSC7385_ENET
+
 /*
  * System Clock Setup
  */
@@ -118,6 +127,22 @@
 #define CFG_IMMR		0xE0000000
 
 /*
+ * Device configurations
+ */
+
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+#define CONFIG_TSEC2
+
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE		0xFE7FE000
+#define CONFIG_VSC7385_IMAGE_SIZE	8192
+
+#endif
+
+/*
  * DDR Setup
  */
 #define CFG_DDR_BASE		0x00000000 /* DDR is system memory */
@@ -251,15 +276,38 @@
 #define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 
+/*
+ * NAND Flash on the Local Bus
+ */
+#define CFG_NAND_BASE		0xE0600000	/* 0xE0600000 */
+#define CFG_BR1_PRELIM		(CFG_NAND_BASE | \
+				 (2 << BR_DECC_SHIFT) |	/* Use HW ECC */ \
+				 BR_PS_8 |		/* Port Size = 8 bit */ \
+				 BR_MS_FCM |		/* MSEL = FCM */ \
+				 BR_V)			/* valid */
+#define CFG_OR1_PRELIM		(0xFFFF8000 |		/* length 32K */ \
+				 OR_FCM_CSCT | \
+				 OR_FCM_CST | \
+				 OR_FCM_CHT | \
+				 OR_FCM_SCY_1 | \
+				 OR_FCM_TRLX | \
+				 OR_FCM_EHTR)
+#define CFG_LBLAWBAR1_PRELIM	CFG_NAND_BASE
+#define CFG_LBLAWAR1_PRELIM	0x8000000E	/* 32KB  */
+
+/* Vitesse 7385 */
+
 #define CFG_VSC7385_BASE	0xF0000000
 
-/* VSC7385 Gigabit Switch support */
-#define CONFIG_VSC7385_ENET
+#ifdef CONFIG_VSC7385_ENET
+
 #define CFG_BR2_PRELIM		0xf0000801		/* Base address */
 #define CFG_OR2_PRELIM		0xfffe09ff		/* 128K bytes*/
 #define CFG_LBLAWBAR2_PRELIM	CFG_VSC7385_BASE	/* Access Base */
 #define CFG_LBLAWAR2_PRELIM	0x80000010		/* Access Size 128K */
 
+#endif
+
 /*
  * Serial Port
  */
@@ -276,6 +324,11 @@
 #define CFG_NS16550_COM1	(CFG_IMMR+0x4500)
 #define CFG_NS16550_COM2	(CFG_IMMR+0x4600)
 
+/* SERDES */
+#define CONFIG_FSL_SERDES
+#define CONFIG_FSL_SERDES1	0xe3000
+#define CONFIG_FSL_SERDES2	0xe3100
+
 /* Use the HUSH parser */
 #define CFG_HUSH_PARSER
 #ifdef	CFG_HUSH_PARSER
@@ -285,6 +338,7 @@
 /* Pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
 
 /* I2C */
 #define CONFIG_HARD_I2C		/* I2C with hardware support */
@@ -312,7 +366,7 @@
 #define CFG_PCI_MMIO_BASE	0x90000000
 #define CFG_PCI_MMIO_PHYS	CFG_PCI_MMIO_BASE
 #define CFG_PCI_MMIO_SIZE	0x10000000 /* 256M */
-#define CFG_PCI_IO_BASE		0xE0300000
+#define CFG_PCI_IO_BASE		0x00000000
 #define CFG_PCI_IO_PHYS		0xE0300000
 #define CFG_PCI_IO_SIZE		0x100000 /* 1M */
 
@@ -324,43 +378,43 @@
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
 
-#undef CONFIG_EEPRO100
 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
 #define CFG_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
 #endif	/* CONFIG_PCI */
 
-#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI	1
-#endif
-
 /*
  * TSEC
  */
-#define CONFIG_TSEC_ENET	/* TSEC ethernet support */
-#define CFG_TSEC1_OFFSET	0x24000
-#define CFG_TSEC1		(CFG_IMMR+CFG_TSEC1_OFFSET)
-#define CFG_TSEC2_OFFSET	0x25000
-#define CFG_TSEC2		(CFG_IMMR+CFG_TSEC2_OFFSET)
+#ifdef CONFIG_TSEC_ENET
 
-/*
- * TSEC ethernet configuration
- */
-#define CONFIG_GMII			1	/* MII PHY management */
-#define CONFIG_TSEC1			1
+#define CONFIG_NET_MULTI
+#define CONFIG_GMII			/* MII PHY management */
+
+#define CONFIG_TSEC1
+
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
 #define CONFIG_TSEC1_NAME		"TSEC0"
-#define CONFIG_TSEC2			1
-#define CONFIG_TSEC2_NAME		"TSEC1"
+#define CFG_TSEC1_OFFSET		0x24000
 #define TSEC1_PHY_ADDR			2
-#define TSEC2_PHY_ADDR			0x1c
 #define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
 #define TSEC1_PHYIDX			0
-#define TSEC2_PHYIDX			0
+#endif
 
+#ifdef CONFIG_TSEC2
+#define CONFIG_HAS_ETH1
+#define CONFIG_TSEC2_NAME		"TSEC1"
+#define CFG_TSEC2_OFFSET		0x25000
+#define TSEC2_PHY_ADDR			0x1c
+#define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_PHYIDX			0
+#endif
 
 /* Options are: TSEC[0-1] */
 #define CONFIG_ETHPRIME			"TSEC0"
 
+#endif
+
 /*
  * Environment
  */
@@ -529,10 +583,15 @@
  */
 #define CONFIG_ENV_OVERWRITE
 
-#define CONFIG_HAS_ETH0				/* add support for "ethaddr" */
-#define CONFIG_ETHADDR	00:04:9f:ef:04:01
-#define CONFIG_HAS_ETH1				/* add support for "eth1addr" */
-#define CONFIG_ETH1ADDR	00:04:9f:ef:04:02
+#ifdef CONFIG_HAS_ETH0
+#define CONFIG_ETHADDR		00:04:9f:ef:04:01
+#endif
+
+#ifdef CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR		00:04:9f:ef:04:02
+#endif
+
+#define CONFIG_HAS_FSL_DR_USB
 
 #define CONFIG_IPADDR		10.0.0.2
 #define CONFIG_SERVERIP		10.0.0.1
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 5ea7b25..85934d7 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -100,6 +100,7 @@
  */
 #define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 
diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h
index 174215c..77eea73 100644
--- a/include/configs/MPC8540EVAL.h
+++ b/include/configs/MPC8540EVAL.h
@@ -83,6 +83,7 @@
  */
 #define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default	*/
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR 	*/
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
 #define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory  */
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index 7334088..3f3f741 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -49,6 +49,9 @@
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
+#define CONFIG_FSL_VIA
+#define CONFIG_FSL_CDS_EEPROM
+
 /*
  * When initializing flash, if we cannot find the manufacturer ID,
  * assume this is the AMD flash associated with the CDS board.
@@ -82,6 +85,7 @@ extern unsigned long get_clock_freq(void);
  */
 #define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 /*
@@ -273,6 +277,8 @@ extern unsigned long get_clock_freq(void);
  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
  */
 
+#define CONFIG_FSL_CADMUS
+
 #define CADMUS_BASE_ADDR 0xf8000000
 #define CFG_BR3_PRELIM   0xf8000801
 #define CFG_OR3_PRELIM   0xfff00ff7
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index a894209..c83d9e2 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -98,6 +98,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  */
 #define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 #define CFG_PCI1_ADDR		(CFG_CCSRBAR+0x8000)
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index a3db9f4..fc8ad88 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -57,6 +57,9 @@
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
+#define CONFIG_FSL_VIA
+#define CONFIG_FSL_CDS_EEPROM
+
 /*
  * When initializing flash, if we cannot find the manufacturer ID,
  * assume this is the AMD flash associated with the CDS board.
@@ -96,6 +99,7 @@ extern unsigned long get_clock_freq(void);
  */
 #define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 #define CFG_PCI1_ADDR	(CFG_CCSRBAR+0x8000)
@@ -296,6 +300,8 @@ extern unsigned long get_clock_freq(void);
  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
  */
 
+#define CONFIG_FSL_CADMUS
+
 #define CADMUS_BASE_ADDR 0xf8000000
 #define CFG_BR3_PRELIM	 0xf8000801
 #define CFG_OR3_PRELIM	 0xfff00ff7
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index 93877ae..500b57c 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -49,6 +49,9 @@
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
+#define CONFIG_FSL_VIA
+#define CONFIG_FSL_CDS_EEPROM
+
 /*
  * When initializing flash, if we cannot find the manufacturer ID,
  * assume this is the AMD flash associated with the CDS board.
@@ -82,6 +85,7 @@ extern unsigned long get_clock_freq(void);
  */
 #define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 /*
@@ -273,6 +277,8 @@ extern unsigned long get_clock_freq(void);
  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
  */
 
+#define CONFIG_FSL_CADMUS
+
 #define CADMUS_BASE_ADDR 0xf8000000
 #define CFG_BR3_PRELIM   0xf8000801
 #define CFG_OR3_PRELIM   0xfff00ff7
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 08884b3..e30302c 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -95,6 +95,7 @@
  */
 #define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index a12d193..7bb20e5 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -90,6 +90,7 @@ extern unsigned long get_clock_freq(void);
  */
 #define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 #define CFG_PCI1_ADDR           (CFG_CCSRBAR+0x8000)
diff --git a/include/configs/PM854.h b/include/configs/PM854.h
index 819bee7..bd058fc 100644
--- a/include/configs/PM854.h
+++ b/include/configs/PM854.h
@@ -92,6 +92,7 @@
  */
 #define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 
diff --git a/include/configs/PM856.h b/include/configs/PM856.h
index 8902f42..38a26dc 100644
--- a/include/configs/PM856.h
+++ b/include/configs/PM856.h
@@ -94,6 +94,7 @@
  */
 #define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 
diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h
index 2bbfe9a..946b3c2 100644
--- a/include/configs/SBC8540.h
+++ b/include/configs/SBC8540.h
@@ -99,6 +99,7 @@
 #else
   #define CFG_CCSRBAR		0xff700000	/* default CCSRBAR	*/
 #endif
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
 #define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	 */
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index 9a0e9b8..b36c826 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -252,12 +252,22 @@
 	"setup=tftp 200000 cam5200/setup.img; autoscr 200000\0"
 #endif
 
+#if defined(CONFIG_TQM5200_B)
+#define ENV_FLASH_LAYOUT						\
+	"fdt_addr=FC100000\0"						\
+	"kernel_addr=FC140000\0"					\
+	"ramdisk_addr=FC600000\0"
+#else	/* !CONFIG_TQM5200_B */
+#define ENV_FLASH_LAYOUT						\
+	"fdt_addr=FC0A0000\0"						\
+	"kernel_addr=FC0C0000\0"					\
+	"ramdisk_addr=FC300000\0"
+#endif
+
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
 	"console=ttyPSC0\0"						\
-	"fdt_addr=FC0A0000\0"						\
-	"kernel_addr=FC0C0000\0"					\
-	"ramdisk_addr=FC300000\0"					\
+	ENV_FLASH_LAYOUT						\
 	"kernel_addr_r=400000\0"					\
 	"fdt_addr_r=600000\0"						\
 	"rootpath=/opt/eldk/ppc_6xx\0"					\
@@ -400,8 +410,9 @@
 # if defined(CONFIG_TQM5200_B)
 #  if defined(CFG_LOWBOOT)
 #   define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:1m(firmware),"	\
-						"1536k(kernel),"	\
-						"3584k(small-fs),"	\
+						"256k(dtb),"		\
+						"2304k(kernel),"	\
+						"2560k(small-fs),"	\
 						"2m(initrd),"		\
 						"8m(misc),"		\
 						"16m(big-fs)"
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index 21e8baf..fca5f74 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -89,6 +89,7 @@
  */
 #define CFG_CCSRBAR_DEFAULT	0xFF700000	/* CCSRBAR Default	*/
 #define CFG_CCSRBAR		0xE0000000	/* relocated CCSRBAR	*/
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
 /*
diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h
index 893924b..ba6d932 100644
--- a/include/configs/pcs440ep.h
+++ b/include/configs/pcs440ep.h
@@ -27,6 +27,12 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+
+/* new uImage format support */
+#define CONFIG_FIT		1
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
+
 /*-----------------------------------------------------------------------
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 516203a..49a7234 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -87,6 +87,7 @@
  */
 #define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 #define CFG_PCI1_ADDR	(CFG_CCSRBAR+0x8000)
diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h
index f9ede5f..81a1e07 100644
--- a/include/configs/sbc8560.h
+++ b/include/configs/sbc8560.h
@@ -93,6 +93,7 @@
 #else
   #define CFG_CCSRBAR		0xff700000	/* default CCSRBAR	*/
 #endif
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
 #define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	 */
diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h
index 8491d97..4df461d 100644
--- a/include/configs/sc520_cdp.h
+++ b/include/configs/sc520_cdp.h
@@ -81,8 +81,8 @@
 #include <config_cmd_default.h>
 
 #define CONFIG_CMD_PCI
+#define CONFIG_CMD_SATA
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_IDE
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_EEPROM
 
@@ -173,37 +173,14 @@
 #define PCNET_HAS_PROM         1
 
 /************************************************************
- * IDE/ATA stuff
- ************************************************************/
-#define CFG_IDE_MAXBUS		1   /* max. 2 IDE busses	*/
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
-
-#define CFG_ATA_IDE0_OFFSET	0x01F0	/* ide0 offste */
-/*#define CFG_ATA_IDE1_OFFSET	0x0170	/###* ide1 offset */
-#define CFG_ATA_DATA_OFFSET	0	/* data reg offset	*/
-#define CFG_ATA_REG_OFFSET	0	/* reg offset */
-#define CFG_ATA_ALT_OFFSET	0x200	/* alternate register offset */
-#define CFG_ATA_BASE_ADDR       0
-
-#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
-#undef  CONFIG_IDE_RESET		/* reset for ide unsupported...	*/
-#undef  CONFIG_IDE_RESET_ROUTINE	/* no special reset function */
-
-/************************************************************
 *SATA/Native Stuff
 ************************************************************/
-#define CFG_SATA_SUPPORTED      1
 #define CFG_SATA_MAXBUS         2       /*Max Sata buses supported */
 #define CFG_SATA_DEVS_PER_BUS   2      /*Max no. of devices per bus/port */
-#define CFG_SATA_MAXDEVICES     (CFG_SATA_MAXBUS* CFG_SATA_DEVS_PER_BUS)
+#define CFG_SATA_MAX_DEVICE     (CFG_SATA_MAXBUS* CFG_SATA_DEVS_PER_BUS)
 #define CFG_ATA_PIIX            1       /*Supports ata_piix driver */
 
 /************************************************************
- * ATAPI support (experimental)
- ************************************************************/
-#define CONFIG_ATAPI			/* enable ATAPI Support */
-
-/************************************************************
  * DISK Partition support
  ************************************************************/
 #define CONFIG_DOS_PARTITION
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h
index 047e1cf..fc5d0cc 100644
--- a/include/configs/stxgp3.h
+++ b/include/configs/stxgp3.h
@@ -114,6 +114,7 @@
 #define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default	*/
 #endif
 #define CFG_CCSRBAR             0xfdf00000      /* relocated CCSRBAR    */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
 
diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h
index e09dd71..15f690a 100644
--- a/include/configs/stxssa.h
+++ b/include/configs/stxssa.h
@@ -127,6 +127,7 @@
 #define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default	*/
 #endif
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR	*/
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
 
diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h
index b035857..f12765d 100644
--- a/include/configs/stxxtc.h
+++ b/include/configs/stxxtc.h
@@ -594,7 +594,5 @@ typedef unsigned int led_id_t;
 
 #define OF_CPU			"PowerPC,MPC870@0"
 #define OF_TBCLK		(MPC8XX_HZ / 16)
-#define CONFIG_OF_HAS_BD_T	1
-#define CONFIG_OF_HAS_UBOOT_ENV	1
 
 #endif	/* __CONFIG_H */
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 7836f28..890993f 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -50,13 +50,11 @@ int fdt_find_and_setprop(void *fdt, const char *node, const char *prop,
 			 const void *val, int len, int create);
 void fdt_fixup_qe_firmware(void *fdt);
 
-#ifdef CONFIG_OF_HAS_UBOOT_ENV
-int fdt_env(void *fdt);
-#endif
-
-#ifdef CONFIG_OF_HAS_BD_T
-int fdt_bd_t(void *fdt);
-#endif
+#ifdef CONFIG_HAS_FSL_DR_USB
+void fdt_fixup_dr_usb(void *blob, bd_t *bd);
+#else
+static inline void fdt_fixup_dr_usb(void *blob, bd_t *bd) {}
+#endif /* CONFIG_HAS_FSL_DR_USB */
 
 #ifdef CONFIG_OF_BOARD_SETUP
 void ft_board_setup(void *blob, bd_t *bd);
diff --git a/include/fis.h b/include/fis.h
new file mode 100644
index 0000000..2040b50
--- /dev/null
+++ b/include/fis.h
@@ -0,0 +1,156 @@
+/*
+ * Copyright (C) 2008 Freescale Semiconductor, Inc.
+ *		Dave Liu <daveliu@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __FIS_H__
+#define __FIS_H__
+/*
+* Register - Host to Device FIS
+*/
+typedef struct sata_fis_h2d {
+	u8 fis_type;
+	u8 pm_port_c;
+	u8 command;
+	u8 features;
+	u8 lba_low;
+	u8 lba_mid;
+	u8 lba_high;
+	u8 device;
+	u8 lba_low_exp;
+	u8 lba_mid_exp;
+	u8 lba_high_exp;
+	u8 features_exp;
+	u8 sector_count;
+	u8 sector_count_exp;
+	u8 res1;
+	u8 control;
+	u8 res2[4];
+} __attribute__ ((packed)) sata_fis_h2d_t;
+
+/*
+* Register - Host to Device FIS for read/write FPDMA queued
+*/
+typedef struct sata_fis_h2d_ncq {
+	u8 fis_type;
+	u8 pm_port_c;
+	u8 command;
+	u8 sector_count_low;
+	u8 lba_low;
+	u8 lba_mid;
+	u8 lba_high;
+	u8 device;
+	u8 lba_low_exp;
+	u8 lba_mid_exp;
+	u8 lba_high_exp;
+	u8 sector_count_high;
+	u8 tag;
+	u8 res1;
+	u8 res2;
+	u8 control;
+	u8 res3[4];
+} __attribute__ ((packed)) sata_fis_h2d_ncq_t;
+
+/*
+* Register - Device to Host FIS
+*/
+typedef struct sata_fis_d2h {
+	u8 fis_type;
+	u8 pm_port_i;
+	u8 status;
+	u8 error;
+	u8 lba_low;
+	u8 lba_mid;
+	u8 lba_high;
+	u8 device;
+	u8 lba_low_exp;
+	u8 lba_mid_exp;
+	u8 lba_high_exp;
+	u8 res1;
+	u8 sector_count;
+	u8 sector_count_exp;
+	u8 res2[2];
+	u8 res3[4];
+} __attribute__ ((packed)) sata_fis_d2h_t;
+
+/*
+* DMA Setup - Device to Host or Host to Device FIS
+*/
+typedef struct sata_fis_dma_setup {
+	u8 fis_type;
+	u8 pm_port_dir_int_act;
+	u8 res1;
+	u8 res2;
+	u32 dma_buffer_id_low;
+	u32 dma_buffer_id_high;
+	u32 res3;
+	u32 dma_buffer_offset;
+	u32 dma_transfer_count;
+	u32 res4;
+} __attribute__ ((packed)) sata_fis_dma_setup_t;
+
+/*
+* PIO Setup - Device to Host FIS
+*/
+typedef struct sata_fis_pio_setup {
+	u8 fis_type;
+	u8 pm_port_dir_int;
+	u8 status;
+	u8 error;
+	u8 lba_low;
+	u8 lba_mid;
+	u8 lba_high;
+	u8 res1;
+	u8 lba_low_exp;
+	u8 lba_mid_exp;
+	u8 lba_high_exp;
+	u8 res2;
+	u8 sector_count;
+	u8 sector_count_exp;
+	u8 res3;
+	u8 e_status;
+	u16 transfer_count;
+	u16 res4;
+} __attribute__ ((packed)) sata_fis_pio_setup_t;
+
+/*
+* Data - Host to Device or Device to Host FIS
+*/
+typedef struct sata_fis_data {
+	u8 fis_type;
+	u8 pm_port;
+	u8 res1;
+	u8 res2;
+	u32 data[2048];
+} __attribute__ ((packed)) sata_fis_data_t;
+
+/* fis_type - SATA FIS type
+ */
+enum sata_fis_type {
+	SATA_FIS_TYPE_REGISTER_H2D		= 0x27,
+	SATA_FIS_TYPE_REGISTER_D2H		= 0x34,
+	SATA_FIS_TYPE_DMA_ACT_D2H		= 0x39,
+	SATA_FIS_TYPE_DMA_SETUP_BI		= 0x41,
+	SATA_FIS_TYPE_DATA_BI			= 0x46,
+	SATA_FIS_TYPE_BIST_ACT_BI		= 0x58,
+	SATA_FIS_TYPE_PIO_SETUP_D2H		= 0x5F,
+	SATA_FIS_TYPE_SET_DEVICE_BITS_D2H	= 0xA1,
+};
+
+#endif	/* __FIS_H__ */
diff --git a/include/image.h b/include/image.h
index 432fa22..36143e2 100644
--- a/include/image.h
+++ b/include/image.h
@@ -1,4 +1,6 @@
 /*
+ * (C) Copyright 2008 Semihalf
+ *
  * (C) Copyright 2000-2005
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
@@ -31,6 +33,34 @@
 #ifndef __IMAGE_H__
 #define __IMAGE_H__
 
+#include <asm/byteorder.h>
+#include <command.h>
+
+#ifndef USE_HOSTCC
+#include <lmb.h>
+#include <linux/string.h>
+#include <asm/u-boot.h>
+
+#else
+
+/* new uImage format support enabled on host */
+#define CONFIG_FIT		1
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
+
+#endif /* USE_HOSTCC */
+
+#if defined(CONFIG_FIT) && !defined(CONFIG_OF_LIBFDT)
+#error "CONFIG_OF_LIBFDT not enabled, required by CONFIG_FIT!"
+#endif
+
+#if defined(CONFIG_FIT)
+#include <fdt.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#define CONFIG_MD5		/* FIT images need MD5 support */
+#endif
+
 /*
  * Operating System Codes
  */
@@ -59,25 +89,25 @@
 /*
  * CPU Architecture Codes (supported by Linux)
  */
-#define IH_CPU_INVALID		0	/* Invalid CPU	*/
-#define IH_CPU_ALPHA		1	/* Alpha	*/
-#define IH_CPU_ARM		2	/* ARM		*/
-#define IH_CPU_I386		3	/* Intel x86	*/
-#define IH_CPU_IA64		4	/* IA64		*/
-#define IH_CPU_MIPS		5	/* MIPS		*/
-#define IH_CPU_MIPS64		6	/* MIPS	 64 Bit */
-#define IH_CPU_PPC		7	/* PowerPC	*/
-#define IH_CPU_S390		8	/* IBM S390	*/
-#define IH_CPU_SH		9	/* SuperH	*/
-#define IH_CPU_SPARC		10	/* Sparc	*/
-#define IH_CPU_SPARC64		11	/* Sparc 64 Bit */
-#define IH_CPU_M68K		12	/* M68K		*/
-#define IH_CPU_NIOS		13	/* Nios-32	*/
-#define IH_CPU_MICROBLAZE	14	/* MicroBlaze   */
-#define IH_CPU_NIOS2		15	/* Nios-II	*/
-#define IH_CPU_BLACKFIN		16	/* Blackfin	*/
-#define IH_CPU_AVR32		17	/* AVR32	*/
-#define IH_CPU_ST200	        18	/* STMicroelectronics ST200  */
+#define IH_ARCH_INVALID		0	/* Invalid CPU	*/
+#define IH_ARCH_ALPHA		1	/* Alpha	*/
+#define IH_ARCH_ARM		2	/* ARM		*/
+#define IH_ARCH_I386		3	/* Intel x86	*/
+#define IH_ARCH_IA64		4	/* IA64		*/
+#define IH_ARCH_MIPS		5	/* MIPS		*/
+#define IH_ARCH_MIPS64		6	/* MIPS	 64 Bit */
+#define IH_ARCH_PPC		7	/* PowerPC	*/
+#define IH_ARCH_S390		8	/* IBM S390	*/
+#define IH_ARCH_SH		9	/* SuperH	*/
+#define IH_ARCH_SPARC		10	/* Sparc	*/
+#define IH_ARCH_SPARC64		11	/* Sparc 64 Bit */
+#define IH_ARCH_M68K		12	/* M68K		*/
+#define IH_ARCH_NIOS		13	/* Nios-32	*/
+#define IH_ARCH_MICROBLAZE	14	/* MicroBlaze   */
+#define IH_ARCH_NIOS2		15	/* Nios-II	*/
+#define IH_ARCH_BLACKFIN	16	/* Blackfin	*/
+#define IH_ARCH_AVR32		17	/* AVR32	*/
+#define IH_ARCH_ST200	        18	/* STMicroelectronics ST200  */
 
 /*
  * Image Types
@@ -139,9 +169,9 @@
 #define IH_NMLEN		32	/* Image Name Length		*/
 
 /*
- * all data in network byte order (aka natural aka bigendian)
+ * Legacy format image header,
+ * all data in network byte order (aka natural aka bigendian).
  */
-
 typedef struct image_header {
 	uint32_t	ih_magic;	/* Image Header Magic Number	*/
 	uint32_t	ih_hcrc;	/* Image Header CRC Checksum	*/
@@ -157,5 +187,412 @@ typedef struct image_header {
 	uint8_t		ih_name[IH_NMLEN];	/* Image Name		*/
 } image_header_t;
 
+/*
+ * Legacy and FIT format headers used by do_bootm() and do_bootm_<os>()
+ * routines.
+ */
+typedef struct bootm_headers {
+	/*
+	 * Legacy os image header, if it is a multi component image
+	 * then boot_get_ramdisk() and get_fdt() will attempt to get
+	 * data from second and third component accordingly.
+	 */
+	image_header_t	*legacy_hdr_os;
+	ulong		legacy_hdr_valid;
+
+#if defined(CONFIG_FIT)
+	const char	*fit_uname_cfg;	/* configuration node unit name */
+
+	void		*fit_hdr_os;	/* os FIT image header */
+	const char	*fit_uname_os;	/* os subimage node unit name */
+	int		fit_noffset_os;	/* os subimage node offset */
+
+	void		*fit_hdr_rd;	/* init ramdisk FIT image header */
+	const char	*fit_uname_rd;	/* init ramdisk subimage node unit name */
+	int		fit_noffset_rd;	/* init ramdisk subimage node offset */
+
+#if defined(CONFIG_PPC)
+	void		*fit_hdr_fdt;	/* FDT blob FIT image header */
+	const char	*fit_uname_fdt;	/* FDT blob subimage node unit name */
+	int		fit_noffset_fdt;/* FDT blob subimage node offset */
+#endif
+#endif
+
+	int		verify;		/* getenv("verify")[0] != 'n' */
+	int		autostart;	/* getenv("autostart")[0] != 'n' */
+	struct lmb	*lmb;		/* for memory mgmt */
+} bootm_headers_t;
+
+/*
+ * Some systems (for example LWMON) have very short watchdog periods;
+ * we must make sure to split long operations like memmove() or
+ * crc32() into reasonable chunks.
+ */
+#define CHUNKSZ (64 * 1024)
+
+#define uimage_to_cpu(x)		ntohl(x)
+#define cpu_to_uimage(x)		htonl(x)
+
+const char *genimg_get_os_name (uint8_t os);
+const char *genimg_get_arch_name (uint8_t arch);
+const char *genimg_get_type_name (uint8_t type);
+const char *genimg_get_comp_name (uint8_t comp);
+int genimg_get_os_id (const char *name);
+int genimg_get_arch_id (const char *name);
+int genimg_get_type_id (const char *name);
+int genimg_get_comp_id (const char *name);
+
+#ifndef USE_HOSTCC
+/* Image format types, returned by _get_format() routine */
+#define IMAGE_FORMAT_INVALID	0x00
+#define IMAGE_FORMAT_LEGACY	0x01	/* legacy image_header based format */
+#define IMAGE_FORMAT_FIT	0x02	/* new, libfdt based format */
+
+int genimg_get_format (void *img_addr);
+int genimg_has_config (bootm_headers_t *images);
+ulong genimg_get_image (ulong img_addr);
+
+int boot_get_ramdisk (int argc, char *argv[], bootm_headers_t *images,
+		uint8_t arch, ulong *rd_start, ulong *rd_end);
+
+#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
+int boot_ramdisk_high (struct lmb *lmb, ulong rd_data, ulong rd_len,
+		  ulong *initrd_start, ulong *initrd_end);
+
+int boot_get_cmdline (struct lmb *lmb, ulong *cmd_start, ulong *cmd_end,
+			ulong bootmap_base);
+int boot_get_kbd (struct lmb *lmb, bd_t **kbd, ulong bootmap_base);
+#endif /* CONFIG_PPC || CONFIG_M68K */
+#endif /* !USE_HOSTCC */
+
+/*******************************************************************/
+/* Legacy format specific code (prefixed with image_) */
+/*******************************************************************/
+static inline uint32_t image_get_header_size (void)
+{
+	return (sizeof (image_header_t));
+}
+
+#define image_get_hdr_l(f) \
+	static inline uint32_t image_get_##f(image_header_t *hdr) \
+	{ \
+		return uimage_to_cpu (hdr->ih_##f); \
+	}
+image_get_hdr_l (magic);
+image_get_hdr_l (hcrc);
+image_get_hdr_l (time);
+image_get_hdr_l (size);
+image_get_hdr_l (load);
+image_get_hdr_l (ep);
+image_get_hdr_l (dcrc);
+
+#define image_get_hdr_b(f) \
+	static inline uint8_t image_get_##f(image_header_t *hdr) \
+	{ \
+		return hdr->ih_##f; \
+	}
+image_get_hdr_b (os);
+image_get_hdr_b (arch);
+image_get_hdr_b (type);
+image_get_hdr_b (comp);
+
+static inline char *image_get_name (image_header_t *hdr)
+{
+	return (char *)hdr->ih_name;
+}
+
+static inline uint32_t image_get_data_size (image_header_t *hdr)
+{
+	return image_get_size (hdr);
+}
+
+/**
+ * image_get_data - get image payload start address
+ * @hdr: image header
+ *
+ * image_get_data() returns address of the image payload. For single
+ * component images it is image data start. For multi component
+ * images it points to the null terminated table of sub-images sizes.
+ *
+ * returns:
+ *     image payload data start address
+ */
+static inline ulong image_get_data (image_header_t *hdr)
+{
+	return ((ulong)hdr + image_get_header_size ());
+}
+
+static inline uint32_t image_get_image_size (image_header_t *hdr)
+{
+	return (image_get_size (hdr) + image_get_header_size ());
+}
+static inline ulong image_get_image_end (image_header_t *hdr)
+{
+	return ((ulong)hdr + image_get_image_size (hdr));
+}
+
+#define image_set_hdr_l(f) \
+	static inline void image_set_##f(image_header_t *hdr, uint32_t val) \
+	{ \
+		hdr->ih_##f = cpu_to_uimage (val); \
+	}
+image_set_hdr_l (magic);
+image_set_hdr_l (hcrc);
+image_set_hdr_l (time);
+image_set_hdr_l (size);
+image_set_hdr_l (load);
+image_set_hdr_l (ep);
+image_set_hdr_l (dcrc);
+
+#define image_set_hdr_b(f) \
+	static inline void image_set_##f(image_header_t *hdr, uint8_t val) \
+	{ \
+		hdr->ih_##f = val; \
+	}
+image_set_hdr_b (os);
+image_set_hdr_b (arch);
+image_set_hdr_b (type);
+image_set_hdr_b (comp);
+
+static inline void image_set_name (image_header_t *hdr, const char *name)
+{
+	strncpy (image_get_name (hdr), name, IH_NMLEN);
+}
+
+int image_check_hcrc (image_header_t *hdr);
+int image_check_dcrc (image_header_t *hdr);
+#ifndef USE_HOSTCC
+int image_check_dcrc_wd (image_header_t *hdr, ulong chunksize);
+int getenv_verify (void);
+int getenv_autostart (void);
+ulong getenv_bootm_low(void);
+ulong getenv_bootm_size(void);
+void memmove_wd (void *to, void *from, size_t len, ulong chunksz);
+#endif
+
+static inline int image_check_magic (image_header_t *hdr)
+{
+	return (image_get_magic (hdr) == IH_MAGIC);
+}
+static inline int image_check_type (image_header_t *hdr, uint8_t type)
+{
+	return (image_get_type (hdr) == type);
+}
+static inline int image_check_arch (image_header_t *hdr, uint8_t arch)
+{
+	return (image_get_arch (hdr) == arch);
+}
+static inline int image_check_os (image_header_t *hdr, uint8_t os)
+{
+	return (image_get_os (hdr) == os);
+}
+
+ulong image_multi_count (image_header_t *hdr);
+void image_multi_getimg (image_header_t *hdr, ulong idx,
+			ulong *data, ulong *len);
+
+inline void image_print_contents (image_header_t *hdr);
+inline void image_print_contents_noindent (image_header_t *hdr);
+
+#ifndef USE_HOSTCC
+static inline int image_check_target_arch (image_header_t *hdr)
+{
+#if defined(__ARM__)
+	if (!image_check_arch (hdr, IH_ARCH_ARM))
+#elif defined(__avr32__)
+	if (!image_check_arch (hdr, IH_ARCH_AVR32))
+#elif defined(__bfin__)
+	if (!image_check_arch (hdr, IH_ARCH_BLACKFIN))
+#elif defined(__I386__)
+	if (!image_check_arch (hdr, IH_ARCH_I386))
+#elif defined(__M68K__)
+	if (!image_check_arch (hdr, IH_ARCH_M68K))
+#elif defined(__microblaze__)
+	if (!image_check_arch (hdr, IH_ARCH_MICROBLAZE))
+#elif defined(__mips__)
+	if (!image_check_arch (hdr, IH_ARCH_MIPS))
+#elif defined(__nios__)
+	if (!image_check_arch (hdr, IH_ARCH_NIOS))
+#elif defined(__nios2__)
+	if (!image_check_arch (hdr, IH_ARCH_NIOS2))
+#elif defined(__PPC__)
+	if (!image_check_arch (hdr, IH_ARCH_PPC))
+#elif defined(__sh__)
+	if (!image_check_arch (hdr, IH_ARCH_SH))
+#else
+# error Unknown CPU type
+#endif
+		return 0;
+
+	return 1;
+}
+#endif /* USE_HOSTCC */
+
+/*******************************************************************/
+/* New uImage format specific code (prefixed with fit_) */
+/*******************************************************************/
+#if defined(CONFIG_FIT)
+
+#define FIT_IMAGES_PATH		"/images"
+#define FIT_CONFS_PATH		"/configurations"
+
+/* hash node */
+#define FIT_HASH_NODENAME	"hash"
+#define FIT_ALGO_PROP		"algo"
+#define FIT_VALUE_PROP		"value"
+
+/* image node */
+#define FIT_DATA_PROP		"data"
+#define FIT_TIMESTAMP_PROP	"timestamp"
+#define FIT_DESC_PROP		"description"
+#define FIT_ARCH_PROP		"arch"
+#define FIT_TYPE_PROP		"type"
+#define FIT_OS_PROP		"os"
+#define FIT_COMP_PROP		"compression"
+#define FIT_ENTRY_PROP		"entry"
+#define FIT_LOAD_PROP		"load"
+
+/* configuration node */
+#define FIT_KERNEL_PROP		"kernel"
+#define FIT_RAMDISK_PROP	"ramdisk"
+#define FIT_FDT_PROP		"fdt"
+#define FIT_DEFAULT_PROP	"default"
+
+#define FIT_MAX_HASH_LEN	20	/* max(crc32_len(4), sha1_len(20)) */
+
+/* cmdline argument format parsing */
+inline int fit_parse_conf (const char *spec, ulong addr_curr,
+		ulong *addr, const char **conf_name);
+inline int fit_parse_subimage (const char *spec, ulong addr_curr,
+		ulong *addr, const char **image_name);
+
+inline void fit_print_contents (const void *fit);
+inline void fit_print_contents_noindent (const void *fit);
+void fit_image_print (const void *fit, int noffset, const char *p);
+void fit_image_print_hash (const void *fit, int noffset, const char *p);
+
+/**
+ * fit_get_end - get FIT image size
+ * @fit: pointer to the FIT format image header
+ *
+ * returns:
+ *     size of the FIT image (blob) in memory
+ */
+static inline ulong fit_get_size (const void *fit)
+{
+	return fdt_totalsize (fit);
+}
+
+/**
+ * fit_get_end - get FIT image end
+ * @fit: pointer to the FIT format image header
+ *
+ * returns:
+ *     end address of the FIT image (blob) in memory
+ */
+static inline ulong fit_get_end (const void *fit)
+{
+	return (ulong)fit + fdt_totalsize (fit);
+}
+
+/**
+ * fit_get_name - get FIT node name
+ * @fit: pointer to the FIT format image header
+ *
+ * returns:
+ *     NULL, on error
+ *     pointer to node name, on success
+ */
+static inline const char *fit_get_name (const void *fit_hdr,
+		int noffset, int *len)
+{
+	return fdt_get_name (fit_hdr, noffset, len);
+}
+
+int fit_get_desc (const void *fit, int noffset, char **desc);
+int fit_get_timestamp (const void *fit, int noffset, time_t *timestamp);
+
+int fit_image_get_node (const void *fit, const char *image_uname);
+int fit_image_get_os (const void *fit, int noffset, uint8_t *os);
+int fit_image_get_arch (const void *fit, int noffset, uint8_t *arch);
+int fit_image_get_type (const void *fit, int noffset, uint8_t *type);
+int fit_image_get_comp (const void *fit, int noffset, uint8_t *comp);
+int fit_image_get_load (const void *fit, int noffset, ulong *load);
+int fit_image_get_entry (const void *fit, int noffset, ulong *entry);
+int fit_image_get_data (const void *fit, int noffset,
+				const void **data, size_t *size);
+
+int fit_image_hash_get_algo (const void *fit, int noffset, char **algo);
+int fit_image_hash_get_value (const void *fit, int noffset, uint8_t **value,
+				int *value_len);
+
+int fit_set_timestamp (void *fit, int noffset, time_t timestamp);
+int fit_set_hashes (void *fit);
+int fit_image_set_hashes (void *fit, int image_noffset);
+int fit_image_hash_set_value (void *fit, int noffset, uint8_t *value,
+				int value_len);
+
+int fit_image_check_hashes (const void *fit, int noffset);
+int fit_image_check_os (const void *fit, int noffset, uint8_t os);
+int fit_image_check_arch (const void *fit, int noffset, uint8_t arch);
+int fit_image_check_type (const void *fit, int noffset, uint8_t type);
+int fit_image_check_comp (const void *fit, int noffset, uint8_t comp);
+int fit_check_format (const void *fit);
+
+int fit_conf_get_node (const void *fit, const char *conf_uname);
+int fit_conf_get_kernel_node (const void *fit, int noffset);
+int fit_conf_get_ramdisk_node (const void *fit, int noffset);
+int fit_conf_get_fdt_node (const void *fit, int noffset);
+
+void fit_conf_print (const void *fit, int noffset, const char *p);
+
+#ifndef USE_HOSTCC
+static inline int fit_image_check_target_arch (const void *fdt, int node)
+{
+#if defined(__ARM__)
+	if (!fit_image_check_arch (fdt, node, IH_ARCH_ARM))
+#elif defined(__avr32__)
+	if (!fit_image_check_arch (fdt, node, IH_ARCH_AVR32))
+#elif defined(__bfin__)
+	if (!fit_image_check_arch (fdt, node, IH_ARCH_BLACKFIN))
+#elif defined(__I386__)
+	if (!fit_image_check_arch (fdt, node, IH_ARCH_I386))
+#elif defined(__M68K__)
+	if (!fit_image_check_arch (fdt, node, IH_ARCH_M68K))
+#elif defined(__microblaze__)
+	if (!fit_image_check_arch (fdt, node, IH_ARCH_MICROBLAZE))
+#elif defined(__mips__)
+	if (!fit_image_check_arch (fdt, node, IH_ARCH_MIPS))
+#elif defined(__nios__)
+	if (!fit_image_check_arch (fdt, node, IH_ARCH_NIOS))
+#elif defined(__nios2__)
+	if (!fit_image_check_arch (fdt, node, IH_ARCH_NIOS2))
+#elif defined(__PPC__)
+	if (!fit_image_check_arch (fdt, node, IH_ARCH_PPC))
+#elif defined(__sh__)
+	if (!fit_image_check_arch (fdt, node, IH_ARCH_SH))
+#else
+# error Unknown CPU type
+#endif
+		return 0;
+
+	return 1;
+}
+#endif /* USE_HOSTCC */
+
+#ifdef CONFIG_FIT_VERBOSE
+#define fit_unsupported(msg)	printf ("! %s:%d " \
+				"FIT images not supported for '%s'\n", \
+				__FILE__, __LINE__, (msg))
+
+#define fit_unsupported_reset(msg)	printf ("! %s:%d " \
+				"FIT images not supported for '%s' " \
+				"- must reset board to recover!\n", \
+				__FILE__, __LINE__, (msg))
+#else
+#define fit_unsupported(msg)
+#define fit_unsupported_reset(msg)
+#endif /* CONFIG_FIT_VERBOSE */
+#endif /* CONFIG_FIT */
 
 #endif	/* __IMAGE_H__ */
diff --git a/include/libata.h b/include/libata.h
new file mode 100644
index 0000000..aedba74
--- /dev/null
+++ b/include/libata.h
@@ -0,0 +1,205 @@
+/*
+ * Copyright (C) 2008 Freescale Semiconductor, Inc.
+ *		Dave Liu <daveliu@freescale.com>
+ *		port from libata of linux kernel
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __LIBATA_H__
+#define __LIBATA_H__
+
+#include <common.h>
+
+/* command
+ */
+enum ata_cmd {
+	/* non-NCQ command */
+	ATA_CMD_DEV_RESET		= 0x08, /* ATAPI device reset */
+	ATA_CMD_FLUSH_CACHE		= 0xE7,
+	ATA_CMD_FLUSH_CACHE_EXT		= 0xEA,
+	ATA_CMD_ID_ATA			= 0xEC,
+	ATA_CMD_ID_ATAPI		= 0xA1,
+	ATA_CMD_READ_DMA		= 0xC8,
+	ATA_CMD_READ_DMA_EXT		= 0x25,
+	ATA_CMD_WRITE_DMA		= 0xCA,
+	ATA_CMD_WRITE_DMA_EXT		= 0x35,
+	ATA_CMD_PIO_READ		= 0x20,
+	ATA_CMD_PIO_READ_EXT		= 0x24,
+	ATA_CMD_PIO_WRITE		= 0x30,
+	ATA_CMD_PIO_WRITE_EXT		= 0x34,
+	ATA_CMD_SET_FEATURES		= 0xEF,
+
+	/* NCQ command */
+	ATA_CMD_READ_FPDMA_QUEUED	= 0x60,
+	ATA_CMD_WRITE_FPDMA_QUEUED	= 0x61,
+};
+
+/* SETFEATURES stuff
+ */
+enum ata_set_features {
+	/* SETFEATURES stuff */
+	SETFEATURES_XFER	= 0x03,
+	XFER_UDMA_7		= 0x47,
+	XFER_UDMA_6		= 0x46,
+	XFER_UDMA_5		= 0x45,
+	XFER_UDMA_4		= 0x44,
+	XFER_UDMA_3		= 0x43,
+	XFER_UDMA_2		= 0x42,
+	XFER_UDMA_1		= 0x41,
+	XFER_UDMA_0		= 0x40,
+	XFER_MW_DMA_4		= 0x24, /* CFA only */
+	XFER_MW_DMA_3		= 0x23, /* CFA only */
+	XFER_MW_DMA_2		= 0x22,
+	XFER_MW_DMA_1		= 0x21,
+	XFER_MW_DMA_0		= 0x20,
+	XFER_PIO_6		= 0x0E, /* CFA only */
+	XFER_PIO_5		= 0x0D, /* CFA only */
+	XFER_PIO_4		= 0x0C,
+	XFER_PIO_3		= 0x0B,
+	XFER_PIO_2		= 0x0A,
+	XFER_PIO_1		= 0x09,
+	XFER_PIO_0		= 0x08,
+	XFER_PIO_SLOW		= 0x00,
+
+	SETFEATURES_WC_ON	= 0x02, /* Enable write cache */
+	SETFEATURES_WC_OFF	= 0x82, /* Disable write cache */
+
+	SETFEATURES_SPINUP	= 0x07, /* Spin-up drive */
+};
+
+enum ata_protocol {
+	ATA_PROT_UNKNOWN,	/* unknown */
+	ATA_PROT_NODATA,	/* no data */
+	ATA_PROT_PIO,		/* PIO data xfer */
+	ATA_PROT_DMA,		/* DMA */
+	ATA_PROT_NCQ,		/* NCQ */
+	ATA_PROT_ATAPI,		/* packet command, PIO data xfer */
+	ATA_PROT_ATAPI_NODATA,	/* packet command, no data */
+	ATA_PROT_ATAPI_DMA,	/* packet command, DMA */
+};
+
+enum ata_dev_typed {
+	ATA_DEV_ATA,		/* ATA device */
+	ATA_DEV_ATAPI,		/* ATAPI device */
+	ATA_DEV_PMP,		/* Port Multiplier Port */
+	ATA_DEV_UNKNOWN,	/* unknown */
+};
+
+enum {
+	ATA_SECT_SIZE		= 512,
+	ATA_MAX_SECTORS_128	= 128,
+	ATA_MAX_SECTORS		= 256,
+	ATA_MAX_SECTORS_LBA48	= 65535,
+
+	/* bits in ATA command block registers */
+	ATA_HOB			= (1 << 7),	/* LBA48 selector */
+	ATA_NIEN		= (1 << 1),	/* disable-irq flag */
+	ATA_LBA			= (1 << 6),	/* LBA28 selector */
+	ATA_DEV1		= (1 << 4),	/* Select Device 1 (slave) */
+	ATA_BUSY		= (1 << 7),	/* BSY status bit */
+	ATA_DRDY		= (1 << 6),	/* device ready */
+	ATA_DF			= (1 << 5),	/* device fault */
+	ATA_DRQ			= (1 << 3),	/* data request i/o */
+	ATA_ERR			= (1 << 0),	/* have an error */
+	ATA_SRST		= (1 << 2),	/* software reset */
+	ATA_ICRC		= (1 << 7),	/* interface CRC error */
+	ATA_UNC			= (1 << 6),	/* uncorrectable media error */
+	ATA_IDNF		= (1 << 4),	/* ID not found */
+	ATA_ABORTED		= (1 << 2),	/* command aborted */
+
+	ATA_ID_WORDS		= 256,
+	ATA_ID_SERNO		= 10,
+	ATA_ID_FW_REV		= 23,
+	ATA_ID_PROD		= 27,
+	ATA_ID_FIELD_VALID	= 53,
+	ATA_ID_LBA_SECTORS	= 60,
+	ATA_ID_MWDMA_MODES	= 63,
+	ATA_ID_PIO_MODES	= 64,
+	ATA_ID_QUEUE_DEPTH	= 75,
+	ATA_ID_SATA_CAP		= 76,
+	ATA_ID_SATA_FEATURES	= 78,
+	ATA_ID_SATA_FEATURES_EN	= 79,
+	ATA_ID_MAJOR_VER	= 80,
+	ATA_ID_MINOR_VER	= 81,
+	ATA_ID_UDMA_MODES	= 88,
+	ATA_ID_LBA48_SECTORS	= 100,
+
+	ATA_ID_SERNO_LEN	= 20,
+	ATA_ID_FW_REV_LEN	= 8,
+	ATA_ID_PROD_LEN		= 40,
+
+	ATA_PIO3		= (1 << 0),
+	ATA_PIO4		= ATA_PIO3 | (1 << 1),
+
+	ATA_UDMA0		= (1 << 0),
+	ATA_UDMA1		= ATA_UDMA0 | (1 << 1),
+	ATA_UDMA2		= ATA_UDMA1 | (1 << 2),
+	ATA_UDMA3		= ATA_UDMA2 | (1 << 3),
+	ATA_UDMA4		= ATA_UDMA3 | (1 << 4),
+	ATA_UDMA5		= ATA_UDMA4 | (1 << 5),
+	ATA_UDMA6		= ATA_UDMA5 | (1 << 6),
+	ATA_UDMA7		= ATA_UDMA6 | (1 << 7),
+};
+
+#define ata_id_is_ata(id)		(((id)[0] & (1 << 15)) == 0)
+#define ata_id_wcache_enabled(id)	((id)[85] & (1 << 5))
+#define ata_id_has_fua(id)		((id)[84] & (1 << 6))
+#define ata_id_has_flush(id)		((id)[83] & (1 << 12))
+#define ata_id_has_flush_ext(id)	((id)[83] & (1 << 13))
+#define ata_id_has_lba48(id)		((id)[83] & (1 << 10))
+#define ata_id_has_wcache(id)		((id)[82] & (1 << 5))
+#define ata_id_has_lba(id)		((id)[49] & (1 << 9))
+#define ata_id_has_dma(id)		((id)[49] & (1 << 8))
+#define ata_id_has_ncq(id)		((id)[76] & (1 << 8))
+#define ata_id_queue_depth(id)		(((id)[75] & 0x1f) + 1)
+
+#define ata_id_u32(id,n)	\
+	(((u32) (id)[(n) + 1] << 16) | ((u32) (id)[(n)]))
+#define ata_id_u64(id,n)	\
+	( ((u64) (id)[(n) + 3] << 48) | \
+	  ((u64) (id)[(n) + 2] << 32) | \
+	  ((u64) (id)[(n) + 1] << 16) | \
+	  ((u64) (id)[(n) + 0]) )
+
+
+static inline unsigned int ata_id_major_version(const u16 *id)
+{
+	unsigned int mver;
+
+	if (id[ATA_ID_MAJOR_VER] == 0xFFFF)
+		return 0;
+
+	for (mver = 14; mver >= 1; mver--)
+		if (id[ATA_ID_MAJOR_VER] & (1 << mver))
+			break;
+	return mver;
+}
+
+static inline int ata_id_is_sata(const u16 *id)
+{
+	return ata_id_major_version(id) >= 5 && id[93] == 0;
+}
+
+u64 ata_id_n_sectors(u16 *id);
+u32 ata_dev_classify(u32 sig);
+void ata_id_c_string(const u16 *id, unsigned char *s,
+			 unsigned int ofs, unsigned int len);
+void ata_dump_id(u16 *id);
+void ata_swap_buf_le16(u16 *buf, unsigned int buf_words);
+
+#endif /* __LIBATA_H__ */
diff --git a/include/libfdt_env.h b/include/libfdt_env.h
index 78f7258..ab5c301 100644
--- a/include/libfdt_env.h
+++ b/include/libfdt_env.h
@@ -21,11 +21,16 @@
 #ifndef _LIBFDT_ENV_H
 #define _LIBFDT_ENV_H
 
-#include <stddef.h>
-#include <linux/types.h>
-#include <asm/byteorder.h>
+#ifdef USE_HOSTCC
+#include <stdint.h>
+#include <string.h>
+#else
 #include <linux/string.h>
+#include <linux/types.h>
+#endif /* USE_HOSTCC */
 
+#include <stddef.h>
+#include <asm/byteorder.h>
 extern struct fdt_header *fdt;  /* Pointer to the working fdt */
 
 #define fdt32_to_cpu(x)		__be32_to_cpu(x)
diff --git a/include/lmb.h b/include/lmb.h
new file mode 100644
index 0000000..cc64cbb
--- /dev/null
+++ b/include/lmb.h
@@ -0,0 +1,54 @@
+#ifndef _LINUX_LMB_H
+#define _LINUX_LMB_H
+#ifdef __KERNEL__
+
+#include <asm/types.h>
+/*
+ * Logical memory blocks.
+ *
+ * Copyright (C) 2001 Peter Bergner, IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#define MAX_LMB_REGIONS 8
+
+struct lmb_property {
+	ulong base;
+	ulong size;
+};
+
+struct lmb_region {
+	unsigned long cnt;
+	ulong size;
+	struct lmb_property region[MAX_LMB_REGIONS+1];
+};
+
+struct lmb {
+	struct lmb_region memory;
+	struct lmb_region reserved;
+};
+
+extern struct lmb lmb;
+
+extern void lmb_init(struct lmb *lmb);
+extern long lmb_add(struct lmb *lmb, ulong base, ulong size);
+extern long lmb_reserve(struct lmb *lmb, ulong base, ulong size);
+extern ulong lmb_alloc(struct lmb *lmb, ulong size, ulong align);
+extern ulong lmb_alloc_base(struct lmb *lmb, ulong size, ulong align, ulong max_addr);
+extern ulong __lmb_alloc_base(struct lmb *lmb, ulong size, ulong align, ulong max_addr);
+extern int lmb_is_reserved(struct lmb *lmb, ulong addr);
+
+extern void lmb_dump_all(struct lmb *lmb);
+
+static inline ulong
+lmb_size_bytes(struct lmb_region *type, unsigned long region_nr)
+{
+	return type->region[region_nr].size;
+}
+#endif /* __KERNEL__ */
+
+#endif /* _LINUX_LMB_H */
diff --git a/include/md5.h b/include/md5.h
new file mode 100644
index 0000000..046d1ee
--- /dev/null
+++ b/include/md5.h
@@ -0,0 +1,23 @@
+/*
+ * This file was transplanted with slight modifications from Linux sources
+ * (fs/cifs/md5.h) into U-Boot by Bartlomiej Sieka <tur@semihalf.com>.
+ */
+
+#ifndef _MD5_H
+#define _MD5_H
+
+#include <linux/types.h>
+
+struct MD5Context {
+	__u32 buf[4];
+	__u32 bits[2];
+	unsigned char in[64];
+};
+
+/*
+ * Calculate and store in 'output' the MD5 digest of 'len' bytes at
+ * 'input'. 'output' must have enough space to hold 16 bytes.
+ */
+void md5 (unsigned char *input, int len, unsigned char output[16]);
+
+#endif /* _MD5_H */
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index df052e3..4ee38aa 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -121,6 +121,7 @@
 #define SPCR_PCIPR			0x03000000	/* PCI bridge system bus request priority */
 #define SPCR_PCIPR_SHIFT		(31-7)
 #define SPCR_OPT			0x00800000	/* Optimize */
+#define SPCR_OPT_SHIFT			(31-8)
 #define SPCR_TBEN			0x00400000	/* E300 PowerPC core time base unit enable */
 #define SPCR_TBEN_SHIFT			(31-9)
 #define SPCR_COREPR			0x00300000	/* E300 PowerPC Core system bus request priority */
@@ -880,7 +881,7 @@
 #define TIMING_CFG0_PRE_PD_EXIT_SHIFT	16
 #define TIMING_CFG0_ODT_PD_EXIT		0x00000F00
 #define TIMING_CFG0_ODT_PD_EXIT_SHIFT	8
-#define TIMING_CFG0_MRS_CYC		0x00000F00
+#define TIMING_CFG0_MRS_CYC		0x0000000F
 #define TIMING_CFG0_MRS_CYC_SHIFT	0
 
 /* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
@@ -903,6 +904,7 @@
 #define TIMING_CFG1_WRTORD_SHIFT	0
 #define TIMING_CFG1_CASLAT_20		0x00030000	/* CAS latency = 2.0 */
 #define TIMING_CFG1_CASLAT_25		0x00040000	/* CAS latency = 2.5 */
+#define TIMING_CFG1_CASLAT_30		0x00050000	/* CAS latency = 2.5 */
 
 /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
  */
diff --git a/include/part.h b/include/part.h
index 8407aa0..b22a637 100644
--- a/include/part.h
+++ b/include/part.h
@@ -27,8 +27,8 @@
 
 typedef struct block_dev_desc {
 	int		if_type;	/* type of the interface */
-	int	        dev;	  	/* device number */
-	unsigned char	part_type;  	/* partition type */
+	int		dev;		/* device number */
+	unsigned char	part_type;	/* partition type */
 	unsigned char	target;		/* target SCSI ID */
 	unsigned char	lun;		/* target LUN */
 	unsigned char	type;		/* device type */
@@ -36,9 +36,9 @@ typedef struct block_dev_desc {
 #ifdef CONFIG_LBA48
 	unsigned char	lba48;		/* device can use 48bit addr (ATA/ATAPI v7) */
 #endif
-	lbaint_t		lba;	  	/* number of blocks */
+	lbaint_t		lba;		/* number of blocks */
 	unsigned long	blksz;		/* block size */
-	char		vendor [40+1]; 	/* IDE model, SCSI Vendor */
+	char		vendor [40+1];	/* IDE model, SCSI Vendor */
 	char		product[20+1];	/* IDE Serial no, SCSI product */
 	char		revision[8+1];	/* firmware revision */
 	unsigned long	(*block_read)(int dev,
@@ -49,6 +49,7 @@ typedef struct block_dev_desc {
 				       unsigned long start,
 				       lbaint_t blkcnt,
 				       const void *buffer);
+	void		*priv;		/* driver private struct pointer */
 }block_dev_desc_t;
 
 /* Interface types: */
@@ -60,6 +61,7 @@ typedef struct block_dev_desc {
 #define IF_TYPE_DOC		5
 #define IF_TYPE_MMC		6
 #define IF_TYPE_SD		7
+#define IF_TYPE_SATA		8
 
 /* Part types */
 #define PART_TYPE_UNKNOWN	0x00
@@ -92,6 +94,7 @@ typedef struct disk_partition {
 /* Misc _get_dev functions */
 block_dev_desc_t* get_dev(char* ifname, int dev);
 block_dev_desc_t* ide_get_dev(int dev);
+block_dev_desc_t* sata_get_dev(int dev);
 block_dev_desc_t* scsi_get_dev(int dev);
 block_dev_desc_t* usb_stor_get_dev(int dev);
 block_dev_desc_t* mmc_get_dev(int dev);
diff --git a/include/pci_ids.h b/include/pci_ids.h
index 3b10452..b0c1957 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -2050,3 +2050,26 @@
 #define PCI_DEVICE_ID_MICROGATE_USC	0x0010
 #define PCI_DEVICE_ID_MICROGATE_SCC	0x0020
 #define PCI_DEVICE_ID_MICROGATE_SCA	0x0030
+
+#define PCI_VENDOR_ID_FREESCALE		0x1957
+#define PCI_DEVICE_ID_MPC8548E		0x0012
+#define PCI_DEVICE_ID_MPC8548		0x0013
+#define PCI_DEVICE_ID_MPC8543E		0x0014
+#define PCI_DEVICE_ID_MPC8543		0x0015
+#define PCI_DEVICE_ID_MPC8547E		0x0018
+#define PCI_DEVICE_ID_MPC8545E		0x0019
+#define PCI_DEVICE_ID_MPC8545		0x001a
+#define PCI_DEVICE_ID_MPC8568E		0x0020
+#define PCI_DEVICE_ID_MPC8568		0x0021
+#define PCI_DEVICE_ID_MPC8567E		0x0022
+#define PCI_DEVICE_ID_MPC8567		0x0023
+#define PCI_DEVICE_ID_MPC8533E		0x0030
+#define PCI_DEVICE_ID_MPC8533		0x0031
+#define PCI_DEVICE_ID_MPC8544E		0x0032
+#define PCI_DEVICE_ID_MPC8544		0x0033
+#define PCI_DEVICE_ID_MPC8572E		0x0040
+#define PCI_DEVICE_ID_MPC8572		0x0041
+#define PCI_DEVICE_ID_MPC8641		0x7010
+#define PCI_DEVICE_ID_MPC8641D		0x7011
+#define PCI_DEVICE_ID_MPC8610		0x7018
+
diff --git a/include/sata.h b/include/sata.h
index 165b471..b4b7029 100644
--- a/include/sata.h
+++ b/include/sata.h
@@ -1,108 +1,6 @@
+int init_sata(int dev);
+int scan_sata(int dev);
+ulong sata_read(int dev, ulong blknr, ulong blkcnt, void *buffer);
+ulong sata_write(int dev, ulong blknr, ulong blkcnt, const void *buffer);
 
-#if (DEBUG_SATA)
-#define PRINTF(fmt,args...)	printf (fmt ,##args)
-#else
-#define PRINTF(fmt,args...)
-#endif
-
-struct sata_ioports {
-	unsigned long cmd_addr;
-	unsigned long data_addr;
-	unsigned long error_addr;
-	unsigned long feature_addr;
-	unsigned long nsect_addr;
-	unsigned long lbal_addr;
-	unsigned long lbam_addr;
-	unsigned long lbah_addr;
-	unsigned long device_addr;
-	unsigned long status_addr;
-	unsigned long command_addr;
-	unsigned long altstatus_addr;
-	unsigned long ctl_addr;
-	unsigned long bmdma_addr;
-	unsigned long scr_addr;
-};
-
-struct sata_port {
-	unsigned char port_no;		/* primary=0, secondary=1	*/
-	struct sata_ioports ioaddr;	/* ATA cmd/ctl/dma reg blks	*/
-	unsigned char ctl_reg;
-	unsigned char last_ctl;
-	unsigned char port_state;	/* 1-port is available and	*/
-					/* 0-port is not available	*/
-	unsigned char dev_mask;
-};
-
-/***********SATA LIBRARY SPECIFIC DEFINITIONS AND DECLARATIONS**************/
-#ifdef SATA_DECL		/*SATA library specific declarations */
-#define ata_id_has_lba48(id)    ((id)[83] & (1 << 10))
-#define ata_id_has_lba(id)      ((id)[49] & (1 << 9))
-#define ata_id_has_dma(id)      ((id)[49] & (1 << 8))
-#define ata_id_u32(id,n)        \
-	(((u32) (id)[(n) + 1] << 16) | ((u32) (id)[(n)]))
-#define ata_id_u64(id,n)        \
-	(((u64) (id)[(n) + 3] << 48) | \
-	((u64) (id)[(n) + 2] << 32) | \
-	((u64) (id)[(n) + 1] << 16) | \
-	((u64) (id)[(n) + 0]) )
-#endif
-
-#ifdef SATA_DECL		/*SATA library specific declarations */
-static inline void
-ata_dump_id (u16 * id)
-{
-	PRINTF ("49==0x%04x  "
-		"53==0x%04x  "
-		"63==0x%04x  "
-		"64==0x%04x  "
-		"75==0x%04x  \n", id[49], id[53], id[63], id[64], id[75]);
-	PRINTF ("80==0x%04x  "
-		"81==0x%04x  "
-		"82==0x%04x  "
-		"83==0x%04x  "
-		"84==0x%04x  \n", id[80], id[81], id[82], id[83], id[84]);
-	PRINTF ("88==0x%04x  " "93==0x%04x\n", id[88], id[93]);
-}
-#endif
-
-#ifdef SATA_DECL		/*SATA library specific declarations */
-int sata_bus_softreset (int num);
-void sata_identify (int num, int dev);
-void sata_port (struct sata_ioports *ioport);
-void set_Feature_cmd (int num, int dev);
-int sata_devchk (struct sata_ioports *ioaddr, int dev);
-void dev_select (struct sata_ioports *ioaddr, int dev);
-u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits, unsigned int max);
-u8 sata_chk_status (struct sata_ioports *ioaddr);
-ulong sata_read (int device, ulong blknr,lbaint_t blkcnt, void * buffer);
-ulong sata_write (int device,ulong blknr, lbaint_t blkcnt, void * buffer);
-void msleep (int count);
-#else
-extern int sata_bus_softreset (int num);
-extern void sata_identify (int num, int dev);
-extern void sata_port (struct sata_ioports *ioport);
-extern void set_Feature_cmd (int num, int dev);
-extern ulong sata_read (int device, ulong blknr,
-			lbaint_t blkcnt, void * buffer);
-extern ulong sata_write (int device, ulong blknr,
-			lbaint_t blkcnt, void * buffer);
-extern void msleep (int count);
-#endif
-
-/************DRIVER SPECIFIC DEFINITIONS AND DECLARATIONS**************/
-
-#ifdef DRV_DECL			/*Driver specific declaration */
-int init_sata (void);
-#else
-extern int init_sata (void);
-#endif
-
-#ifdef DRV_DECL			/*Defines Driver Specific variables */
-struct sata_port port[CFG_SATA_MAXBUS];
-block_dev_desc_t sata_dev_desc[CFG_SATA_MAXDEVICES];
-int curr_dev = -1;
-#else
-extern struct sata_port port[CFG_SATA_MAXBUS];
-extern block_dev_desc_t sata_dev_desc[CFG_SATA_MAXDEVICES];
-extern int curr_dev;
-#endif
+int sata_initialize(void);
diff --git a/include/usb.h b/include/usb.h
index 4e1539f..5a6ffdd 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -195,7 +195,7 @@ void usb_event_poll(void);
 #define USB_MAX_STOR_DEV 5
 block_dev_desc_t *usb_stor_get_dev(int index);
 int usb_stor_scan(int mode);
-void usb_stor_info(void);
+int usb_stor_info(void);
 
 #endif
 
diff --git a/include/vsc7385.h b/include/vsc7385.h
new file mode 100644
index 0000000..fceb078
--- /dev/null
+++ b/include/vsc7385.h
@@ -0,0 +1,12 @@
+/*
+ * Header file for vsc7385.c
+ *
+ * Author: Timur Tabi <timur@freescale.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc.  This file is licensed
+ * under the terms of the GNU General Public License version 2.  This
+ * program is licensed "as is" without any warranty of any kind, whether
+ * express or implied.
+ */
+
+int vsc7385_upload_firmware(void *firmware, unsigned int size);