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authorDave Liu <daveliu@freescale.com>2008-11-21 16:31:29 +0800
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2009-01-23 17:03:13 -0600
commit22ff3d01348e0a2dc369b7efcbac30e4ce86d178 (patch)
treee3ed66edb226e004cc85cdc4d4a966c55ce4f141 /include
parent80ee3ce6d7fe9441b4352d7cfaf6afc2507b1106 (diff)
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fsl-ddr: clean up the ddr code for DDR3 controller
- The DDR3 controller is expanding the bits for timing config - Add the DDR3 32-bit bus mode support Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'include')
-rw-r--r--include/asm-ppc/fsl_ddr_sdram.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h
index c1ea7cd..0006c21 100644
--- a/include/asm-ppc/fsl_ddr_sdram.h
+++ b/include/asm-ppc/fsl_ddr_sdram.h
@@ -34,7 +34,10 @@ typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
#elif defined(CONFIG_FSL_DDR3)
#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */
typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
+#ifndef CONFIG_FSL_SDRAM_TYPE
+#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3
#endif
+#endif /* #if defined(CONFIG_FSL_DDR1) */
/* define bank(chip select) interleaving mode */
#define FSL_DDR_CS0_CS1 0x40