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authorWolfgang Denk <wd@denx.de>2010-12-16 23:00:53 +0100
committerWolfgang Denk <wd@denx.de>2010-12-16 23:00:53 +0100
commit006915fbb0e3c1c9927fe32c4e92cb011f8499e7 (patch)
treeb477df920f7d638a0472aa1d6bfa5ff71243448c /include
parent98e69567022eb2138dd99554b3a2e80522a1b153 (diff)
parentb5d58d8500bfb918c7fec56f241e6ee1078c2be0 (diff)
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Merge branch 'master' of ../master into next
Diffstat (limited to 'include')
-rw-r--r--include/configs/MPC8360EMDS.h4
-rw-r--r--include/configs/MPC8536DS.h5
-rw-r--r--include/configs/MPC8569MDS.h3
-rw-r--r--include/configs/MPC8572DS.h1
-rw-r--r--include/configs/P1_P2_RDB.h13
-rw-r--r--include/configs/am3517_evm.h7
-rw-r--r--include/configs/aria.h1
-rw-r--r--include/configs/at91rm9200ek.h18
-rw-r--r--include/configs/atngw100.h2
-rw-r--r--include/configs/davinci_dvevm.h19
-rw-r--r--include/configs/igep0030.h1
-rw-r--r--include/configs/mimc200.h2
-rw-r--r--include/configs/mx51evk.h7
-rw-r--r--include/configs/omap3_evm.h6
-rw-r--r--include/configs/omap3_sdp3430.h6
-rw-r--r--include/configs/omap3_zoom1.h6
-rw-r--r--include/configs/omap3_zoom2.h6
-rw-r--r--include/configs/omap4_sdp4430.h1
-rw-r--r--include/configs/pm9261.h7
-rw-r--r--include/configs/pm9263.h7
-rw-r--r--include/configs/pm9g45.h7
-rw-r--r--include/configs/r7780mp.h1
-rw-r--r--include/configs/s5p_goni.h2
-rw-r--r--include/configs/smdkc100.h2
-rw-r--r--include/configs/top9000.h314
-rw-r--r--include/configs/xpedite537x.h10
-rw-r--r--include/configs/xpedite550x.h10
-rw-r--r--include/linux/mii.h181
-rw-r--r--include/pci_ids.h1
-rw-r--r--include/post.h6
30 files changed, 546 insertions, 110 deletions
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index 7b82c43..a959940 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -296,13 +296,13 @@
/*
* CS4 on Local Bus, to PIB
*/
-#define CONFIG_SYS_BR4_PRELIM 0xf8010801 /* CS4 base address at 0xf8010000 */
+#define CONFIG_SYS_BR4_PRELIM 0xf8008801 /* CS4 base address at 0xf8008000 */
#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
/*
* CS5 on Local Bus, to PIB
*/
-#define CONFIG_SYS_BR5_PRELIM 0xf8008801 /* CS5 base address at 0xf8008000 */
+#define CONFIG_SYS_BR5_PRELIM 0xf8010801 /* CS5 base address at 0xf8010000 */
#define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
/*
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 850665a..5c5be0c 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -242,9 +242,10 @@
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \
- || defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
+#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
+ defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
#else
#undef CONFIG_SYS_RAMBOOT
#endif
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index c7973b4..9620fd0 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -203,8 +203,9 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND)
+#if defined(CONFIG_RAMBOOT_NAND)
#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
#else
#undef CONFIG_SYS_RAMBOOT
#endif
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 692c811..1ee95ae 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -202,6 +202,7 @@
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
+#define CONFIG_HWCONFIG /* enable hwconfig */
#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
#ifdef CONFIG_PHYS_64BIT
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index 610f3ed..2dfee3d 100644
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -201,9 +201,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \
- || defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
+#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
+ defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
#else
#undef CONFIG_SYS_RAMBOOT
#endif
@@ -436,14 +437,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-/* TBI PHY configuration for SGMII mode */
-#define CONFIG_TSEC_TBICR_SETTINGS ( \
- TBICR_PHY_RESET \
- | TBICR_ANEG_ENABLE \
- | TBICR_FULL_DUPLEX \
- | TBICR_SPEED1_SET \
- )
-
#endif /* CONFIG_TSEC_ENET */
/*
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 9a9ba88..70e8f07 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -163,6 +163,7 @@
#define CONFIG_DRIVER_OMAP34XX_I2C 1
#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
/*
* Board NAND Info.
*/
@@ -330,4 +331,10 @@ extern unsigned int boot_flash_sec;
extern unsigned int boot_flash_type;
#endif
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */
diff --git a/include/configs/aria.h b/include/configs/aria.h
index b3ca8d2..3a60de0 100644
--- a/include/configs/aria.h
+++ b/include/configs/aria.h
@@ -49,7 +49,6 @@
#define CONFIG_E300 1 /* E300 Family */
#define CONFIG_MPC512X 1 /* MPC512X family */
#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
-#define CONFIG_FSL_DIU_LOGO_BMP 1 /* Don't include FSL DIU binary bmp */
#define CONFIG_SYS_TEXT_BASE 0xFFF00000
diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h
index 14559f5..810023a 100644
--- a/include/configs/at91rm9200ek.h
+++ b/include/configs/at91rm9200ek.h
@@ -33,6 +33,20 @@
#include <asm/sizes.h>
/*
+ * set some initial configurations depending on configure target
+ *
+ * at91rm9200ek_config -> boot from 0x0 in NOR Flash at CS0
+ * at91rm9200ek_ram_config -> continue booting from 0x20100000 in RAM; lowlevel
+ * initialisation was done by some preloader
+ */
+#ifdef CONFIG_RAMBOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE 0x20100000
+#else
+#define CONFIG_SYS_TEXT_BASE 0x10000000
+#endif
+
+/*
* AT91C_XTAL_CLOCK is the frequency of external xtal in hertz
* AT91C_MAIN_CLOCK is the frequency of PLLA output
* AT91C_MASTER_CLOCK is the peripherial clock
@@ -57,6 +71,8 @@
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
+#define CONFIG_AT91FAMILY
+
/*
* Memory Configuration
*/
@@ -90,7 +106,7 @@
#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */
#define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
-#define CONFIG_SYS_SDRAM1 CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
+#define CONFIG_SYS_SDRAM1 (CONFIG_SYS_SDRAM_BASE+0x80)
#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h
index 83056b6..92491ca 100644
--- a/include/configs/atngw100.h
+++ b/include/configs/atngw100.h
@@ -104,8 +104,6 @@
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_DOS_PARTITION 1
-
/*
* Command line configuration.
*/
diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h
index e1b1db1..45214fa 100644
--- a/include/configs/davinci_dvevm.h
+++ b/include/configs/davinci_dvevm.h
@@ -50,7 +50,7 @@
/*=======*/
#define DV_EVM
#define CONFIG_SYS_NAND_SMALLPAGE
-#define CONFIG_SYS_USE_NOR
+#define CONFIG_SYS_USE_NAND
#define CONFIG_DISPLAY_CPUINFO
/*===================*/
/* SoC Configuration */
@@ -78,6 +78,7 @@
#define CONFIG_STACKSIZE (256*1024) /* regular stack */
#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
#define PHYS_SDRAM_1_SIZE 0x10000000 /* DDR size 256MB */
+
#define DDR_8BANKS /* 8-bank DDR2 (256MB) */
/*====================*/
/* Serial Driver info */
@@ -228,11 +229,13 @@
#define CONFIG_PREBOOT "usb start"
#endif
#endif
-/*=======================*/
-/* KGDB support (if any) */
-/*=======================*/
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
-#endif
+
+#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
#endif /* __CONFIG_H */
diff --git a/include/configs/igep0030.h b/include/configs/igep0030.h
index d61793c..1325bfa 100644
--- a/include/configs/igep0030.h
+++ b/include/configs/igep0030.h
@@ -110,6 +110,7 @@
#define CONFIG_MTD_DEVICE
#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+#undef CONFIG_CMD_NFS /* nfs */
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
#undef CONFIG_CMD_IMLS /* List all found images */
diff --git a/include/configs/mimc200.h b/include/configs/mimc200.h
index 6ed9e75..16e2ec6 100644
--- a/include/configs/mimc200.h
+++ b/include/configs/mimc200.h
@@ -109,8 +109,6 @@
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_DOS_PARTITION 1
-
/*
* Command line configuration.
*/
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index f98438d..b4e5738 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -216,8 +216,9 @@
*/
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_SECT_SIZE (128 * 1024)
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
+#define CONFIG_ENV_SIZE (8 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 84b2986..5bdb3fd 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -330,7 +330,11 @@ extern unsigned int boot_flash_type;
* Support for relocation
*/
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
/*
* Define the board revision statically
diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h
index a5eb648..4708981 100644
--- a/include/configs/omap3_sdp3430.h
+++ b/include/configs/omap3_sdp3430.h
@@ -309,6 +309,12 @@
#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */
#endif
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
/*
* SDRAM Memory Map
*/
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index d9e8ea0..f7d0652 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -236,6 +236,12 @@
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
/* load address */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
/*
* OMAP3 has 12 GP timers, they can be driven by the system clock
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h
index 41abe04..7377933 100644
--- a/include/configs/omap3_zoom2.h
+++ b/include/configs/omap3_zoom2.h
@@ -188,6 +188,12 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"usbtty=cdc_acm\0" \
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
/*
* Miscellaneous configurable options
*/
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index bdd330a..9a8bb73 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -140,6 +140,7 @@
/* Disabled commands */
#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
#undef CONFIG_CMD_IMLS /* List all found images */
diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h
index 7fcc9ba..26e5049 100644
--- a/include/configs/pm9261.h
+++ b/include/configs/pm9261.h
@@ -45,6 +45,8 @@
#define CONFIG_PM9261 1 /* on a Ronetix PM9261 Board */
#define CONFIG_ARCH_CPU_INIT
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+#define CONFIG_SYS_TEXT_BASE 0
+#define CONFIG_AT91FAMILY
/* clocks */
/* CKGR_MOR - enable main osc. */
@@ -201,6 +203,7 @@
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_CACHE
#define CONFIG_CMD_PING 1
#define CONFIG_CMD_DHCP 1
#define CONFIG_CMD_NAND 1
@@ -370,6 +373,10 @@
#define CONFIG_SYS_MALLOC_LEN \
ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+ GENERATED_GBL_DATA_SIZE)
+
#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index 619af2d..96e12f2 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -44,6 +44,8 @@
#define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */
#define CONFIG_ARCH_CPU_INIT
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+#define CONFIG_SYS_TEXT_BASE 0
+#define CONFIG_AT91FAMILY
/* clocks */
#define CONFIG_SYS_MOR_VAL \
@@ -212,6 +214,7 @@
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_CACHE
#define CONFIG_CMD_PING 1
#define CONFIG_CMD_DHCP 1
#define CONFIG_CMD_NAND 1
@@ -401,6 +404,10 @@
*/
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+ GENERATED_GBL_DATA_SIZE)
+
#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
index 3ed6b56..ec51ccf 100644
--- a/include/configs/pm9g45.h
+++ b/include/configs/pm9g45.h
@@ -39,6 +39,8 @@
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_TEXT_BASE 0x73f00000
+#define CONFIG_AT91FAMILY
#define CONFIG_ARCH_CPU_INIT
@@ -79,6 +81,7 @@
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_CACHE
#define CONFIG_CMD_PING 1
#define CONFIG_CMD_DHCP 1
#define CONFIG_CMD_NAND 1
@@ -175,6 +178,10 @@
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024,\
0x1000)
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+ GENERATED_GBL_DATA_SIZE)
+
#define CONFIG_STACKSIZE (32*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h
index 3416cb8..802416f 100644
--- a/include/configs/r7780mp.h
+++ b/include/configs/r7780mp.h
@@ -154,7 +154,6 @@
#define CONFIG_RTL8169
*/
/* AX88796L Support(NE2000 base chip) */
-#define CONFIG_DRIVER_NE2000
#define CONFIG_DRIVER_AX88796L
#define CONFIG_DRIVER_NE2000_BASE 0xA4100000
#endif
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index 541aec0..f53e798 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -217,4 +217,6 @@
#define CONFIG_DOS_PARTITION 1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
+
#endif /* __CONFIG_H */
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index e36b262..fb8b43c 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -231,6 +231,8 @@
#define CONFIG_DOS_PARTITION 1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
+
/*
* Ethernet Contoller driver
*/
diff --git a/include/configs/top9000.h b/include/configs/top9000.h
new file mode 100644
index 0000000..ff3933b
--- /dev/null
+++ b/include/configs/top9000.h
@@ -0,0 +1,314 @@
+/*
+ * (C) Copyright 2010
+ * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
+ *
+ * Configuation settings for the TOP9000 CPU module with AT91SAM9XE.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/*
+ * top9000 with at91sam9xe256 or at91sam9xe512
+ *
+ * Initial Bootloader is in embedded flash.
+ * Vital Product Data, U-Boot Environment are in I2C-EEPROM.
+ * U-Boot is in embedded flash, a backup U-Boot can be in NAND flash.
+ * kernel and file system are either in NAND flash or on a micro SD card.
+ * NAND flash is optional.
+ * I2C EEPROM is never optional.
+ * SPI FRAM is optional.
+ * SPI ENC28J60 is optional.
+ * 16 or 32 bit wide SDRAM.
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Warning: changing CONFIG_SYS_TEXT_BASE requires
+ * adapting the initial boot program
+ */
+#define CONFIG_SYS_TEXT_BASE 0x21f00000 /* 31 MB into RAM */
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+#define CONFIG_CMD_ASKENV
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_PROMPT "TOP9000> "
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_CACHE
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz xtal */
+#define CONFIG_SYS_HZ 1000
+
+/* SoC */
+#define CONFIG_ARM926EJS /* ARM926EJS Core */
+#define CONFIG_AT91FAMILY /* it's a member of AT91 */
+#define CONFIG_AT91SAM9260 /* Atmel AT91SAM9260 based SoC */
+#define CONFIG_AT91SAM9XE
+
+/* Misc CPU related */
+#define CONFIG_AT91_LEGACY
+#define CONFIG_ARCH_CPU_INIT
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_AT91RESET_EXTRST /* assert external reset */
+
+/* general purpose I/O */
+#define CONFIG_AT91_GPIO
+#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART3 /* USART 3 is DBGU !!! */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
+
+/* SD/MMC card */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#define CONFIG_SYS_MMC_CD_PIN AT91_PIN_PC9
+#define CONFIG_CMD_MMC
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_SYS_PHY_ID 1
+#define CONFIG_RMII
+#define CONFIG_NET_MULTI
+#define CONFIG_NET_RETRY_COUNT 20
+
+/* real time clock */
+#define CONFIG_RTC_AT91SAM9_RTT
+#define CONFIG_CMD_DATE
+
+#if defined(CONFIG_AT91SAM9XE)
+/*
+ * NOR flash - use embedded flash of SAM9XE256/512
+ * U-Boot will not fit into 128K !
+ * 2010.09 will not fit into 256K with all options enabled !
+ *
+ * Layout:
+ * 16kB 1st Bootloader
+ * Rest U-Boot
+ * the first sector (16kB) of EFLASH cannot be unprotected
+ * with u-boot commands
+ */
+# define CONFIG_AT91_EFLASH
+# define CONFIG_SYS_FLASH_BASE 0x200000
+# define CONFIG_SYS_MAX_FLASH_SECT 32
+# define CONFIG_SYS_MAX_FLASH_BANKS 1
+# define CONFIG_SYS_FLASH_PROTECTION
+# define CONFIG_EFLASH_PROTSECTORS 1 /* protect first sector */
+#endif
+
+/* SPI */
+#define CONFIG_ATMEL_SPI
+#define CONFIG_CMD_SPI
+
+/* RAMTRON FRAM */
+#define CONFIG_CMD_SF
+#define CONFIG_ATMEL_SPI0 /* SPI used for FRAM is SPI0 */
+#define FRAM_SPI_BUS 0
+#define FRAM_CS_NUM 0
+#define CONFIG_SPI_FLASH /* RAMTRON FRAM on SPI bus */
+#define CONFIG_SPI_FRAM_RAMTRON
+#define CONFIG_SF_DEFAULT_SPEED 1000000 /* be conservative here... */
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC "FM25H20"
+
+/* Microchip ENC28J60 (second LAN) */
+#if defined(CONFIG_EVAL9000)
+# define CONFIG_ENC28J60
+# define CONFIG_ATMEL_SPI1 /* SPI used for ENC28J60 is SPI1 */
+# define ENC_SPI_BUS 1
+# define ENC_CS_NUM 0
+# define ENC_SPI_CLOCK 1000000
+#endif /* CONFIG_EVAL9000 */
+
+/*
+ * SDRAM: 1 bank, min 32, max 128 MB
+ * Initialized before u-boot gets started.
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CONFIG_SYS_SDRAM_SIZE 0x08000000
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END 0x21e00000
+#define CONFIG_SYS_LOAD_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + 0x01000000)
+/*
+ * Initial stack pointer: 16k - GENERATED_GBL_DATA_SIZE in internal SRAM,
+ * leaving the correct space for initial global data structure above
+ * that address while providing maximum stack area below.
+ */
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (0x00300000 + 0x4000 - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * NAND flash: 256 MB (optional)
+ *
+ * Layout:
+ * 640kB: u-boot (includes space for spare sectors, handled by
+ * initial loader)
+ * 2MB: kernel
+ * rest: file system
+ */
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CONFIG_SYS_NAND_DBW_8
+#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
+#define CONFIG_CMD_NAND
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "top9000"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* I2C support must always be enabled */
+#define CONFIG_SOFT_I2C
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C_SPEED 400000
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_I2C_MULTI_BUS
+#define I2C0_PORT AT91_PIO_PORTA
+#define SDA0_PIN 23
+#define SCL0_PIN 24
+#define I2C1_PORT AT91_PIO_PORTB
+#define SDA1_PIN 12
+#define SCL1_PIN 13
+#define I2C_SOFT_DECLARATIONS void iic_init(void);\
+ int iic_read(void);\
+ void iic_sda(int);\
+ void iic_scl(int);
+#define I2C_ACTIVE
+#define I2C_TRISTATE
+#define I2C_INIT iic_init()
+#define I2C_READ iic_read()
+#define I2C_SDA(bit) iic_sda(bit)
+#define I2C_SCL(bit) iic_scl(bit)
+#define I2C_DELAY udelay(3)
+/* EEPROM configuration */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_SIZE 0x2000
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+/* later: #define CONFIG_I2C_ENV_EEPROM_BUS 0 */
+/* ENV is always in I2C-EEPROM */
+#define CONFIG_ENV_IS_IN_EEPROM
+#define CONFIG_ENV_OFFSET 0x1000
+#define CONFIG_ENV_SIZE 0x0f00
+/* VPD settings */
+#define CONFIG_SYS_I2C_FACT_ADDR 0x57
+#define CONFIG_SYS_FACT_OFFSET 0x1F00
+#define CONFIG_SYS_FACT_SIZE 0x0100
+/* later: #define CONFIG_MISC_INIT_R */
+/* define the next only if you want to allow users to enter VPD data */
+#define CONFIG_SYS_FACT_ENTRY
+#ifndef __ASSEMBLY__
+extern void read_factory_r(void);
+#endif
+
+/*
+ * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
+ * data on the serial line may interrupt the boot sequence.
+ */
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_AUTOBOOT
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT \
+ "Press SPACE to abort autoboot in %d seconds\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR "d"
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+/*
+ * add filesystem commands if we have at least 1 storage
+ * media with filesystem
+ */
+#if defined(CONFIG_NAND_ATMEL) \
+ || defined(CONFIG_USB_ATMEL) \
+ || defined(CONFIG_MMC)
+# define CONFIG_DOS_PARTITION
+# define CONFIG_CMD_FAT
+# define CONFIG_CMD_EXT2
+/* later: #define CONFIG_CMD_JFFS2 */
+#endif
+
+/* add NET commands if we have at least 1 LAN */
+#if defined(CONFIG_MACB) || defined(CONFIG_ENC28J60)
+# define CONFIG_CMD_PING
+# define CONFIG_CMD_DHCP
+# define CONFIG_CMD_MII
+/* is this really needed ? */
+# define CONFIG_RESET_PHY_R
+/* BOOTP options */
+# define CONFIG_BOOTP_BOOTFILESIZE
+# define CONFIG_BOOTP_BOOTPATH
+# define CONFIG_BOOTP_GATEWAY
+# define CONFIG_BOOTP_HOSTNAME
+#endif
+
+/* linux in NAND flash */
+#define CONFIG_BOOTCOUNT_LIMIT 1
+#define CONFIG_BOOTCOMMAND \
+ "nand read 0x21000000 0xA0000 0x200000; bootm"
+#define CONFIG_BOOTARGS \
+ "console=ttyS0,115200 " \
+ "root=/dev/mtdblock2 " \
+ "mtdparts=atmel_nand:" \
+ "640k(uboot)ro," \
+ "2M(linux)," \
+ "16M(root)," \
+ "-(rest) " \
+ "rw "\
+ "rootfstype=jffs2"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN \
+ ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+#define CONFIG_STACKSIZE (32*1024)
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
+
diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h
index e0a1fa4..a74766d 100644
--- a/include/configs/xpedite537x.h
+++ b/include/configs/xpedite537x.h
@@ -375,6 +375,16 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
#define CONFIG_ETHPRIME "eTSEC2"
+/*
+ * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
+ * 1000mbps SGMII link
+ */
+#define CONFIG_TSEC_TBICR_SETTINGS ( \
+ TBICR_PHY_RESET \
+ | TBICR_FULL_DUPLEX \
+ | TBICR_SPEED1_SET \
+ )
+
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC1"
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h
index 42d1f69..a051913 100644
--- a/include/configs/xpedite550x.h
+++ b/include/configs/xpedite550x.h
@@ -345,6 +345,16 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
#define CONFIG_ETHPRIME "eTSEC2"
+/*
+ * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
+ * 1000mbps SGMII link
+ */
+#define CONFIG_TSEC_TBICR_SETTINGS ( \
+ TBICR_PHY_RESET \
+ | TBICR_FULL_DUPLEX \
+ | TBICR_SPEED1_SET \
+ )
+
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC1"
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
diff --git a/include/linux/mii.h b/include/linux/mii.h
index 7c63095..6e7ffab 100644
--- a/include/linux/mii.h
+++ b/include/linux/mii.h
@@ -10,98 +10,132 @@
/* Generic MII registers. */
-#define MII_BMCR 0x00 /* Basic mode control register */
-#define MII_BMSR 0x01 /* Basic mode status register */
-#define MII_PHYSID1 0x02 /* PHYS ID 1 */
-#define MII_PHYSID2 0x03 /* PHYS ID 2 */
-#define MII_ADVERTISE 0x04 /* Advertisement control reg */
-#define MII_LPA 0x05 /* Link partner ability reg */
-#define MII_EXPANSION 0x06 /* Expansion register */
-#define MII_DCOUNTER 0x12 /* Disconnect counter */
-#define MII_FCSCOUNTER 0x13 /* False carrier counter */
-#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
-#define MII_RERRCOUNTER 0x15 /* Receive error counter */
-#define MII_SREVISION 0x16 /* Silicon revision */
-#define MII_RESV1 0x17 /* Reserved... */
-#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
-#define MII_PHYADDR 0x19 /* PHY address */
-#define MII_RESV2 0x1a /* Reserved... */
-#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
-#define MII_NCONFIG 0x1c /* Network interface config */
+#define MII_BMCR 0x00 /* Basic mode control register */
+#define MII_BMSR 0x01 /* Basic mode status register */
+#define MII_PHYSID1 0x02 /* PHYS ID 1 */
+#define MII_PHYSID2 0x03 /* PHYS ID 2 */
+#define MII_ADVERTISE 0x04 /* Advertisement control reg */
+#define MII_LPA 0x05 /* Link partner ability reg */
+#define MII_EXPANSION 0x06 /* Expansion register */
+#define MII_CTRL1000 0x09 /* 1000BASE-T control */
+#define MII_STAT1000 0x0a /* 1000BASE-T status */
+#define MII_ESTATUS 0x0f /* Extended Status */
+#define MII_DCOUNTER 0x12 /* Disconnect counter */
+#define MII_FCSCOUNTER 0x13 /* False carrier counter */
+#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
+#define MII_RERRCOUNTER 0x15 /* Receive error counter */
+#define MII_SREVISION 0x16 /* Silicon revision */
+#define MII_RESV1 0x17 /* Reserved... */
+#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
+#define MII_PHYADDR 0x19 /* PHY address */
+#define MII_RESV2 0x1a /* Reserved... */
+#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
+#define MII_NCONFIG 0x1c /* Network interface config */
/* Basic mode control register. */
-#define BMCR_RESV 0x003f /* Unused... */
-#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
-#define BMCR_CTST 0x0080 /* Collision test */
-#define BMCR_FULLDPLX 0x0100 /* Full duplex */
-#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
-#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
-#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
-#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
-#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
-#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
-#define BMCR_RESET 0x8000 /* Reset the DP83840 */
+#define BMCR_RESV 0x003f /* Unused... */
+#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
+#define BMCR_CTST 0x0080 /* Collision test */
+#define BMCR_FULLDPLX 0x0100 /* Full duplex */
+#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
+#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
+#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
+#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
+#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
+#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
+#define BMCR_RESET 0x8000 /* Reset the DP83840 */
/* Basic mode status register. */
-#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
-#define BMSR_JCD 0x0002 /* Jabber detected */
-#define BMSR_LSTATUS 0x0004 /* Link status */
-#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
-#define BMSR_RFAULT 0x0010 /* Remote fault detected */
-#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
-#define BMSR_RESV 0x07c0 /* Unused... */
-#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
-#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
-#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
-#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
-#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
+#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
+#define BMSR_JCD 0x0002 /* Jabber detected */
+#define BMSR_LSTATUS 0x0004 /* Link status */
+#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
+#define BMSR_RFAULT 0x0010 /* Remote fault detected */
+#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
+#define BMSR_RESV 0x00c0 /* Unused... */
+#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
+#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
+#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
+#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
+#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
+#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
+#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
+#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
/* Advertisement control register. */
-#define ADVERTISE_SLCT 0x001f /* Selector bits */
-#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
-#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
-#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
-#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
-#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
-#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
-#define ADVERTISE_RESV 0x1c00 /* Unused... */
-#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
-#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
-#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
+#define ADVERTISE_SLCT 0x001f /* Selector bits */
+#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
+#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
+#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
+#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
+#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */
+#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
+#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
+#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
+#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
+#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
+#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
+#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */
+#define ADVERTISE_RESV 0x1000 /* Unused... */
+#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
+#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
+#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
ADVERTISE_CSMA)
#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
- ADVERTISE_100HALF | ADVERTISE_100FULL)
+ ADVERTISE_100HALF | ADVERTISE_100FULL)
/* Link partner ability register. */
-#define LPA_SLCT 0x001f /* Same as advertise selector */
-#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
-#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
-#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
-#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
-#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
-#define LPA_RESV 0x1c00 /* Unused... */
-#define LPA_RFAULT 0x2000 /* Link partner faulted */
-#define LPA_LPACK 0x4000 /* Link partner acked us */
-#define LPA_NPAGE 0x8000 /* Next page bit */
+#define LPA_SLCT 0x001f /* Same as advertise selector */
+#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
+#define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */
+#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
+#define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */
+#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
+#define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */
+#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
+#define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/
+#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
+#define LPA_PAUSE_CAP 0x0400 /* Can pause */
+#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */
+#define LPA_RESV 0x1000 /* Unused... */
+#define LPA_RFAULT 0x2000 /* Link partner faulted */
+#define LPA_LPACK 0x4000 /* Link partner acked us */
+#define LPA_NPAGE 0x8000 /* Next page bit */
#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
/* Expansion register for auto-negotiation. */
-#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */
-#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */
-#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */
-#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */
-#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */
-#define EXPANSION_RESV 0xffe0 /* Unused... */
+#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */
+#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */
+#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */
+#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */
+#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */
+#define EXPANSION_RESV 0xffe0 /* Unused... */
+
+#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */
+#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */
/* N-way test register. */
-#define NWAYTEST_RESV1 0x00ff /* Unused... */
-#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */
-#define NWAYTEST_RESV2 0xfe00 /* Unused... */
+#define NWAYTEST_RESV1 0x00ff /* Unused... */
+#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */
+#define NWAYTEST_RESV2 0xfe00 /* Unused... */
+
+/* 1000BASE-T Control register */
+#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */
+#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */
+/* 1000BASE-T Status register */
+#define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */
+#define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */
+#define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */
+#define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */
+
+/* Flow control flags */
+#define FLOW_CTRL_TX 0x01
+#define FLOW_CTRL_RX 0x02
/**
* mii_nway_result
@@ -114,7 +148,7 @@
*
* The one exception to IEEE 802.3u is that 100baseT4 is placed
* between 100T-full and 100T-half. If your phy does not support
- * 100T4 this is fine. If your phy places 100T4 elsewhere in the
+ * 100T4 this is fine. If your phy places 100T4 elsewhere in the
* priority order, you will need to roll your own function.
*/
static inline unsigned int mii_nway_result (unsigned int negotiated)
@@ -154,5 +188,4 @@ static inline unsigned int mii_duplex (unsigned int duplex_lock,
return 0;
}
-
#endif /* __LINUX_MII_H__ */
diff --git a/include/pci_ids.h b/include/pci_ids.h
index dcc381d..cb8398d 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -882,6 +882,7 @@
#define PCI_DEVICE_ID_PLX_SPCOM200 0x1103
#define PCI_DEVICE_ID_PLX_DJINN_ITOO 0x1151
#define PCI_DEVICE_ID_PLX_R753 0x1152
+#define PCI_DEVICE_ID_PLX_9030 0x9030
#define PCI_DEVICE_ID_PLX_9050 0x9050
#define PCI_DEVICE_ID_PLX_9060 0x9060
#define PCI_DEVICE_ID_PLX_9060ES 0x906E
diff --git a/include/post.h b/include/post.h
index 957ce3b..519cef1 100644
--- a/include/post.h
+++ b/include/post.h
@@ -58,11 +58,13 @@
#elif defined (CONFIG_MPC85xx)
#include <asm/immap_85xx.h>
-#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + offsetof(ccsr_pic_t, tfrr))
+#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET + \
+ offsetof(ccsr_pic_t, tfrr))
#elif defined (CONFIG_MPC86xx)
#include <asm/immap_86xx.h>
-#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + offsetof(ccsr_pic_t, tfrr))
+#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PIC_OFFSET + \
+ offsetof(ccsr_pic_t, tfrr))
#elif defined (CONFIG_4xx)
#define _POST_WORD_ADDR \