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authorYe.Li <B37916@freescale.com>2015-03-27 17:17:14 +0800
committerYe.Li <B37916@freescale.com>2015-03-27 17:25:01 +0800
commitb4d3b2a8eaf1ad1dc529ae2348d1646a2833b701 (patch)
treec187f3f145f829d82c523acbc8d4b124c85504cf /include
parent8ba7f88f9efac9f90319b71644d3d1191f535d03 (diff)
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MLK-10492-1 imx: mx7d: Update LCDIF clock settings
To support lower clock frequency, needs to set post divider and test divider in PLL_VIDEO. So update LCDIF clock settings function to support this feature. Signed-off-by: Ye.Li <B37916@freescale.com>
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