summaryrefslogtreecommitdiff
path: root/include
diff options
context:
space:
mode:
authorBenoît Thébaudeau <benoit.thebaudeau@advansee.com>2013-04-11 09:35:51 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-04-12 07:55:07 +0200
commitda962b71758d52b38a4ed89380d296ed25920d18 (patch)
tree414567a20230b6476d0c7c316e02abfc403c70f1 /include
parent8b7cd098ddd130c0dc0d8a3820c3c592978aa9d3 (diff)
downloadu-boot-imx-da962b71758d52b38a4ed89380d296ed25920d18.zip
u-boot-imx-da962b71758d52b38a4ed89380d296ed25920d18.tar.gz
u-boot-imx-da962b71758d52b38a4ed89380d296ed25920d18.tar.bz2
nand: mxc: Switch NAND SPL to generic SPL
This also fixes support for mx31pdk and tx25, which had been broken by commit e05e5de7fae5bec79617e113916dac6631251156. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Scott Wood <scottwood@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'include')
-rw-r--r--include/configs/mx31pdk.h21
-rw-r--r--include/configs/tx25.h22
-rw-r--r--include/fsl_nfc.h225
3 files changed, 29 insertions, 239 deletions
diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index 34e4295..80ec08e 100644
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -45,7 +45,16 @@
#define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#define CONFIG_SPL
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
+#define CONFIG_SPL_MAX_SIZE 2048
+#define CONFIG_SPL_NAND_SUPPORT
+
+#define CONFIG_SPL_TEXT_BASE 0x87dc0000
+#define CONFIG_SYS_TEXT_BASE 0x87e00000
+
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
@@ -116,7 +125,7 @@
"bootcmd=run bootcmd_net\0" \
"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
"tftpboot 0x81000000 uImage-mx31; bootm\0" \
- "prg_uboot=tftpboot 0x81000000 u-boot-nand.bin; " \
+ "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \
"nand erase 0x0 0x40000; " \
"nand write 0x81000000 0x0 0x40000\0"
@@ -163,7 +172,7 @@
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_GBL_DATA_OFFSET)
+ CONFIG_SYS_INIT_RAM_SIZE)
/*-----------------------------------------------------------------------
* FLASH and environment organization
@@ -189,10 +198,10 @@
/* NAND configuration for the NAND_SPL */
/* Start copying real U-boot from the second page */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
-#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800
/* Load U-Boot to this address */
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x87f00000
+#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
diff --git a/include/configs/tx25.h b/include/configs/tx25.h
index 80194d8..e72f8f6 100644
--- a/include/configs/tx25.h
+++ b/include/configs/tx25.h
@@ -21,6 +21,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#include <asm/arch/imx-regs.h>
/*
* KARO TX25 board - SoC Configuration
@@ -31,8 +32,14 @@
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for U-Boot */
-/* NAND BOOT is the only boot method */
-#define CONFIG_NAND_U_BOOT
+#define CONFIG_SPL
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
+#define CONFIG_SPL_MAX_SIZE 2048
+#define CONFIG_SPL_NAND_SUPPORT
+
+#define CONFIG_SPL_TEXT_BASE 0x810c0000
+#define CONFIG_SYS_TEXT_BASE 0x81200000
#ifndef MACH_TYPE_TX25
#define MACH_TYPE_TX25 2177
@@ -40,16 +47,16 @@
#define CONFIG_MACH_TYPE MACH_TYPE_TX25
-#ifdef CONFIG_NAND_SPL
+#ifdef CONFIG_SPL_BUILD
/* Start copying real U-boot from the second page */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
+#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000
-#define CONFIG_SYS_NAND_U_BOOT_DST (0x81200000)
+#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_SPARE_SIZE 64
+#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_SIZE (128 * 1024 * 1024)
@@ -173,7 +180,6 @@
/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
- GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (IMX_RAM_BASE + IMX_RAM_SIZE)
#endif /* __CONFIG_H */
diff --git a/include/fsl_nfc.h b/include/fsl_nfc.h
deleted file mode 100644
index 48a6448..0000000
--- a/include/fsl_nfc.h
+++ /dev/null
@@ -1,225 +0,0 @@
-/*
- * (c) 2009 Magnus Lilja <lilja.magnus@gmail.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __FSL_NFC_H
-#define __FSL_NFC_H
-
-/*
- * Register map and bit definitions for the Freescale NAND Flash Controller
- * present in various i.MX devices.
- *
- * MX31 and MX27 have version 1, which has:
- * 4 512-byte main buffers and
- * 4 16-byte spare buffers
- * to support up to 2K byte pagesize nand.
- * Reading or writing a 2K page requires 4 FDI/FDO cycles.
- *
- * MX25 and MX35 have version 2.1, and MX51 and MX53 have version 3.2, which
- * have:
- * 8 512-byte main buffers and
- * 8 64-byte spare buffers
- * to support up to 4K byte pagesize nand.
- * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
- * Also some of registers are moved and/or changed meaning as seen below.
- */
-#if defined(CONFIG_MX27) || defined(CONFIG_MX31)
-#define MXC_NFC_V1
-#define is_mxc_nfc_1() 1
-#define is_mxc_nfc_21() 0
-#define is_mxc_nfc_32() 0
-#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
-#define MXC_NFC_V2_1
-#define is_mxc_nfc_1() 0
-#define is_mxc_nfc_21() 1
-#define is_mxc_nfc_32() 0
-#elif defined(CONFIG_MX51) || defined(CONFIG_MX53)
-#define MXC_NFC_V3
-#define MXC_NFC_V3_2
-#define is_mxc_nfc_1() 0
-#define is_mxc_nfc_21() 0
-#define is_mxc_nfc_32() 1
-#else
-#error "MXC NFC implementation not supported"
-#endif
-#define is_mxc_nfc_3() is_mxc_nfc_32()
-
-#if defined(MXC_NFC_V1)
-#define NAND_MXC_NR_BUFS 4
-#define NAND_MXC_SPARE_BUF_SIZE 16
-#define NAND_MXC_REG_OFFSET 0xe00
-#define NAND_MXC_2K_MULTI_CYCLE
-#elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
-#define NAND_MXC_NR_BUFS 8
-#define NAND_MXC_SPARE_BUF_SIZE 64
-#define NAND_MXC_REG_OFFSET 0x1e00
-#endif
-
-struct fsl_nfc_regs {
- u8 main_area[NAND_MXC_NR_BUFS][0x200];
- u8 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE];
- /*
- * reserved size is offset of nfc registers
- * minus total main and spare sizes
- */
- u8 reserved1[NAND_MXC_REG_OFFSET
- - NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)];
-#if defined(MXC_NFC_V1)
- u16 buf_size;
- u16 reserved2;
- u16 buf_addr;
- u16 flash_addr;
- u16 flash_cmd;
- u16 config;
- u16 ecc_status_result;
- u16 rsltmain_area;
- u16 rsltspare_area;
- u16 wrprot;
- u16 unlockstart_blkaddr;
- u16 unlockend_blkaddr;
- u16 nf_wrprst;
- u16 config1;
- u16 config2;
-#elif defined(MXC_NFC_V2_1)
- u16 reserved2[2];
- u16 buf_addr;
- u16 flash_addr;
- u16 flash_cmd;
- u16 config;
- u32 ecc_status_result;
- u16 spare_area_size;
- u16 wrprot;
- u16 reserved3[2];
- u16 nf_wrprst;
- u16 config1;
- u16 config2;
- u16 reserved4;
- u16 unlockstart_blkaddr;
- u16 unlockend_blkaddr;
- u16 unlockstart_blkaddr1;
- u16 unlockend_blkaddr1;
- u16 unlockstart_blkaddr2;
- u16 unlockend_blkaddr2;
- u16 unlockstart_blkaddr3;
- u16 unlockend_blkaddr3;
-#elif defined(MXC_NFC_V3_2)
- u32 flash_cmd;
- u32 flash_addr[12];
- u32 config1;
- u32 ecc_status_result;
- u32 status_sum;
- u32 launch;
-#endif
-};
-
-#ifdef MXC_NFC_V3_2
-struct fsl_nfc_ip_regs {
- u32 wrprot;
- u32 wrprot_unlock_blkaddr[8];
- u32 config2;
- u32 config3;
- u32 ipc;
- u32 err_addr;
- u32 delay_line;
-};
-#endif
-
-/* Set FCMD to 1, rest to 0 for Command operation */
-#define NFC_CMD 0x1
-
-/* Set FADD to 1, rest to 0 for Address operation */
-#define NFC_ADDR 0x2
-
-/* Set FDI to 1, rest to 0 for Input operation */
-#define NFC_INPUT 0x4
-
-/* Set FDO to 001, rest to 0 for Data Output operation */
-#define NFC_OUTPUT 0x8
-
-/* Set FDO to 010, rest to 0 for Read ID operation */
-#define NFC_ID 0x10
-
-/* Set FDO to 100, rest to 0 for Read Status operation */
-#define NFC_STATUS 0x20
-
-#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
-#define NFC_CONFIG1_SP_EN (1 << 2)
-#define NFC_CONFIG1_RST (1 << 6)
-#define NFC_CONFIG1_CE (1 << 7)
-#elif defined(MXC_NFC_V3_2)
-#define NFC_CONFIG1_SP_EN (1 << 0)
-#define NFC_CONFIG1_CE (1 << 1)
-#define NFC_CONFIG1_RST (1 << 2)
-#endif
-#define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
-#define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
-#define NFC_V1_V2_CONFIG1_BIG (1 << 5)
-#define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
-#define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
-#define NFC_V2_CONFIG1_FP_INT (1 << 11)
-#define NFC_V3_CONFIG1_RBA_MASK (0x7 << 4)
-#define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7) << 4)
-
-#define NFC_V1_V2_CONFIG2_INT (1 << 15)
-#define NFC_V3_CONFIG2_PS_MASK (0x3 << 0)
-#define NFC_V3_CONFIG2_PS_512 (0 << 0)
-#define NFC_V3_CONFIG2_PS_2048 (1 << 0)
-#define NFC_V3_CONFIG2_PS_4096 (2 << 0)
-#define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
-#define NFC_V3_CONFIG2_ECC_EN (1 << 3)
-#define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
-#define NFC_V3_CONFIG2_NUM_ADDR_PH0 (1 << 5)
-#define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
-#define NFC_V3_CONFIG2_PPB_MASK (0x3 << 7)
-#define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7)
-#define NFC_V3_CONFIG2_EDC_MASK (0x7 << 9)
-#define NFC_V3_CONFIG2_EDC(x) (((x) & 0x7) << 9)
-#define NFC_V3_CONFIG2_NUM_ADDR_PH1(x) (((x) & 0x3) << 12)
-#define NFC_V3_CONFIG2_INT_MSK (1 << 15)
-#define NFC_V3_CONFIG2_SPAS_MASK (0xff << 16)
-#define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
-#define NFC_V3_CONFIG2_ST_CMD_MASK (0xff << 24)
-#define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
-
-#define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
-#define NFC_V3_CONFIG3_FW8 (1 << 3)
-#define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
-#define NFC_V3_CONFIG3_NUM_OF_DEVS(x) (((x) & 0x7) << 12)
-#define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
-#define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
-
-#define NFC_V3_WRPROT_UNLOCK (1 << 2)
-#define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
-
-#define NFC_V3_IPC_CREQ (1 << 0)
-#define NFC_V3_IPC_INT (1 << 31)
-
-#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
-#define operation config2
-#define readnfc readw
-#define writenfc writew
-#elif defined(MXC_NFC_V3_2)
-#define operation launch
-#define readnfc readl
-#define writenfc writel
-#endif
-
-#endif /* __FSL_NFC_H */