Merge branch 'master' of /home/stefan/git/u-boot/u-boot

11 files changed, 1221 insertions, 37 deletions

diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 455bbe0..f12a3e6 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -76,10 +76,10 @@
  * seem to have the SPD connected to I2C.
  */
 #define CFG_DDR_SIZE		128		/* MB */
-#define CFG_DDR_CONFIG		( CSCONFIG_EN | CSCONFIG_AP \
-				| 0x00040000 /* TODO */ \
+#define CFG_DDR_CONFIG		( CSCONFIG_EN \
+				| 0x00010000 /* TODO */ \
 				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
-				/* 0x80840102 */
+				/* 0x80010102 */
 
 #define CFG_DDR_TIMING_3	0x00000000
 #define CFG_DDR_TIMING_0	( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
@@ -92,25 +92,25 @@
 				| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
 				/* 0x00220802 */
 #define CFG_DDR_TIMING_1	( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
-				| ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
+				| ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
 				| ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
 				| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
-				| (13 << TIMING_CFG1_REFREC_SHIFT ) \
+				| (10 << TIMING_CFG1_REFREC_SHIFT ) \
 				| ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
 				| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
 				| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
-				/* 0x3935d322 */
-#define CFG_DDR_TIMING_2	( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \
-				| (31 << TIMING_CFG2_CPO_SHIFT ) \
+				/* 0x3835a322 */
+#define CFG_DDR_TIMING_2	( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
+				| ( 5 << TIMING_CFG2_CPO_SHIFT ) \
 				| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
 				| ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
 				| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
 				| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
-				| (10 << TIMING_CFG2_FOUR_ACT_SHIFT) )
-				/* 0x0f9048ca */ /* P9-45,may need tuning */
-#define CFG_DDR_INTERVAL	( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \
-				| ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
-				/* 0x03200064 */
+				| ( 6 << TIMING_CFG2_FOUR_ACT_SHIFT) )
+				/* 0x129048c6 */ /* P9-45,may need tuning */
+#define CFG_DDR_INTERVAL	( ( 1296 << SDRAM_INTERVAL_REFINT_SHIFT ) \
+				| ( 1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
+				/* 0x05100500 */
 #if defined(CONFIG_DDR_2T_TIMING)
 #define CFG_SDRAM_CFG		( SDRAM_CFG_SREN \
 				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
@@ -124,9 +124,9 @@
 #endif
 #define CFG_SDRAM_CFG2		0x00401000;
 /* set burst length to 8 for 32-bit data path */
-#define CFG_DDR_MODE		( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \
-				| ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
-				/* 0x44400232 */
+#define CFG_DDR_MODE		( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
+				| ( 0x0632 << SDRAM_MODE_SD_SHIFT ) )
+				/* 0x44480632 */
 #define CFG_DDR_MODE_2		0x8000C000;
 
 #define CFG_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
new file mode 100644
index 0000000..ad2305c
--- /dev/null
+++ b/include/configs/MPC8315ERDB.h
@@ -0,0 +1,547 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ *
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef DEBUG
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1 /* E300 family */
+#define CONFIG_MPC83XX		1 /* MPC83xx family */
+#define CONFIG_MPC831X		1 /* MPC831x CPU family */
+#define CONFIG_MPC8315		1 /* MPC8315 CPU specific */
+#define CONFIG_MPC8315ERDB	1 /* MPC8315ERDB board specific */
+
+/*
+ * System Clock Setup
+ */
+#define CONFIG_83XX_CLKIN	66666667 /* in Hz */
+#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
+
+/*
+ * Hardware Reset Configuration Word
+ * if CLKIN is 66.66MHz, then
+ * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
+ */
+#define CFG_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_2X1 |\
+	HRCWL_SVCOD_DIV_2 |\
+	HRCWL_CSB_TO_CLKIN_2X1 |\
+	HRCWL_CORE_TO_CSB_3X1)
+#define CFG_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_RL_EXT_LEGACY |\
+	HRCWH_TSEC1M_IN_RGMII |\
+	HRCWH_TSEC2M_IN_RGMII |\
+	HRCWH_BIG_ENDIAN |\
+	HRCWH_LALE_NORMAL)
+
+/*
+ * System IO Config
+ */
+#define CFG_SICRH		0x00000000
+#define CFG_SICRL		0x00000000 /* 3.3V, no delay */
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
+
+/*
+ * IMMR new address
+ */
+#define CFG_IMMR		0xE0000000
+
+/*
+ * Arbiter Setup
+ */
+#define CFG_ACR_PIPE_DEP	3 /* Arbiter pipeline depth is 4 */
+#define CFG_ACR_RPTCNT		3 /* Arbiter repeat count is 4 */
+#define CFG_SPCR_TSECEP		3 /* eTSEC emergency priority is highest */
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_BASE		0x00000000 /* DDR is system memory */
+#define CFG_SDRAM_BASE		CFG_DDR_BASE
+#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
+#define CFG_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+#define CFG_DDRCDR_VALUE	( DDRCDR_EN \
+				| DDRCDR_PZ_LOZ \
+				| DDRCDR_NZ_LOZ \
+				| DDRCDR_ODT \
+				| DDRCDR_Q_DRN )
+				/* 0x7b880001 */
+/*
+ * Manually set up DDR parameters
+ * consist of two chips HY5PS12621BFP-C4 from HYNIX
+ */
+#define CFG_DDR_SIZE		128 /* MB */
+#define CFG_DDR_CS0_BNDS	0x00000007
+#define CFG_DDR_CS0_CONFIG	( CSCONFIG_EN \
+				| 0x00010000  /* ODT_WR to CSn */ \
+				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
+				/* 0x80010102 */
+#define CFG_DDR_TIMING_3	0x00000000
+#define CFG_DDR_TIMING_0	( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
+				| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
+				| ( 0 << TIMING_CFG0_RRT_SHIFT ) \
+				| ( 0 << TIMING_CFG0_WWT_SHIFT ) \
+				| ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
+				| ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
+				| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
+				| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
+				/* 0x00220802 */
+#define CFG_DDR_TIMING_1	( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
+				| ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
+				| ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
+				| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
+				| ( 6 << TIMING_CFG1_REFREC_SHIFT ) \
+				| ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
+				| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
+				| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
+				/* 0x39356222 */
+#define CFG_DDR_TIMING_2	( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
+				| ( 4 << TIMING_CFG2_CPO_SHIFT ) \
+				| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
+				| ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
+				| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
+				| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
+				| ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) )
+				/* 0x121048c7 */
+#define CFG_DDR_INTERVAL	( ( 0x0360 << SDRAM_INTERVAL_REFINT_SHIFT ) \
+				| ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
+				/* 0x03600100 */
+#define CFG_DDR_SDRAM_CFG	( SDRAM_CFG_SREN \
+				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
+				| SDRAM_CFG_32_BE )
+				/* 0x43080000 */
+#define CFG_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
+#define CFG_DDR_MODE		( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \
+				| ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
+				/* ODT 150ohm CL=3, AL=1 on SDRAM */
+#define CFG_DDR_MODE2		0x00000000
+
+/*
+ * Memory test
+ */
+#undef CFG_DRAM_TEST		/* memory test, takes time */
+#define CFG_MEMTEST_START	0x00040000 /* memtest region */
+#define CFG_MEMTEST_END		0x00140000
+
+/*
+ * The reserved memory
+ */
+#define CFG_MONITOR_BASE	TEXT_BASE /* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef CFG_RAMBOOT
+#endif
+
+#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(512 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CFG_INIT_RAM_LOCK	1
+#define CFG_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CFG_INIT_RAM_END	0x1000 /* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE	0x100 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CFG_LCRR		(LCRR_DBYP | LCRR_CLKDIV_2)
+#define CFG_LBC_LBCR		0x00040000
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CFG_FLASH_CFI		/* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER	/* use the CFI driver */
+#define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+
+#define CFG_FLASH_BASE		0xFE000000 /* FLASH base address */
+#define CFG_FLASH_SIZE		8 /* FLASH size is 8M */
+
+#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE /* Window base at flash base */
+#define CFG_LBLAWAR0_PRELIM	0x80000016 /* 8MB window size */
+
+#define CFG_BR0_PRELIM		( CFG_FLASH_BASE	/* Flash Base address */ \
+				| (2 << BR_PS_SHIFT)	/* 16 bit port size */ \
+				| BR_V )		/* valid */
+#define CFG_OR0_PRELIM		( (~(CFG_FLASH_SIZE - 1) << 20) \
+				| OR_UPM_XAM \
+				| OR_GPCM_CSNT \
+				| OR_GPCM_ACS_0b11 \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_15 \
+				| OR_GPCM_TRLX \
+				| OR_GPCM_EHTR \
+				| OR_GPCM_EAD )
+
+#define CFG_MAX_FLASH_BANKS	1 /* number of banks */
+#define CFG_MAX_FLASH_SECT	135 /* 127 64KB sectors and 8 8KB top sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
+
+/*
+ * NAND Flash on the Local Bus
+ */
+#define CFG_NAND_BASE		0xE0600000	/* 0xE0600000 */
+#define CFG_MAX_NAND_DEVICE	1
+#define NAND_MAX_CHIPS		1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+
+#define CFG_BR1_PRELIM		( CFG_NAND_BASE \
+				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+				| BR_PS_8		/* Port Size = 8 bit */ \
+				| BR_MS_FCM		/* MSEL = FCM */ \
+				| BR_V )		/* valid */
+#define CFG_OR1_PRELIM		( 0xFFFF8000		/* length 32K */ \
+				| OR_FCM_CSCT \
+				| OR_FCM_CST \
+				| OR_FCM_CHT \
+				| OR_FCM_SCY_1 \
+				| OR_FCM_TRLX \
+				| OR_FCM_EHTR )
+				/* 0xFFFF8396 */
+
+#define CFG_LBLAWBAR1_PRELIM	CFG_NAND_BASE
+#define CFG_LBLAWAR1_PRELIM	0x8000000E	/* 32KB  */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CFG_NS16550_COM1	(CFG_IMMR+0x4500)
+#define CFG_NS16550_COM2	(CFG_IMMR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/* I2C */
+#define CONFIG_HARD_I2C		/* I2C with hardware support */
+#define CONFIG_FSL_I2C
+#define CFG_I2C_SPEED		400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES	{0x51} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3000
+#define CFG_I2C2_OFFSET		0x3100
+
+/*
+ * Board info - revision and where boot from
+ */
+#define CFG_I2C_PCF8574A_ADDR	0x39
+
+/*
+ * Config on-board RTC
+ */
+#define CONFIG_RTC_DS1337	/* ds1339 on board, use ds1337 rtc via i2c */
+#define CFG_I2C_RTC_ADDR	0x68 /* at address 0x68 */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI_MEM_BASE	0x80000000
+#define CFG_PCI_MEM_PHYS	CFG_PCI_MEM_BASE
+#define CFG_PCI_MEM_SIZE	0x10000000 /* 256M */
+#define CFG_PCI_MMIO_BASE	0x90000000
+#define CFG_PCI_MMIO_PHYS	CFG_PCI_MMIO_BASE
+#define CFG_PCI_MMIO_SIZE	0x10000000 /* 256M */
+#define CFG_PCI_IO_BASE		0xE0300000
+#define CFG_PCI_IO_PHYS		0xE0300000
+#define CFG_PCI_IO_SIZE		0x100000 /* 1M */
+
+#define CFG_PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE
+#define CFG_PCI_SLV_MEM_BUS	0x00000000
+#define CFG_PCI_SLV_MEM_SIZE	0x80000000
+
+#define CONFIG_PCI
+#define CONFIG_83XX_GENERIC_PCI	1 /* Use generic PCI setup */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+
+#define CONFIG_EEPRO100
+#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI	1
+#endif
+
+/*
+ * TSEC
+ */
+#define CONFIG_TSEC_ENET	/* TSEC ethernet support */
+#define CFG_TSEC1_OFFSET	0x24000
+#define CFG_TSEC1		(CFG_IMMR+CFG_TSEC1_OFFSET)
+#define CFG_TSEC2_OFFSET	0x25000
+#define CFG_TSEC2		(CFG_IMMR+CFG_TSEC2_OFFSET)
+
+/*
+ * TSEC ethernet configuration
+ */
+#define CONFIG_MII		1 /* MII PHY management */
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC0"
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC1"
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+/* Options are: eTSEC[0-1] */
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+/*
+ * Environment
+ */
+#ifndef CFG_RAMBOOT
+	#define CFG_ENV_IS_IN_FLASH	1
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+	#define CFG_ENV_SECT_SIZE	0x10000 /* 64K(one sector) for env */
+	#define CFG_ENV_SIZE		0x2000
+#else
+	#define CFG_NO_FLASH		1	/* Flash is not usable now */
+	#define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+	#define CFG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PCI
+
+#if defined(CFG_RAMBOOT)
+    #undef CONFIG_CMD_ENV
+    #undef CONFIG_CMD_LOADS
+#endif
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
+
+#undef CONFIG_WATCHDOG		/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP		/* undef to save memory */
+#define CFG_LOAD_ADDR		0x2000000 /* default load address */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt */
+
+#if defined(CONFIG_CMD_KGDB)
+	#define CFG_CBSIZE	1024 /* Console I/O Buffer Size */
+#else
+	#define CFG_CBSIZE	256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Core HID Setup
+ */
+#define CFG_HID0_INIT		0x000000000
+#define CFG_HID0_FINAL		(HID0_ENABLE_MACHINE_CHECK | \
+				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
+#define CFG_HID2		HID2_HBE
+
+/*
+ * MMU Setup
+ */
+
+/* DDR: cache cacheable */
+#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
+#define CFG_DBAT0L	CFG_IBAT0L
+#define CFG_DBAT0U	CFG_IBAT0U
+
+/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
+#define CFG_IBAT1L	(CFG_IMMR | BATL_PP_10 | \
+			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT1U	(CFG_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
+#define CFG_DBAT1L	CFG_IBAT1L
+#define CFG_DBAT1U	CFG_IBAT1U
+
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
+#define CFG_IBAT2L	(CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT2U	(CFG_FLASH_BASE | BATU_BL_8M | BATU_VS | BATU_VP)
+#define CFG_DBAT2L	(CFG_FLASH_BASE | BATL_PP_10 | \
+			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT2U	CFG_IBAT2U
+
+/* Stack in dcache: cacheable, no memory coherence */
+#define CFG_IBAT3L	(CFG_INIT_RAM_ADDR | BATL_PP_10)
+#define CFG_IBAT3U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CFG_DBAT3L	CFG_IBAT3L
+#define CFG_DBAT3U	CFG_IBAT3U
+
+/* PCI MEM space: cacheable */
+#define CFG_IBAT4L	(CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT4U	(CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT4L	CFG_IBAT4L
+#define CFG_DBAT4U	CFG_IBAT4U
+
+/* PCI MMIO space: cache-inhibit and guarded */
+#define CFG_IBAT5L	(CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
+			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT5U	(CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT5L	CFG_IBAT5L
+#define CFG_DBAT5U	CFG_IBAT5U
+
+#define CFG_IBAT6L	0
+#define CFG_IBAT6U	0
+#define CFG_DBAT6L	CFG_IBAT6L
+#define CFG_DBAT6U	CFG_IBAT6U
+
+#define CFG_IBAT7L	0
+#define CFG_IBAT7U	0
+#define CFG_DBAT7L	CFG_IBAT7L
+#define CFG_DBAT7U	CFG_IBAT7U
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02 /* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_ETHADDR		04:00:00:00:00:0A
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR		04:00:00:00:00:0B
+#endif
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_LOADADDR 200000	/* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+   "netdev=eth0\0"							\
+   "consoledev=ttyS0\0"							\
+   "ramdiskaddr=1000000\0"						\
+   "ramdiskfile=ramfs.83xx\0"						\
+   "fdtaddr=400000\0"							\
+   "fdtfile=mpc8315erdb.dtb\0"						\
+   ""
+
+#define CONFIG_NFSBOOTCOMMAND						\
+   "setenv bootargs root=/dev/nfs rw "					\
+      "nfsroot=$serverip:$rootpath "					\
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+      "console=$consoledev,$baudrate $othbootargs;"			\
+   "tftp $loadaddr $bootfile;"						\
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+   "setenv bootargs root=/dev/ram rw "					\
+      "console=$consoledev,$baudrate $othbootargs;"			\
+   "tftp $ramdiskaddr $ramdiskfile;"					\
+   "tftp $loadaddr $bootfile;"						\
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+
+#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 4ea8709..295e785 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -321,7 +321,7 @@
  * QE UEC ethernet configuration
  */
 #define CONFIG_UEC_ETH
-#define CONFIG_ETHPRIME		"Freescale GETH"
+#define CONFIG_ETHPRIME		"FSL UEC0"
 
 #define CONFIG_UEC_ETH1		/* ETH3 */
 
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index 25ac58c..6c0e68a 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -377,7 +377,7 @@
  * QE UEC ethernet configuration
  */
 #define CONFIG_UEC_ETH
-#define CONFIG_ETHPRIME		"Freescale GETH"
+#define CONFIG_ETHPRIME		"FSL UEC0"
 
 #define CONFIG_UEC_ETH1		/* ETH3 */
 
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index fdacb90..168ca2a 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -405,7 +405,7 @@
  * QE UEC ethernet configuration
  */
 #define CONFIG_UEC_ETH
-#define CONFIG_ETHPRIME		"Freescale GETH"
+#define CONFIG_ETHPRIME		"FSL UEC0"
 #define CONFIG_PHY_MODE_NEED_CHANGE
 
 #define CONFIG_UEC_ETH1		/* GETH1 */
@@ -466,6 +466,7 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_SDRAM
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index 0f6f8f1..83a4b1e 100644
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -282,7 +282,7 @@
  * QE UEC ethernet configuration
  */
 #define CONFIG_UEC_ETH
-#define CONFIG_ETHPRIME		"Freescale GETH"
+#define CONFIG_ETHPRIME		"FSL UEC0"
 
 #define CONFIG_UEC_ETH1		/* GETH1 */
 
@@ -387,15 +387,6 @@
 #define CFG_HID2		HID2_HBE
 
 /*
- * Cache Config
- */
-#define CFG_DCACHE_SIZE		32768
-#define CFG_CACHELINE_SIZE	32
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5 /*log base 2 of the above value */
-#endif
-
-/*
  * MMU Setup
  */
 
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
new file mode 100644
index 0000000..2da4f29
--- /dev/null
+++ b/include/configs/MPC837XERDB.h
@@ -0,0 +1,596 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Kevin Lam <kevin.lam@freescale.com>
+ * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1 /* E300 family */
+#define CONFIG_MPC83XX		1 /* MPC83XX family */
+#define CONFIG_MPC837X		1 /* MPC837X CPU specific */
+#define CONFIG_MPC837XERDB	1
+
+#define CONFIG_PCI	1
+
+/*
+ * System Clock Setup
+ */
+#ifdef CONFIG_PCISLAVE
+#define CONFIG_83XX_PCICLK	66666667 /* in HZ */
+#else
+#define CONFIG_83XX_CLKIN	66666667 /* in Hz */
+#define CONFIG_83XX_GENERIC_PCI	1
+#endif
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
+#endif
+
+/*
+ * Hardware Reset Configuration Word
+ */
+#define CFG_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_SVCOD_DIV_2 |\
+	HRCWL_CSB_TO_CLKIN_5X1 |\
+	HRCWL_CORE_TO_CSB_2X1)
+
+#ifdef CONFIG_PCISLAVE
+#define CFG_HRCW_HIGH (\
+	HRCWH_PCI_AGENT |\
+	HRCWH_PCI1_ARBITER_DISABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0XFFF00100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_RL_EXT_LEGACY |\
+	HRCWH_TSEC1M_IN_RGMII |\
+	HRCWH_TSEC2M_IN_RGMII |\
+	HRCWH_BIG_ENDIAN |\
+	HRCWH_LDP_CLEAR)
+#else
+#define CFG_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_RL_EXT_LEGACY |\
+	HRCWH_TSEC1M_IN_RGMII |\
+	HRCWH_TSEC2M_IN_RGMII |\
+	HRCWH_BIG_ENDIAN |\
+	HRCWH_LDP_CLEAR)
+#endif
+
+/* System performance - define the value i.e. CFG_XXX
+*/
+
+/* Arbiter Configuration Register */
+#define CFG_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
+#define CFG_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
+
+/* System Priority Control Regsiter */
+#define CFG_SPCR_TSECEP		3	/* eTSEC1&2 emergency priority (0-3) */
+
+/* System Clock Configuration Register */
+#define CFG_SCCR_TSEC1CM	1		/* eTSEC1 clock mode (0-3) */
+#define CFG_SCCR_TSEC2CM	1		/* eTSEC2 clock mode (0-3) */
+#define CFG_SCCR_SATACM		SCCR_SATACM_1	/* SATA1-4 clock mode (0-3) */
+
+/*
+ * System IO Config
+ */
+#define CFG_SICRH		0x08200000
+#define CFG_SICRL		0x00000000
+
+/*
+ * Output Buffer Impedance
+ */
+#define CFG_OBIR		0x30100000
+
+/*
+ * IMMR new address
+ */
+#define CFG_IMMR		0xE0000000
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_BASE		0x00000000 /* DDR is system memory */
+#define CFG_SDRAM_BASE		CFG_DDR_BASE
+#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
+#define CFG_DDR_SDRAM_CLK_CNTL	0x03000000
+#define CFG_83XX_DDR_USES_CS0
+
+#define CFG_DDRCDR_VALUE	(DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
+
+#undef CONFIG_DDR_ECC		/* support DDR ECC function */
+#undef CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */
+
+#undef CONFIG_NEVER_ASSERT_ODT_TO_CPU	/* Never assert ODT to internal IOs */
+
+/*
+ * Manually set up DDR parameters
+ */
+#define CFG_DDR_SIZE		256		/* MB */
+#define CFG_DDR_CS0_BNDS	0x0000000f
+#define CFG_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_ODT_WR_ACS \
+				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+
+#define CFG_DDR_TIMING_3	0x00000000
+#define CFG_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
+				| (0 << TIMING_CFG0_WRT_SHIFT) \
+				| (0 << TIMING_CFG0_RRT_SHIFT) \
+				| (0 << TIMING_CFG0_WWT_SHIFT) \
+				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+				| (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+				/* 0x00220802 */
+				/* 0x00260802 */ /* DDR400 */
+#define CFG_DDR_TIMING_1	((3 << TIMING_CFG1_PRETOACT_SHIFT) \
+				| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+				| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
+				| (7 << TIMING_CFG1_CASLAT_SHIFT) \
+				| (13 << TIMING_CFG1_REFREC_SHIFT) \
+				| (3 << TIMING_CFG1_WRREC_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+				| (2 << TIMING_CFG1_WRTORD_SHIFT))
+				/* 0x3935d322 */
+				/* 0x3937d322 */
+#define CFG_DDR_TIMING_2	0x02984cc8
+
+#define CFG_DDR_INTERVAL	((1545 << SDRAM_INTERVAL_REFINT_SHIFT) \
+				| (256 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+				/* 0x06090100 */
+
+#if defined(CONFIG_DDR_2T_TIMING)
+#define CFG_DDR_SDRAM_CFG		(SDRAM_CFG_SREN \
+				| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
+				| SDRAM_CFG_2T_EN \
+				| SDRAM_CFG_DBW_32)
+#else
+#define CFG_DDR_SDRAM_CFG		(SDRAM_CFG_SREN \
+				| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT)
+				/* 0x43000000 */
+#endif
+#define CFG_DDR_SDRAM_CFG2	0x00001000 /* 1 posted refresh */
+#define CFG_DDR_MODE		((0x0440 << SDRAM_MODE_ESD_SHIFT) \
+				| (0x0442 << SDRAM_MODE_SD_SHIFT))
+				/* 0x04400442 */ /* DDR400 */
+#define CFG_DDR_MODE2		0x00000000;
+
+/*
+ * Memory test
+ */
+#undef CFG_DRAM_TEST		/* memory test, takes time */
+#define CFG_MEMTEST_START	0x00040000 /* memtest region */
+#define CFG_MEMTEST_END		0x0ef70010
+
+/*
+ * The reserved memory
+ */
+#define CFG_MONITOR_BASE	TEXT_BASE /* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef	CFG_RAMBOOT
+#endif
+
+#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(512 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CFG_INIT_RAM_LOCK	1
+#define CFG_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CFG_INIT_RAM_END	0x1000 /* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE	0x100 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CFG_LCRR		(LCRR_DBYP | LCRR_CLKDIV_8)
+#define CFG_LBC_LBCR		0x00000000
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CFG_FLASH_CFI		/* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER	/* use the CFI driver */
+#define CFG_FLASH_BASE		0xFE000000 /* FLASH base address */
+#define CFG_FLASH_SIZE		8 /* max FLASH size is 32M */
+
+#define CFG_FLASH_EMPTY_INFO			/* display empty sectors */
+#define CFG_FLASH_USE_BUFFER_WRITE		/* buffer up multiple bytes */
+
+#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE /* Window base at flash base */
+#define CFG_LBLAWAR0_PRELIM	0x80000016	/* 8 MB window size */
+
+#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | /* Flash Base address */ \
+				(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
+				BR_V) /* valid */
+#define CFG_OR0_PRELIM		(0xFF800000		/* 8 MByte */ \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_9 \
+				| OR_GPCM_EHTR \
+				| OR_GPCM_EAD)
+				/* 0xFF806FF7	TODO SLOW 8 MB flash size */
+
+#define CFG_MAX_FLASH_BANKS	1 /* number of banks */
+#define CFG_MAX_FLASH_SECT	256 /* max sectors per device */
+
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CFG_VSC7385_BASE	0xF0000000
+
+/* VSC7385 Gigabit Switch support */
+#define CONFIG_VSC7385_ENET
+#define CFG_BR2_PRELIM		0xf0000801		/* Base address */
+#define CFG_OR2_PRELIM		0xfffe09ff		/* 128K bytes*/
+#define CFG_LBLAWBAR2_PRELIM	CFG_VSC7385_BASE	/* Access Base */
+#define CFG_LBLAWAR2_PRELIM	0x80000010		/* Access Size 128K */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CFG_NS16550_COM1	(CFG_IMMR+0x4500)
+#define CFG_NS16550_COM2	(CFG_IMMR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+/* I2C */
+#define CONFIG_HARD_I2C		/* I2C with hardware support */
+#undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
+#define CONFIG_FSL_I2C
+#define CFG_I2C_SPEED		400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES	{0x51} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3000
+#define CFG_I2C2_OFFSET		0x3100
+
+/*
+ * Config on-board RTC
+ */
+#define CONFIG_RTC_DS1374	/* use ds1374 rtc via i2c */
+#define CFG_I2C_RTC_ADDR	0x68 /* at address 0x68 */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI_MEM_BASE	0x80000000
+#define CFG_PCI_MEM_PHYS	CFG_PCI_MEM_BASE
+#define CFG_PCI_MEM_SIZE	0x10000000 /* 256M */
+#define CFG_PCI_MMIO_BASE	0x90000000
+#define CFG_PCI_MMIO_PHYS	CFG_PCI_MMIO_BASE
+#define CFG_PCI_MMIO_SIZE	0x10000000 /* 256M */
+#define CFG_PCI_IO_BASE		0xE0300000
+#define CFG_PCI_IO_PHYS		0xE0300000
+#define CFG_PCI_IO_SIZE		0x100000 /* 1M */
+
+#define CFG_PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE
+#define CFG_PCI_SLV_MEM_BUS	0x00000000
+#define CFG_PCI_SLV_MEM_SIZE	0x80000000
+
+#ifdef CONFIG_PCI
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
+#endif	/* CONFIG_PCI */
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI	1
+#endif
+
+/*
+ * TSEC
+ */
+#define CONFIG_TSEC_ENET	/* TSEC ethernet support */
+#define CFG_TSEC1_OFFSET	0x24000
+#define CFG_TSEC1		(CFG_IMMR+CFG_TSEC1_OFFSET)
+#define CFG_TSEC2_OFFSET	0x25000
+#define CFG_TSEC2		(CFG_IMMR+CFG_TSEC2_OFFSET)
+
+/*
+ * TSEC ethernet configuration
+ */
+#define CONFIG_GMII			1	/* MII PHY management */
+#define CONFIG_TSEC1			1
+#define CONFIG_TSEC1_NAME		"TSEC0"
+#define CONFIG_TSEC2			1
+#define CONFIG_TSEC2_NAME		"TSEC1"
+#define TSEC1_PHY_ADDR			2
+#define TSEC2_PHY_ADDR			0x1c
+#define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC1_PHYIDX			0
+#define TSEC2_PHYIDX			0
+
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME			"TSEC0"
+
+/*
+ * Environment
+ */
+#ifndef CFG_RAMBOOT
+	#define CFG_ENV_IS_IN_FLASH	1
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE+CFG_MONITOR_LEN)
+	#define CFG_ENV_SECT_SIZE	0x10000	/* 64K (one sector) for env */
+	#define CFG_ENV_SIZE		0x4000
+#else
+	#define CFG_NO_FLASH		1	/* Flash is not usable now */
+	#define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-0x1000)
+	#define CFG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DATE
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#endif
+
+#if defined(CFG_RAMBOOT)
+#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_LOADS
+#endif
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
+
+#undef CONFIG_WATCHDOG		/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP		/* undef to save memory */
+#define CFG_LOAD_ADDR		0x2000000 /* default load address */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt */
+
+#if defined(CONFIG_CMD_KGDB)
+	#define CFG_CBSIZE	1024 /* Console I/O Buffer Size */
+#else
+	#define CFG_CBSIZE	256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Core HID Setup
+ */
+#define CFG_HID0_INIT		0x000000000
+#define CFG_HID0_FINAL		HID0_ENABLE_MACHINE_CHECK
+#define CFG_HID2		HID2_HBE
+
+/*
+ * MMU Setup
+ */
+
+/* DDR: cache cacheable */
+#define CFG_SDRAM_LOWER		CFG_SDRAM_BASE
+#define CFG_SDRAM_UPPER		(CFG_SDRAM_BASE + 0x10000000)
+
+#define CFG_IBAT0L	(CFG_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U	(CFG_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT0L	CFG_IBAT0L
+#define CFG_DBAT0U	CFG_IBAT0U
+
+#define CFG_IBAT1L	(CFG_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U	(CFG_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT1L	CFG_IBAT1L
+#define CFG_DBAT1U	CFG_IBAT1U
+
+/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
+#define CFG_IBAT2L	(CFG_IMMR | BATL_PP_10 | \
+			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT2U	(CFG_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
+#define CFG_DBAT2L	CFG_IBAT2L
+#define CFG_DBAT2U	CFG_IBAT2U
+
+/* L2 Switch: cache-inhibit and guarded */
+#define CFG_IBAT3L	(CFG_VSC7385_BASE | BATL_PP_10 | \
+			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT3U	(CFG_VSC7385_BASE | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CFG_DBAT3L	CFG_IBAT3L
+#define CFG_DBAT3U	CFG_IBAT3U
+
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
+#define CFG_IBAT4L	(CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT4U	(CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_DBAT4L	(CFG_FLASH_BASE | BATL_PP_10 | \
+			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT4U	CFG_IBAT4U
+
+/* Stack in dcache: cacheable, no memory coherence */
+#define CFG_IBAT5L	(CFG_INIT_RAM_ADDR | BATL_PP_10)
+#define CFG_IBAT5U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CFG_DBAT5L	CFG_IBAT5L
+#define CFG_DBAT5U	CFG_IBAT5U
+
+#ifdef CONFIG_PCI
+/* PCI MEM space: cacheable */
+#define CFG_IBAT6L	(CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT6U	(CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT6L	CFG_IBAT6L
+#define CFG_DBAT6U	CFG_IBAT6U
+/* PCI MMIO space: cache-inhibit and guarded */
+#define CFG_IBAT7L	(CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
+			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT7U	(CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT7L	CFG_IBAT7L
+#define CFG_DBAT7U	CFG_IBAT7U
+#else
+#define CFG_IBAT6L	(0)
+#define CFG_IBAT6U	(0)
+#define CFG_IBAT7L	(0)
+#define CFG_IBAT7U	(0)
+#define CFG_DBAT6L	CFG_IBAT6L
+#define CFG_DBAT6U	CFG_IBAT6U
+#define CFG_DBAT7L	CFG_IBAT7L
+#define CFG_DBAT7U	CFG_IBAT7U
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02 /* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_HAS_ETH0				/* add support for "ethaddr" */
+#define CONFIG_ETHADDR	00:04:9f:ef:04:01
+#define CONFIG_HAS_ETH1				/* add support for "eth1addr" */
+#define CONFIG_ETH1ADDR	00:04:9f:ef:04:02
+
+#define CONFIG_IPADDR		10.0.0.2
+#define CONFIG_SERVERIP		10.0.0.1
+#define CONFIG_GATEWAYIP	10.0.0.1
+#define CONFIG_NETMASK		255.0.0.0
+#define CONFIG_NETDEV		eth1
+
+#define CONFIG_HOSTNAME		mpc837x_rdb
+#define CONFIG_ROOTPATH		/nfsroot
+#define CONFIG_RAMDISKFILE	rootfs.ext2.gz.uboot
+#define CONFIG_BOOTFILE		uImage
+#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
+#define CONFIG_FDTFILE		mpc837x_rdb.dtb
+
+#define CONFIG_LOADADDR		200000	/* default location for tftp and bootm */
+#define CONFIG_BOOTDELAY	-1	/* -1 disables auto-boot */
+#define CONFIG_BAUDRATE		115200
+
+#define XMK_STR(x)	#x
+#define MK_STR(x)	XMK_STR(x)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"netdev=" MK_STR(CONFIG_NETDEV) "\0"				\
+	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
+	"tftpflash=tftp $loadaddr $uboot;"				\
+		"protect off " MK_STR(TEXT_BASE) " +$filesize; "	\
+		"erase " MK_STR(TEXT_BASE) " +$filesize; "		\
+		"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "	\
+		"protect on " MK_STR(TEXT_BASE) " +$filesize; "		\
+		"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"	\
+	"fdtaddr=400000\0"						\
+	"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"				\
+	"ramdiskaddr=1000000\0"						\
+	"ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0"			\
+	"console=ttyS0\0"						\
+	"setbootargs=setenv bootargs "					\
+		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
+	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv rootdev /dev/nfs;"					\
+	"run setbootargs;"						\
+	"run setipargs;"						\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv rootdev /dev/ram;"					\
+	"run setbootargs;"						\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#undef MK_STR
+#undef XMK_STR
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index eb6ccb6..ac4b3e1 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -141,6 +141,9 @@
 #endif
 
 #define CFG_ID_EEPROM
+#ifdef CFG_ID_EEPROM
+#define CONFIG_ID_EEPROM
+#endif
 #define ID_EEPROM_ADDR		0x57
 
 
@@ -312,11 +315,8 @@
 #define CONFIG_CMD_NET
 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
 
-#define CONFIG_RTL8139
-#define CONFIG_SK98
-#define CONFIG_EEPRO100
-#define CONFIG_TULIP
-#ifdef CONFIG_TULIP
+#define CONFIG_ULI526X
+#ifdef CONFIG_ULI526X
 #define CONFIG_ETHADDR   00:E0:0C:00:00:01
 #endif
 
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 7f485c6..ab875f0 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -152,6 +152,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #endif
 
 #define CFG_ID_EEPROM	1
+#ifdef CFG_ID_EEPROM
+#define CONFIG_ID_EEPROM
+#endif
 #define ID_EEPROM_ADDR 0x57
 
 /*
diff --git a/include/linux/mtd/fsl_upm.h b/include/linux/mtd/fsl_upm.h
new file mode 100644
index 0000000..634ff02
--- /dev/null
+++ b/include/linux/mtd/fsl_upm.h
@@ -0,0 +1,39 @@
+/*
+ * FSL UPM NAND driver
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *                    Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __LINUX_MTD_NAND_FSL_UPM
+#define __LINUX_MTD_NAND_FSL_UPM
+
+#include <linux/mtd/nand.h>
+
+struct fsl_upm {
+	const u32 *array;
+	void __iomem *mdr;
+	void __iomem *mxmr;
+	void __iomem *mar;
+	void __iomem *io_addr;
+};
+
+struct fsl_upm_nand {
+	struct fsl_upm upm;
+
+	int width;
+	int upm_cmd_offset;
+	int upm_addr_offset;
+	int wait_pattern;
+	int (*dev_ready)(void);
+	int chip_delay;
+};
+
+extern int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun);
+
+#endif
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 7299ca0..39cecf2 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -725,13 +725,20 @@
 #define SCCR_USBCM_3			0x00F00000
 
 #elif defined(CONFIG_MPC8313)
-/* TSEC1 bits are for TSEC2 as well */
 #define SCCR_TSEC1CM			0xc0000000
 #define SCCR_TSEC1CM_SHIFT		30
+#define SCCR_TSEC1CM_0			0x00000000
 #define SCCR_TSEC1CM_1			0x40000000
 #define SCCR_TSEC1CM_2			0x80000000
 #define SCCR_TSEC1CM_3			0xC0000000
 
+#define SCCR_TSEC2CM			0x30000000
+#define SCCR_TSEC2CM_SHIFT		28
+#define SCCR_TSEC2CM_0			0x00000000
+#define SCCR_TSEC2CM_1			0x10000000
+#define SCCR_TSEC2CM_2			0x20000000
+#define SCCR_TSEC2CM_3			0x30000000
+
 #define SCCR_TSEC1ON			0x20000000
 #define SCCR_TSEC1ON_SHIFT		29
 #define SCCR_TSEC2ON			0x10000000
@@ -831,8 +838,6 @@
 #define SCCR_PCIEXP2CM_3		0x000c0000
 
 /* All of the four SATA controllers must have the same clock ratio */
-#define SCCR_SATA1CM			0x000000c0
-#define SCCR_SATA1CM_SHIFT		6
 #define SCCR_SATACM			0x000000ff
 #define SCCR_SATACM_SHIFT		0
 #define SCCR_SATACM_0			0x00000000
@@ -852,6 +857,7 @@
  */
 #define CSCONFIG_EN			0x80000000
 #define CSCONFIG_AP			0x00800000
+#define CSCONFIG_ODT_WR_ACS		0x00010000
 #define CSCONFIG_ROW_BIT		0x00000700
 #define CSCONFIG_ROW_BIT_12		0x00000000
 #define CSCONFIG_ROW_BIT_13		0x00000100
@@ -1480,6 +1486,7 @@
 
 /* DDRCDR - DDR Control Driver Register
  */
+#define DDRCDR_DHC_EN		0x80000000
 #define DDRCDR_EN		0x40000000
 #define DDRCDR_PZ		0x3C000000
 #define DDRCDR_PZ_MAXZ		0x00000000