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authorNobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>2008-07-03 23:11:02 +0900
committerNobuhiro Iwamatsu <iwamatsu@nigauri.org>2008-08-31 22:51:55 +0900
commit6ede753ddf52a7b0f992d9bccbe5e4a0968ca475 (patch)
tree9966e388ce9ad0787741dc5b28df6083c864f342 /include
parent6ad43d0dd86b612895ddc7f480eb6cdfe793adf9 (diff)
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sh: Add support Renesas SH7203 processor
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'include')
-rw-r--r--include/asm-sh/cpu_sh7203.h41
1 files changed, 41 insertions, 0 deletions
diff --git a/include/asm-sh/cpu_sh7203.h b/include/asm-sh/cpu_sh7203.h
new file mode 100644
index 0000000..77dcac4
--- /dev/null
+++ b/include/asm-sh/cpu_sh7203.h
@@ -0,0 +1,41 @@
+#ifndef _ASM_CPU_SH7203_H_
+#define _ASM_CPU_SH7203_H_
+
+/* Cache */
+#define CCR1 0xFFFC1000
+#define CCR CCR1
+
+/* PFC */
+#define PACR 0xA4050100
+#define PBCR 0xA4050102
+#define PCCR 0xA4050104
+#define PETCR 0xA4050106
+
+/* Port Data Registers */
+#define PADR 0xA4050120
+#define PBDR 0xA4050122
+#define PCDR 0xA4050124
+
+/* BSC */
+
+/* SDRAM controller */
+
+/* SCIF */
+#define SCSMR_0 0xFFFE8000
+#define SCIF0_BASE SCSMR_0
+
+/* Timer(CMT) */
+#define CMSTR 0xFFFEC000
+#define CMCSR_0 0xFFFEC002
+#define CMCNT_0 0xFFFEC004
+#define CMCOR_0 0xFFFEC006
+#define CMCSR_1 0xFFFEC008
+#define CMCNT_1 0xFFFEC00A
+#define CMCOR_1 0xFFFEC00C
+
+/* On chip oscillator circuits */
+#define FRQCR 0xA415FF80
+#define WTCNT 0xA415FF84
+#define WTCSR 0xA415FF86
+
+#endif /* _ASM_CPU_SH7203_H_ */