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| author | Nitin Garg <nitin.garg@freescale.com> | 2014-05-27 18:39:39 -0500 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2014-06-13 10:17:01 -0500 |
| commit | 6d87677d499f71a0ed3994f414bdbf9a7e6a4099 (patch) | |
| tree | 78f3abe568e7012bdbcb7c3814446d3bbf326a8f /include | |
| parent | e8072eb17fe56a72e000319cd7a9aa42eb4e1cef (diff) | |
| download | u-boot-imx-6d87677d499f71a0ed3994f414bdbf9a7e6a4099.zip u-boot-imx-6d87677d499f71a0ed3994f414bdbf9a7e6a4099.tar.gz u-boot-imx-6d87677d499f71a0ed3994f414bdbf9a7e6a4099.tar.bz2 | |
ENGR00315499-14 ARM:imx6:sabresd/arm2 Add USB HOST BSP support
Enable the USB EHCI on sabresd and arm2 boards to support USB mass
storage device.
Pins are configured in board_ehci_hcd_init for VBUS control.
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/mx6qarm2.h | 12 | ||||
| -rw-r--r-- | include/configs/mx6sabresd.h | 12 |
2 files changed, 24 insertions, 0 deletions
diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h index 66b48ba..db51032 100644 --- a/include/configs/mx6qarm2.h +++ b/include/configs/mx6qarm2.h @@ -155,4 +155,16 @@ #define CONFIG_OF_LIBFDT #define CONFIG_CMD_BOOTZ +/* USB Configs */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + #endif /* __CONFIG_H */ diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 053aa8d..10cbdf7 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -27,6 +27,18 @@ #include "mx6sabre_common.h" +/* USB Configs */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */ + #define CONFIG_SYS_FSL_USDHC_NUM 3 #if defined(CONFIG_ENV_IS_IN_MMC) #define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC3 */ |