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authorTom Rini <trini@ti.com>2013-11-11 09:40:34 -0500
committerTom Rini <trini@ti.com>2013-11-11 09:40:34 -0500
commit60390d70be7336b2441f5f69bd4f5affa83d064d (patch)
tree857824f8b7f5f7aaf2f5dac91eea94392818a7a0 /include
parent85b8c5c4bf80025de4632ae6c9a8a606e51508a4 (diff)
parenta3e80904fb07cda792e636704e3b3950d1446af3 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-mips
Diffstat (limited to 'include')
-rw-r--r--include/configs/malta.h (renamed from include/configs/qemu-malta.h)45
-rw-r--r--include/msc01.h135
-rw-r--r--include/pci.h6
-rw-r--r--include/pci_ids.h3
-rw-r--r--include/pci_msc01.h17
5 files changed, 188 insertions, 18 deletions
diff --git a/include/configs/qemu-malta.h b/include/configs/malta.h
index 03514d1..4098e72 100644
--- a/include/configs/qemu-malta.h
+++ b/include/configs/malta.h
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: GPL-2.0
*/
-#ifndef _QEMU_MALTA_CONFIG_H
-#define _QEMU_MALTA_CONFIG_H
+#ifndef _MALTA_CONFIG_H
+#define _MALTA_CONFIG_H
#include <asm/addrspace.h>
#include <asm/malta.h>
@@ -13,12 +13,21 @@
/*
* System configuration
*/
-#define CONFIG_QEMU_MALTA
+#define CONFIG_MALTA
+
+#define CONFIG_MEMSIZE_IN_BYTES
#define CONFIG_PCI
#define CONFIG_PCI_GT64120
+#define CONFIG_PCI_MSC01
#define CONFIG_PCI_PNP
#define CONFIG_PCNET
+#define CONFIG_PCNET_79C973
+#define PCNET_HAS_PROM
+
+#define CONFIG_MISC_INIT_R
+#define CONFIG_RTC_MC146818
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
/*
* CPU Configuration
@@ -26,10 +35,6 @@
#define CONFIG_SYS_MHZ 250 /* arbitrary value */
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
-#define CONFIG_SYS_DCACHE_SIZE 16384 /* arbitrary value */
-#define CONFIG_SYS_ICACHE_SIZE 16384 /* arbitrary value */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* arbitrary value */
-
#define CONFIG_SWAP_IO_SPACE
/*
@@ -54,9 +59,9 @@
* Console configuration
*/
#if defined(CONFIG_SYS_LITTLE_ENDIAN)
-#define CONFIG_SYS_PROMPT "qemu-maltael # "
+#define CONFIG_SYS_PROMPT "maltael # "
#else
-#define CONFIG_SYS_PROMPT "qemu-malta # "
+#define CONFIG_SYS_PROMPT "malta # "
#endif
#define CONFIG_SYS_CBSIZE 256
@@ -76,16 +81,11 @@
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK 115200
-#define CONFIG_SYS_NS16550_COM1 CKSEG1ADDR(MALTA_UART_BASE)
+#define CONFIG_SYS_NS16550_COM1 CKSEG1ADDR(MALTA_GT_UART0_BASE)
+#define CONFIG_SYS_NS16550_COM2 CKSEG1ADDR(MALTA_MSC01_UART0_BASE)
#define CONFIG_CONS_INDEX 1
/*
- * Environment
- */
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_SIZE 0x10000
-
-/*
* Flash configuration
*/
#define CONFIG_SYS_FLASH_BASE (KSEG1 | MALTA_FLASH_BASE)
@@ -96,6 +96,15 @@
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_ADDR \
+ (CONFIG_SYS_FLASH_BASE + (4 << 20) - CONFIG_ENV_SIZE)
+
+/*
* Commands
*/
#include <config_cmd_default.h>
@@ -105,9 +114,11 @@
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_NFS
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_SYS_LONGHELP /* verbose help, undef to save memory */
-#endif /* _QEMU_MALTA_CONFIG_H */
+#endif /* _MALTA_CONFIG_H */
diff --git a/include/msc01.h b/include/msc01.h
new file mode 100644
index 0000000..37cf963
--- /dev/null
+++ b/include/msc01.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MSC01_H__
+#define __MSC01_H__
+
+/*
+ * Bus Interface Unit
+ */
+
+#define MSC01_BIU_IP1BAS1L_OFS 0x0208
+#define MSC01_BIU_IP1MSK1L_OFS 0x0218
+#define MSC01_BIU_IP1BAS2L_OFS 0x0248
+#define MSC01_BIU_IP1MSK2L_OFS 0x0258
+#define MSC01_BIU_IP2BAS1L_OFS 0x0288
+#define MSC01_BIU_IP2MSK1L_OFS 0x0298
+#define MSC01_BIU_IP2BAS2L_OFS 0x02c8
+#define MSC01_BIU_IP2MSK2L_OFS 0x02d8
+#define MSC01_BIU_IP3BAS1L_OFS 0x0308
+#define MSC01_BIU_IP3MSK1L_OFS 0x0318
+#define MSC01_BIU_IP3BAS2L_OFS 0x0348
+#define MSC01_BIU_IP3MSK2L_OFS 0x0358
+#define MSC01_BIU_MCBAS1L_OFS 0x0388
+#define MSC01_BIU_MCMSK1L_OFS 0x0398
+#define MSC01_BIU_MCBAS2L_OFS 0x03c8
+#define MSC01_BIU_MCMSK2L_OFS 0x03d8
+
+/*
+ * PCI Bridge
+ */
+
+#define MSC01_PCI_SC2PMBASL_OFS 0x0208
+#define MSC01_PCI_SC2PMMSKL_OFS 0x0218
+#define MSC01_PCI_SC2PMMAPL_OFS 0x0228
+#define MSC01_PCI_SC2PIOBASL_OFS 0x0248
+#define MSC01_PCI_SC2PIOMSKL_OFS 0x0258
+#define MSC01_PCI_SC2PIOMAPL_OFS 0x0268
+#define MSC01_PCI_P2SCMSKL_OFS 0x0308
+#define MSC01_PCI_P2SCMAPL_OFS 0x0318
+#define MSC01_PCI_INTSTAT_OFS 0x0608
+#define MSC01_PCI_CFGADDR_OFS 0x0610
+#define MSC01_PCI_CFGDATA_OFS 0x0618
+#define MSC01_PCI_HEAD0_OFS 0x2000
+#define MSC01_PCI_HEAD1_OFS 0x2008
+#define MSC01_PCI_HEAD2_OFS 0x2010
+#define MSC01_PCI_HEAD3_OFS 0x2018
+#define MSC01_PCI_HEAD4_OFS 0x2020
+#define MSC01_PCI_HEAD5_OFS 0x2028
+#define MSC01_PCI_HEAD6_OFS 0x2030
+#define MSC01_PCI_HEAD7_OFS 0x2038
+#define MSC01_PCI_HEAD8_OFS 0x2040
+#define MSC01_PCI_HEAD9_OFS 0x2048
+#define MSC01_PCI_HEAD10_OFS 0x2050
+#define MSC01_PCI_HEAD11_OFS 0x2058
+#define MSC01_PCI_HEAD12_OFS 0x2060
+#define MSC01_PCI_HEAD13_OFS 0x2068
+#define MSC01_PCI_HEAD14_OFS 0x2070
+#define MSC01_PCI_HEAD15_OFS 0x2078
+#define MSC01_PCI_BAR0_OFS 0x2220
+#define MSC01_PCI_CFG_OFS 0x2380
+#define MSC01_PCI_SWAP_OFS 0x2388
+
+#define MSC01_PCI_SC2PMMSKL_MSK_MSK 0xff000000
+#define MSC01_PCI_SC2PIOMSKL_MSK_MSK 0xff000000
+
+#define MSC01_PCI_INTSTAT_TA_SHF 6
+#define MSC01_PCI_INTSTAT_TA_MSK (0x1 << MSC01_PCI_INTSTAT_TA_SHF)
+#define MSC01_PCI_INTSTAT_MA_SHF 7
+#define MSC01_PCI_INTSTAT_MA_MSK (0x1 << MSC01_PCI_INTSTAT_MA_SHF)
+
+#define MSC01_PCI_CFGADDR_BNUM_SHF 16
+#define MSC01_PCI_CFGADDR_BNUM_MSK (0xff << MSC01_PCI_CFGADDR_BNUM_SHF)
+#define MSC01_PCI_CFGADDR_DNUM_SHF 11
+#define MSC01_PCI_CFGADDR_DNUM_MSK (0x1f << MSC01_PCI_CFGADDR_DNUM_SHF)
+#define MSC01_PCI_CFGADDR_FNUM_SHF 8
+#define MSC01_PCI_CFGADDR_FNUM_MSK (0x3 << MSC01_PCI_CFGADDR_FNUM_SHF)
+#define MSC01_PCI_CFGADDR_RNUM_SHF 2
+#define MSC01_PCI_CFGADDR_RNUM_MSK (0x3f << MSC01_PCI_CFGADDR_RNUM_SHF)
+
+#define MSC01_PCI_HEAD0_VENDORID_SHF 0
+#define MSC01_PCI_HEAD0_DEVICEID_SHF 16
+
+#define MSC01_PCI_HEAD2_REV_SHF 0
+#define MSC01_PCI_HEAD2_CLASS_SHF 16
+
+#define MSC01_PCI_CFG_EN_SHF 15
+#define MSC01_PCI_CFG_EN_MSK (0x1 << MSC01_PCI_CFG_EN_SHF)
+#define MSC01_PCI_CFG_G_SHF 16
+#define MSC01_PCI_CFG_G_MSK (0x1 << MSC01_PCI_CFG_G_SHF)
+#define MSC01_PCI_CFG_RA_SHF 17
+#define MSC01_PCI_CFG_RA_MSK (0x1 << MSC01_PCI_CFG_RA_SHF)
+
+#define MSC01_PCI_SWAP_BAR0_BSWAP_SHF 0
+#define MSC01_PCI_SWAP_IO_BSWAP_SHF 18
+
+/*
+ * Peripheral Bus Controller
+ */
+
+#define MSC01_PBC_CLKCFG_OFS 0x0100
+#define MSC01_PBC_CS0CFG_OFS 0x0400
+#define MSC01_PBC_CS0TIM_OFS 0x0500
+#define MSC01_PBC_CS0RW_OFS 0x0600
+
+#define MSC01_PBC_CLKCFG_SHF 0
+#define MSC01_PBC_CLKCFG_MSK (0x1f << MSC01_PBC_CLKCFG_SHF)
+
+#define MSC01_PBC_CS0CFG_WS_SHF 0
+#define MSC01_PBC_CS0CFG_WS_MSK (0x1f << MSC01_PBC_CS0CFG_WS_SHF)
+#define MSC01_PBC_CS0CFG_WSIDLE_SHF 8
+#define MSC01_PBC_CS0CFG_WSIDLE_MSK (0x1f << MSC01_PBC_CS0CFG_WSIDLE_SHF)
+#define MSC01_PBC_CS0CFG_DTYP_SHF 16
+#define MSC01_PBC_CS0CFG_DTYP_MSK (0x3 << MSC01_PBC_CS0CFG_DTYP_SHF)
+#define MSC01_PBC_CS0CFG_ADM_SHF 20
+#define MSC01_PBC_CS0CFG_ADM_MSK (0x1 << MSC01_PBC_CS0CFG_ADM_SHF)
+
+#define MSC01_PBC_CS0TIM_CAT_SHF 0
+#define MSC01_PBC_CS0TIM_CAT_MSK (0x1f << MSC01_PBC_CS0TIM_CAT_SHF)
+#define MSC01_PBC_CS0TIM_CDT_SHF 8
+#define MSC01_PBC_CS0TIM_CDT_MSK (0x1f << MSC01_PBC_CS0TIM_CDT_SHF)
+
+#define MSC01_PBC_CS0RW_WAT_SHF 0
+#define MSC01_PBC_CS0RW_WAT_MSK (0x1f << MSC01_PBC_CS0RW_WAT_SHF)
+#define MSC01_PBC_CS0RW_WDT_SHF 8
+#define MSC01_PBC_CS0RW_WDT_MSK (0x1f << MSC01_PBC_CS0RW_WDT_SHF)
+#define MSC01_PBC_CS0RW_RAT_SHF 16
+#define MSC01_PBC_CS0RW_RAT_MSK (0x1f << MSC01_PBC_CS0RW_RAT_SHF)
+#define MSC01_PBC_CS0RW_RDT_SHF 24
+#define MSC01_PBC_CS0RW_RDT_MSK (0x1f << MSC01_PBC_CS0RW_RDT_SHF)
+
+#endif /* __MSC01_H__ */
diff --git a/include/pci.h b/include/pci.h
index d462479..461f17c 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -417,6 +417,8 @@
#include <pci_ids.h>
+#ifndef __ASSEMBLY__
+
#ifdef CONFIG_SYS_PCI_64BIT
typedef u64 pci_addr_t;
typedef u64 pci_size_t;
@@ -667,4 +669,6 @@ extern void pci_mpc824x_init (struct pci_controller *hose);
#ifdef CONFIG_MPC85xx
extern void pci_mpc85xx_init (struct pci_controller *hose);
#endif
-#endif /* _PCI_H */
+
+#endif /* __ASSEMBLY__ */
+#endif /* _PCI_H */
diff --git a/include/pci_ids.h b/include/pci_ids.h
index 2c6dfd4..6bab677 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -2170,6 +2170,9 @@
#define PCI_DEVICE_ID_ENE_720 0x1421
#define PCI_DEVICE_ID_ENE_722 0x1422
+#define PCI_VENDOR_ID_MIPS 0x153f
+#define PCI_DEVICE_ID_MIPS_MSC01 0x0001
+
#define PCI_SUBVENDOR_ID_PERLE 0x155f
#define PCI_SUBDEVICE_ID_PCI_RAS4 0xf001
#define PCI_SUBDEVICE_ID_PCI_RAS8 0xf010
diff --git a/include/pci_msc01.h b/include/pci_msc01.h
new file mode 100644
index 0000000..54945a7
--- /dev/null
+++ b/include/pci_msc01.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __PCI_MSC01_H__
+#define __PCI_MSC01_H__
+
+extern void msc01_pci_init(void *base, unsigned long sys_bus,
+ unsigned long sys_phys, unsigned long sys_size,
+ unsigned long mem_bus, unsigned long mem_phys,
+ unsigned long mem_size, unsigned long io_bus,
+ unsigned long io_phys, unsigned long io_size);
+
+#endif /* __PCI_MSC01_H__ */