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| author | Ranjani Vaidyanathan <ra5478@freescale.com> | 2011-06-22 17:08:46 -0500 |
|---|---|---|
| committer | Ranjani Vaidyanathan <ra5478@freescale.com> | 2011-06-22 18:16:20 -0500 |
| commit | 88d03a4087ad1c13b546e7d0962a885633d01b76 (patch) | |
| tree | fcadf0be0187fc62e700dfc99ab67f2cd68ae51b /include | |
| parent | 65317a185c154cbe3f5dbbf3358cbd4ffbe52c81 (diff) | |
| download | u-boot-imx-88d03a4087ad1c13b546e7d0962a885633d01b76.zip u-boot-imx-88d03a4087ad1c13b546e7d0962a885633d01b76.tar.gz u-boot-imx-88d03a4087ad1c13b546e7d0962a885633d01b76.tar.bz2 | |
ENGR00151966: MX51 - Apply SW workaround for the PLL1 unlock HW issue.
Apply the following SW workaround to fix the PLL unlock issue.
1.Move all the clock sources which are currently running
on PLL1 from PLL1 to PLL2
2.Clear AREN bit in PLL1 (to avoid restart during MFN change)
3.Program the PLL1 to the next settings:
a. MFI = 8
b. MFD = 179
c. MFN = 180
d. PLM = 1
4.Manually restart the PLL1
5.Wait to PLL1 to lock
6.Reprogram the PLL1 to the next settings:
a. MFI = 60, others keep same
7.Load the MFN
8.Wait for LDREQ and delay ~4.6us
9.Switch the clocks which were previously moved from PLL1 to PLL2 back to PLL1
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions