Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts.

All of the PCI/PCI-Express driver and initialization code that
was in the MPC8641HPCN port has now been moved into the common
drivers/fsl_pci_init.c.  In a subsequent patch, this will be
utilized by the 85xx ports as well.

Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added.

Also enable the second PCI-Express controller on 8641
by getting its BATS and CFG_ setup right.

Fixed a u16 vendor compiler warning in AHCI driver too.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>

3 files changed, 182 insertions, 18 deletions

diff --git a/include/asm-ppc/immap_fsl_pci.h b/include/asm-ppc/immap_fsl_pci.h
new file mode 100644
index 0000000..bd732b6
--- /dev/null
+++ b/include/asm-ppc/immap_fsl_pci.h
@@ -0,0 +1,150 @@
+/* (C) Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __IMMAP_85xx_fsl_pci__
+#define __IMMAP_85xx_fsl_pci__
+
+/*
+ * Common PCI/PCIE Register structure for mpc85xx and mpc86xx
+ */
+
+/*
+ * PCI Translation Registers
+ */
+typedef struct pci_outbound_window {
+	u32	potar;		/* 0x00 - Address */
+	u32	potear;		/* 0x04 - Address Extended */
+	u32	powbar;		/* 0x08 - Window Base Address */
+	u32	res1;
+	u32	powar;		/* 0x10 - Window Attributes */
+#define POWAR_EN	0x80000000
+#define POWAR_IO_READ	0x00080000
+#define POWAR_MEM_READ	0x00040000
+#define POWAR_IO_WRITE	0x00008000
+#define POWAR_MEM_WRITE	0x00004000
+	u32	res2[3];
+} pot_t;
+
+typedef struct pci_inbound_window {
+	u32	pitar;		/* 0x00 - Address */
+	u32	res1;
+	u32	piwbar;		/* 0x08 - Window Base Address */
+	u32	piwbear;	/* 0x0c - Window Base Address Extended */
+	u32	piwar;		/* 0x10 - Window Attributes */
+#define PIWAR_EN		0x80000000
+#define PIWAR_PF		0x20000000
+#define PIWAR_LOCAL		0x00f00000
+#define PIWAR_READ_SNOOP	0x00050000
+#define PIWAR_WRITE_SNOOP	0x00005000
+	u32	res2[3];
+} pit_t;
+
+/* PCI/PCI Express Registers */
+typedef struct ccsr_pci {
+	u32	cfg_addr;	/* 0x000 - PCI Configuration Address Register */
+	u32	cfg_data;	/* 0x004 - PCI Configuration Data Register */
+	u32	int_ack;	/* 0x008 - PCI Interrupt Acknowledge Register */
+	u32	out_comp_to;	/* 0x00C - PCI Outbound Completion Timeout Register */
+	u32	out_conf_to;	/* 0x010 - PCI Configuration Timeout Register */
+	u32	config;		/* 0x014 - PCIE CONFIG Register */
+	char	res2[8];
+	u32	pme_msg_det;	/* 0x020 - PCIE PME & message detect register */
+	u32	pme_msg_dis;	/* 0x024 - PCIE PME & message disable register */
+	u32	pme_msg_int_en;	/* 0x028 - PCIE PME & message interrupt enable register */
+	u32	pm_command;	/* 0x02c - PCIE PM Command register */
+	char	res4[3016];	/*     (- #xbf8	 #x30)3016 */
+	u32	block_rev1;	/* 0xbf8 - PCIE Block Revision register 1 */
+	u32	block_rev2;	/* 0xbfc - PCIE Block Revision register 2 */
+
+	pot_t	pot[5];		/* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3, and 4 */
+	u32	res5[64];
+	pit_t	pit[3];		/* 0xda0 - 0xdff Inbound ATMU's 3, 2, and 1 */
+#define PIT3 0
+#define PIT2 1
+#define PIT1 2
+
+#if 0
+	u32	potar0;		/* 0xc00 - PCI Outbound Transaction Address Register 0 */
+	u32	potear0;	/* 0xc04 - PCI Outbound Translation Extended Address Register 0 */
+	char	res5[8];
+	u32	powar0;		/* 0xc10 - PCI Outbound Window Attributes Register 0 */
+	char	res6[12];
+	u32	potar1;		/* 0xc20 - PCI Outbound Transaction Address Register 1 */
+	u32	potear1;	/* 0xc24 - PCI Outbound Translation Extended Address Register 1 */
+	u32	powbar1;	/* 0xc28 - PCI Outbound Window Base Address Register 1 */
+	char	res7[4];
+	u32	powar1;		/* 0xc30 - PCI Outbound Window Attributes Register 1 */
+	char	res8[12];
+	u32	potar2;		/* 0xc40 - PCI Outbound Transaction Address Register 2 */
+	u32	potear2;	/* 0xc44 - PCI Outbound Translation Extended Address Register 2 */
+	u32	powbar2;	/* 0xc48 - PCI Outbound Window Base Address Register 2 */
+	char	res9[4];
+	u32	powar2;		/* 0xc50 - PCI Outbound Window Attributes Register 2 */
+	char	res10[12];
+	u32	potar3;		/* 0xc60 - PCI Outbound Transaction Address Register 3 */
+	u32	potear3;	/* 0xc64 - PCI Outbound Translation Extended Address Register 3 */
+	u32	powbar3;	/* 0xc68 - PCI Outbound Window Base Address Register 3 */
+	char	res11[4];
+	u32	powar3;		/* 0xc70 - PCI Outbound Window Attributes Register 3 */
+	char	res12[12];
+	u32	potar4;		/* 0xc80 - PCI Outbound Transaction Address Register 4 */
+	u32	potear4;	/* 0xc84 - PCI Outbound Translation Extended Address Register 4 */
+	u32	powbar4;	/* 0xc88 - PCI Outbound Window Base Address Register 4 */
+	char	res13[4];
+	u32	powar4;		/* 0xc90 - PCI Outbound Window Attributes Register 4 */
+	char	res14[268];
+	u32	pitar3;		/* 0xda0 - PCI Inbound Translation Address Register 3 */
+	char	res15[4];
+	u32	piwbar3;	/* 0xda8 - PCI Inbound Window Base Address Register 3 */
+	u32	piwbear3;	/* 0xdac - PCI Inbound Window Base Extended Address Register 3 */
+	u32	piwar3;		/* 0xdb0 - PCI Inbound Window Attributes Register 3 */
+	char	res16[12];
+	u32	pitar2;		/* 0xdc0 - PCI Inbound Translation Address Register 2 */
+	char	res17[4];
+	u32	piwbar2;	/* 0xdc8 - PCI Inbound Window Base Address Register 2 */
+	u32	piwbear2;	/* 0xdcc - PCI Inbound Window Base Extended Address Register 2 */
+	u32	piwar2;		/* 0xdd0 - PCI Inbound Window Attributes Register 2 */
+	char	res18[12];
+	u32	pitar1;		/* 0xde0 - PCI Inbound Translation Address Register 1 */
+	char	res19[4];
+	u32	piwbar1;	/* 0xde8 - PCI Inbound Window Base Address Register 1 */
+	char	res20[4];
+	u32	piwar1;		/* 0xdf0 - PCI Inbound Window Attributes Register 1 */
+	char	res21[12];
+#endif
+	u32	pedr;		/* 0xe00 - PCI Error Detect Register */
+	u32	pecdr;		/* 0xe04 - PCI Error Capture Disable Register */
+	u32	peer;		/* 0xe08 - PCI Error Interrupt Enable Register */
+	u32	peattrcr;	/* 0xe0c - PCI Error Attributes Capture Register */
+	u32	peaddrcr;	/* 0xe10 - PCI Error Address Capture Register */
+/*	u32	perr_disr	 * 0xe10 - PCIE Erorr Disable Register */
+	u32	peextaddrcr;	/* 0xe14 - PCI	Error Extended Address Capture Register */
+	u32	pedlcr;		/* 0xe18 - PCI Error Data Low Capture Register */
+	u32	pedhcr;		/* 0xe1c - PCI Error Error Data High Capture Register */
+	u32	gas_timr;	/* 0xe20 - PCI Gasket Timer Register */
+/*	u32	perr_cap_stat;	 * 0xe20 - PCIE Error Capture Status Register */
+	char	res22[4];
+	u32	perr_cap0;	/* 0xe28 - PCIE Error Capture Register 0 */
+	u32	perr_cap1;	/* 0xe2c - PCIE Error Capture Register 1 */
+	u32	perr_cap2;	/* 0xe30 - PCIE Error Capture Register 2 */
+	u32	perr_cap3;	/* 0xe34 - PCIE Error Capture Register 3 */
+	char	res23[456];	/*     (- #x1000 #xe38) 456 */
+} ccsr_fsl_pci_t;
+
+#endif /*__IMMAP_fsl_pci__*/
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 808c19f..5a511e5 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -46,8 +46,10 @@
 
 #define CFG_RESET_ADDRESS    0xfff00100
 
-/*#undef CONFIG_PCI*/
-#define CONFIG_PCI
+#define CONFIG_PCI		1	/* Enable PCI/PCIE */
+#define CONFIG_PCI1		1	/* PCIE controler 1 (ULI bridge) */
+#define CONFIG_PCI2		1	/* PCIE controler 2 (slot) */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 
 #define CONFIG_TSEC_ENET 		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
@@ -76,6 +78,9 @@
 #define L2_ENABLE	(L2CR_L2E)
 
 #ifndef CONFIG_SYS_CLK_FREQ
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
 #endif
 
@@ -93,6 +98,9 @@
 #define CFG_CCSRBAR		0xf8000000	/* relocated CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
+#define CFG_PCI1_ADDR		(CFG_CCSRBAR+0x8000)
+#define CFG_PCI2_ADDR		(CFG_CCSRBAR+0x9000)
+
 /*
  * DDR Setup
  */
@@ -296,9 +304,9 @@
 #define CFG_PCI1_MEM_BASE	0x80000000
 #define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
 #define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI1_IO_BASE	0xe2000000
-#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
+#define CFG_PCI1_IO_BASE	0x00000000
+#define CFG_PCI1_IO_PHYS	0xe2000000
+#define CFG_PCI1_IO_SIZE	0x00100000	/* 1M */
 
 /* PCI view of System Memory */
 #define CFG_PCI_MEMORY_BUS      0x00000000
@@ -311,10 +319,10 @@
 
 #define CFG_PCI2_MEM_BASE	0xa0000000
 #define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
-#define CFG_PCI2_MEM_SIZE	0x10000000	/* 256M */
-#define CFG_PCI2_IO_BASE	0xe3000000
-#define CFG_PCI2_IO_PHYS	CFG_PCI2_IO_BASE
-#define CFG_PCI2_IO_SIZE	0x1000000	/* 16M */
+#define CFG_PCI2_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI2_IO_BASE	0x00000000
+#define CFG_PCI2_IO_PHYS	0xe3000000
+#define CFG_PCI2_IO_SIZE	0x00100000	/* 1M */
 
 #if defined(CONFIG_PCI)
 
@@ -396,20 +404,20 @@
  * 0xa000_0000  512M   PCI-Express 2 Memory
  *	Changed it for operating from 0xd0000000
  */
-#define CFG_DBAT1L      ( CFG_PCI1_MEM_BASE | BATL_PP_RW \
+#define CFG_DBAT1L      ( CFG_PCI1_MEM_PHYS | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT1U      (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_IBAT1L      (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_DBAT1U	(CFG_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP)
+#define CFG_IBAT1L	(CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CFG_IBAT1U      CFG_DBAT1U
 
 /*
  * BAT2         512M   Cache-inhibited, guarded
  * 0xc000_0000  512M   RapidIO Memory
  */
-#define CFG_DBAT2L      (CFG_RIO_MEM_BASE | BATL_PP_RW \
+#define CFG_DBAT2L      (CFG_RIO_MEM_PHYS | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT2U      (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
-#define CFG_IBAT2L      (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_DBAT2U	(CFG_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP)
+#define CFG_IBAT2L	(CFG_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CFG_IBAT2U      CFG_DBAT2U
 
 /*
@@ -428,10 +436,10 @@
  * 0xe300_0000  16M    PCI-Express 2 I/0
  *    Note that this is at 0xe0000000
  */
-#define CFG_DBAT4L      ( CFG_PCI1_IO_BASE | BATL_PP_RW \
+#define CFG_DBAT4L      ( CFG_PCI1_IO_PHYS | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT4U      (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CFG_IBAT4L      (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_DBAT4U	(CFG_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_IBAT4L	(CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CFG_IBAT4U      CFG_DBAT4U
 
 /*
diff --git a/include/pci.h b/include/pci.h
index 7c9a0e3..8e5dacc 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -302,6 +302,12 @@
 #define PCI_MAX_PCI_DEVICES	32
 #define PCI_MAX_PCI_FUNCTIONS	8
 
+#define PCI_DCR		0x54    /* PCIe Device Control Register */
+#define PCI_DSR		0x56    /* PCIe Device Status Register */
+#define PCI_LSR		0x5e    /* PCIe Link Status Register */
+#define PCI_LTSSM	0x404   /* PCIe Link Training, Status State Machine */
+#define  PCI_LTSSM_L0	0x16    /* L0 state */
+
 /* Include the ID list */
 
 #include <pci_ids.h>