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| author | Allen Xu <allen.xu@freescale.com> | 2011-11-03 11:15:48 +0800 |
|---|---|---|
| committer | Allen Xu <allen.xu@freescale.com> | 2011-11-03 11:29:26 +0800 |
| commit | 13b7fad6b3fc8034738543f5946378239aae440f (patch) | |
| tree | 12e3d8a4c7462ac6d38c22cb9261c512b748b2bc /include | |
| parent | 01a080fe6c11de531f79d0a05d7a06dac1708e41 (diff) | |
| download | u-boot-imx-13b7fad6b3fc8034738543f5946378239aae440f.zip u-boot-imx-13b7fad6b3fc8034738543f5946378239aae440f.tar.gz u-boot-imx-13b7fad6b3fc8034738543f5946378239aae440f.tar.bz2 | |
ENGR00161254 MX6Q: Add NAND support in Uboot
Add iomux and clock setting in Uboot code to support NAND, due to
the conflict between NAND and SD, NAND function is not enabled in
default configuration.
Signed-off-by: Allen Xu <allen.xu@freescale.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-arm/arch-mx6/mx6.h | 5 | ||||
| -rw-r--r-- | include/configs/mx6q_arm2.h | 27 |
2 files changed, 32 insertions, 0 deletions
diff --git a/include/asm-arm/arch-mx6/mx6.h b/include/asm-arm/arch-mx6/mx6.h index 1a984de..ae52fa2 100644 --- a/include/asm-arm/arch-mx6/mx6.h +++ b/include/asm-arm/arch-mx6/mx6.h @@ -169,6 +169,9 @@ #define CSD1_DDR_BASE_ADDR MMDC1_ARB_BASE_ADDR #define CS0_BASE_ADDR WEIM_ARB_BASE_ADDR #define NAND_FLASH_BASE_ADDR APBH_DMA_ARB_BASE_ADDR +#define ABPHDMA_BASE_ADDR APBH_DMA_ARB_BASE_ADDR +#define GPMI_BASE_ADDR (APBH_DMA_ARB_BASE_ADDR + 0x02000) +#define BCH_BASE_ADDR (APBH_DMA_ARB_BASE_ADDR + 0x04000) /* Defines for Blocks connected via AIPS (SkyBlue) */ #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR @@ -652,6 +655,8 @@ enum mxc_clock { MXC_ESDHC4_CLK, MXC_SATA_CLK, MXC_NFC_CLK, + MXC_GPMI_CLK, + MXC_BCH_CLK, }; enum mxc_peri_clocks { diff --git a/include/configs/mx6q_arm2.h b/include/configs/mx6q_arm2.h index c9bff96..e21bfad 100644 --- a/include/configs/mx6q_arm2.h +++ b/include/configs/mx6q_arm2.h @@ -237,6 +237,32 @@ #define CONFIG_LIBATA #endif +/* + * GPMI Nand Configs + */ +/* #define CONFIG_CMD_NAND */ + +#ifdef CONFIG_CMD_NAND + #define CONFIG_NAND_GPMI + #define CONFIG_GPMI_NFC_SWAP_BLOCK_MARK + #define CONFIG_GPMI_NFC_V2 + + #define CONFIG_GPMI_REG_BASE GPMI_BASE_ADDR + #define CONFIG_BCH_REG_BASE BCH_BASE_ADDR + + #define NAND_MAX_CHIPS 8 + #define CONFIG_SYS_NAND_BASE 0x40000000 + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + + #define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMD_FAT 1 + #define CONFIG_CMD_EXT2 1 + + /* NAND is the unique module invoke APBH-DMA */ + #define CONFIG_APBH_DMA_V2 + #define CONFIG_MXS_DMA_REG_BASE ABPHDMA_BASE_ADDR +#endif + /*----------------------------------------------------------------------- * Stack sizes * @@ -260,6 +286,7 @@ /* Monitor at beginning of flash */ #define CONFIG_FSL_ENV_IN_MMC +/* #define CONFIG_FSL_ENV_IN_NAND */ /* #define CONFIG_FSL_ENV_IN_SATA */ #define CONFIG_ENV_SECT_SIZE (8 * 1024) |