ENGR00179013 : MX6Solo/Quad : SABREAUTO: Add Parallel NOR Support

-Added u-boot config CONFIG_CMD_WEIMNOR for MX6Solo/Quad SABREAUTO to
support WEIM NOR.
- CONFIG_FLASH_HEADER_OFFSET is 0x1000 for WEIM NOR.
-SPI NOR and WEIM NOR has pin conflicts, either one can be enabled.
- mx6q_sabreauto_config, mx6solo_sabreauto_config configured default
for SPI NOR.
-In order to enable  the read/write commands and to boot from WEIM NOR,
need to enable the CONFIG_CMD_WEIMNOR. This will disable SPI-NOR

Signed-off-by: Prabhu Sundararaj <b36876@freescale.com>

2 files changed, 52 insertions, 7 deletions

diff --git a/include/configs/mx6q_sabreauto.h b/include/configs/mx6q_sabreauto.h
index e304b5a..0a5f291 100644
--- a/include/configs/mx6q_sabreauto.h
+++ b/include/configs/mx6q_sabreauto.h
@@ -1,7 +1,7 @@
 /*
  * Copyright (C) 2010-2012 Freescale Semiconductor, Inc.
  *
- * Configuration settings for the MX6Q Armadillo2 Freescale board.
+ * Configuration settings for the MX6Q SABRE-AI Freescale board.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -30,7 +30,6 @@
 #define CONFIG_MX6Q
 #define CONFIG_MX6Q_SABREAUTO
 #define CONFIG_FLASH_HEADER
-#define CONFIG_FLASH_HEADER_OFFSET 0x400
 #define CONFIG_MX6_CLK32	   32768
 
 #define CONFIG_SKIP_RELOCATE_UBOOT
@@ -91,6 +90,7 @@
 #define CONFIG_CMD_SPI
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_IMXOTP
+/*#define CONFIG_CMD_WEIMNOR*/ 	/*To boot from WEIM NOR. This will disable SPI NOR BOOT */
 
 /* Enable below configure when supporting nand */
 #define CONFIG_CMD_SF
@@ -194,8 +194,11 @@
 	#define CONFIG_SYS_I2C_SLAVE            0x30
 #endif
 
+
+
 /*
  * SPI Configs
+ * SPI NOR AND WEIM NOR share PINs, so cannot be enabled both at sametime
  */
 #ifdef CONFIG_CMD_SF
 	#define CONFIG_FSL_SF		1
@@ -206,6 +209,26 @@
 	#define MAX_SPI_BYTES		(64 * 4)
 #endif
 
+/*
+ * WEIM NOR Config
+ */
+#ifdef CONFIG_CMD_WEIMNOR
+	#define CONFIG_SYS_FLASH_CFI			/* use the Common Flash Interface */
+	#define CONFIG_FLASH_CFI_DRIVER			/* use the CFI driver */
+	#define CONFIG_SYS_FLASH_BASE		0x08000000	/* start of FLASH   */
+	#define CONFIG_SYS_FLASH_SIZE		0x08000000	/* max flash size in bytes */
+	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+	#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+	#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
+	#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+	#define CONFIG_SYS_MAX_FLASH_SECT	256		/* max sectors per device */
+	#define CONFIG_SYS_FLASH_PROTECTION
+	#define CONFIG_FLASH_HEADER_OFFSET 0x1000
+#else
+	#define CONFIG_FLASH_HEADER_OFFSET 0x400
+#endif
+
+
 /* Regulator Configs */
 #ifdef CONFIG_CMD_REGUL
 	#define CONFIG_ANATOP_REGULATOR
@@ -294,8 +317,9 @@
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CONFIG_SYS_NO_FLASH
-
+#ifndef CONFIG_CMD_WEIMNOR
+	#define CONFIG_SYS_NO_FLASH
+#endif
 /* Monitor at beginning of flash */
 #define CONFIG_FSL_ENV_IN_MMC
 /* #define CONFIG_FSL_ENV_IN_NAND */
diff --git a/include/configs/mx6solo_sabreauto.h b/include/configs/mx6solo_sabreauto.h
index 999fb2a..eadb69e 100644
--- a/include/configs/mx6solo_sabreauto.h
+++ b/include/configs/mx6solo_sabreauto.h
@@ -32,7 +32,6 @@
 #define CONFIG_DDR_32BIT
 #define CONFIG_MX6Q_SABREAUTO
 #define CONFIG_FLASH_HEADER
-#define CONFIG_FLASH_HEADER_OFFSET 0x400
 #define CONFIG_MX6_CLK32	   32768
 
 #define CONFIG_SKIP_RELOCATE_UBOOT
@@ -93,6 +92,7 @@
 #define CONFIG_CMD_SPI
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_IMXOTP
+#define CONFIG_CMD_WEIMNOR 	/*To boot from WEIM NOR. This will disable SPI NOR BOOT */
 
 /* Enable below configure when supporting nand */
 #define CONFIG_CMD_SF
@@ -197,6 +197,7 @@
 
 /*
  * SPI Configs
+ * SPI NOR AND WEIM NOR share PINs, so cannot be enabled both at sametime
  */
 #ifdef CONFIG_CMD_SF
 	#define CONFIG_FSL_SF		1
@@ -207,6 +208,25 @@
 	#define MAX_SPI_BYTES		(64 * 4)
 #endif
 
+/*
+ * WEIM NOR Config
+ */
+#ifdef CONFIG_CMD_WEIMNOR
+	#define CONFIG_SYS_FLASH_CFI			/* use the Common Flash Interface */
+	#define CONFIG_FLASH_CFI_DRIVER			/* use the CFI driver */
+	#define CONFIG_SYS_FLASH_BASE		0x08000000	/* start of FLASH   */
+	#define CONFIG_SYS_FLASH_SIZE		0x08000000	/* max flash size in bytes */
+	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+	#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+	#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
+	#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+	#define CONFIG_SYS_MAX_FLASH_SECT	256		/* max sectors per device */
+	#define CONFIG_SYS_FLASH_PROTECTION
+	#define CONFIG_FLASH_HEADER_OFFSET 0x1000
+#else
+	#define CONFIG_FLASH_HEADER_OFFSET 0x400
+#endif
+
 /* Regulator Configs */
 #ifdef CONFIG_CMD_REGUL
 	#define CONFIG_ANATOP_REGULATOR
@@ -283,8 +303,9 @@
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CONFIG_SYS_NO_FLASH
-
+#ifndef CONFIG_CMD_WEIMNOR
+	#define CONFIG_SYS_NO_FLASH
+#endif
 /* Monitor at beginning of flash */
 #define CONFIG_FSL_ENV_IN_MMC
 /* #define CONFIG_FSL_ENV_IN_NAND */