Merge branch 'master' of http://www.denx.de/git/u-boot

7 files changed, 483 insertions, 37 deletions

diff --git a/include/common.h b/include/common.h
index 0cd0d4c..6a74442 100644
--- a/include/common.h
+++ b/include/common.h
@@ -114,7 +114,7 @@ typedef volatile unsigned char	vu_char;
 #endif	/* DEBUG */
 
 #define BUG() do { \
-        printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \
+	printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \
 	panic("BUG!"); \
 } while (0)
 #define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0)
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index e0de5c1..897d1b2 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -285,7 +285,7 @@
  */
 #define CFG_IPBSPEED_133		/* define for 133MHz speed */
 
-#if defined(CFG_IPBSPEED_133)
+#if defined(CFG_IPBSPEED_133) && !defined(CONFIG_CAM5200)
 /*
  * PCI Bus clocking configuration
  *
@@ -349,13 +349,29 @@
  */
 #define CFG_FLASH_BASE		0xFC000000
 
+#ifndef CONFIG_CAM5200
 /* use CFI flash driver */
 #define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CFG_FLASH_CFI_DRIVER	1	/* Use the common driver */
 #define CFG_FLASH_BANKS_LIST	{ CFG_BOOTCS_START }
+#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
+					   (= chip selects) */
+#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+#else /* CONFIG_CAM5200 */
+#define CFG_MAX_FLASH_BANKS	2	/* max num of flash banks
+					   (= chip selects) */
+#define CFG_FLASH_WORD_SIZE	unsigned int /* main flash device with */
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_ADDR0		0x555
+#define CFG_FLASH_ADDR1		0x2AA
+#define CFG_FLASH_2ND_16BIT_DEV	1	/* NIOS flash is a 16bit device */
+#define CFG_MAX_FLASH_SECT	128
+#endif /* ifndef CONFIG_CAM5200 */
+
 #define CFG_FLASH_EMPTY_INFO
 #define CFG_FLASH_SIZE		0x04000000 /* 64 MByte */
-#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
 #define CFG_FLASH_USE_BUFFER_WRITE	1
 
 #if defined (CONFIG_CAM5200)
@@ -366,9 +382,6 @@
 # define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00060000)
 #endif
 
-#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
-					   (= chip selects) */
-
 /* Dynamic MTD partition support */
 #define CONFIG_JFFS2_CMDLINE
 #define MTDIDS_DEFAULT		"nor0=TQM5200-0"
@@ -401,10 +414,8 @@
 #elif defined (CONFIG_CAM5200)
 #   define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:768k(firmware),"	\
 						"1792k(kernel),"	\
-						"3584k(small-fs),"	\
-						"2m(initrd),"		\
-						"8m(misc),"		\
-						"16m(big-fs)"
+						"5632k(rootfs),"	\
+						"24m(home)"
 #elif defined (CONFIG_FO300)
 #   define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:640k(firmware),"	\
 						"1408k(kernel),"	\
@@ -479,31 +490,43 @@
 /*
  * GPIO configuration
  *
- * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
- *	Bit 0 (mask: 0x80000000): 1
+ * use CS1: Bit 0 (mask: 0x80000000):
+ *	   1 -> Pin gpio_wkup_6 as second SDRAM chip select (mem_cs1).
  * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
- *	00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
- *	01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
- *	      Use for REV200 STK52XX boards and FO300 boards. Do not use
- *	      with REV100 modules (because, there I2C1 is used as I2C bus)
- * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
- * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
- *	000 -> All PSC2 pins are GIOPs
- *	001 -> CAN1/2 on PSC2 pins
- *	       Use for REV100 STK52xx boards
- *	01x -> Use AC97
- * use PSC3: Bits 20-23 (mask: 0x00000f00)
- *	1100 -> UART/SPI (on FO300 board)
- * use PSC6:
- *   on STK52xx and FO300:
- *	use as UART. Pins PSC6_0 to PSC6_3 are used.
- *	Bits 9:11 (mask: 0x00700000):
- *	   101 -> PSC6 : Extended POST test is not available
- *   on MINI-FAP and TQM5200_IB:
- *	use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
- *	   000 -> PSC6 could not be used as UART, CODEC or IrDA
- *   GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
- *   tests.
+ *	  00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
+ *		SPI on PSC3 according to PSC3 setting. Use for CAM5200.
+ *	  01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
+ *		Use for REV200 STK52XX boards and FO300 boards. Do not use
+ *		with REV100 modules (because, there I2C1 is used as I2C bus).
+ * use ATA: Bits 6-7 (mask 0x03000000):
+ *	  00 -> No ATA chip selects, csb_4/5 used as normal chip selects.
+ *		Use for CAM5200 board.
+ *	  01 -> ATA cs0/1 on csb_4/5. Use for the remaining boards.
+ * use PSC6: Bits 9-11 (mask 0x00700000):
+ *	 000 -> use PSC6_0 to PSC6_3 as GPIO, PSC6 could not be used as
+ *		UART, CODEC or IrDA.
+ *		GPIO on PSC6_3 is used in post_hotkeys_pressed() to
+ *		enable extended POST tests.
+ *		Use for MINI-FAP and TQM5200_IB boards.
+ *	 101 -> use PSC6 as UART. Pins PSC6_0 to PSC6_3 are used.
+ *		Extended POST test is not available.
+ *		Use for STK52xx, FO300 and CAM5200 boards.
+ * use PCI_DIS: Bit 16 (mask 0x00008000):
+ *	   1 -> disable PCI controller (on CAM5200 board).
+ * use USB: Bits 18-19 (mask 0x00003000):
+ *	  10 -> two UARTs (on FO300 and CAM5200).
+ * use PSC3: Bits 20-23 (mask: 0x00000f00):
+ *	0000 -> All PSC3 pins are GPIOs.
+ *	1100 -> UART/SPI (on FO300 board).
+ *	0100 -> UART (on CAM5200 board).
+ * use PSC2: Bits 25:27 (mask: 0x00000030):
+ *	 000 -> All PSC2 pins are GPIOs.
+ *	 100 -> UART (on CAM5200 board).
+ *	 001 -> CAN1/2 on PSC2 pins.
+ *	        Use for REV100 STK52xx boards
+ *	 01x -> Use AC97 (on FO300 board).
+ * use PSC1: Bits 29-31 (mask: 0x00000007):
+ *	 100 -> UART (on all boards).
  */
 #if defined (CONFIG_MINIFAP)
 # define CFG_GPS_PORT_CONFIG	0x91000004
@@ -519,6 +542,8 @@
 # endif
 #elif defined (CONFIG_FO300)
 # define CFG_GPS_PORT_CONFIG	0x91502c24
+#elif defined (CONFIG_CAM5200)
+# define CFG_GPS_PORT_CONFIG	0x8050A444
 #else  /* TMQ5200 Inbetriebnahme-Board */
 # define CFG_GPS_PORT_CONFIG	0x81000004
 #endif
@@ -613,6 +638,16 @@
 #define CFG_CS_BURST		0x00000000
 #define CFG_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for flash and SM501 */
 
+#if defined(CONFIG_CAM5200)
+#define CFG_CS4_START		0xB0000000
+#define CFG_CS4_SIZE		0x00010000
+#define CFG_CS4_CFG		0x01019C10
+
+#define CFG_CS5_START		0xD0000000
+#define CFG_CS5_SIZE		0x01208000
+#define CFG_CS5_CFG		0x1414BF10
+#endif
+
 #define CFG_RESET_ADDRESS	0xff000000
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h
new file mode 100644
index 0000000..5d7bed6
--- /dev/null
+++ b/include/configs/ep82xxm.h
@@ -0,0 +1,395 @@
+/*
+ * Copyright (C) 2006 Embedded Planet, LLC.
+ *
+ * U-Boot configuration for Embedded Planet EP82xxM boards.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MPC8260
+#define CPU_ID_STR		"MPC8270"
+
+#define CONFIG_EP82XXM	/* Embedded Planet EP82xxM H 1.0 board /*
+			/* 256MB SDRAM / 64MB FLASH */
+
+#undef DEBUG
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f */
+
+/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Select serial console configuration
+ *
+ * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ */
+#define	CONFIG_CONS_ON_SMC		/* Console is on SMC         */
+#undef  CONFIG_CONS_ON_SCC		/* It's not on SCC           */
+#undef	CONFIG_CONS_NONE		/* It's not on external UART */
+#define CONFIG_CONS_INDEX	1	/* SMC1 is used for console  */
+
+#define CFG_BCSR		0xFA000000
+
+/*
+ * Select ethernet configuration
+ *
+ * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
+ * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
+ * SCC, 1-3 for FCC)
+ *
+ * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
+ * must be defined elsewhere (as for the console), or CFG_CMD_NET must
+ * be removed from CONFIG_COMMANDS to remove support for networking.
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* Ethernet is not on SCC */
+#define CONFIG_ETHER_ON_FCC		/* Ethernet is on FCC     */
+#undef	CONFIG_ETHER_NONE		/* No external Ethernet   */
+
+#define CONFIG_NET_MULTI
+
+#define CONFIG_ETHER_ON_FCC2
+#define CONFIG_ETHER_ON_FCC3
+
+#define CFG_CMXFCR_MASK3	(CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
+#define CFG_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK16)
+#define CFG_CMXFCR_MASK2	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+#define CFG_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+
+#define CFG_CPMFCR_RAMTYPE	0
+#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#define CONFIG_MII			/* MII PHY management        */
+#define CONFIG_BITBANGMII		/* Bit-banged MDIO interface */
+
+/*
+ * GPIO pins used for bit-banged MII communications
+ */
+#define MDIO_PORT		0	/* Not used - implemented in BCSR */
+#define MDIO_ACTIVE		(*(vu_char *)(CFG_BCSR + 8) &= 0xFB)
+#define MDIO_TRISTATE		(*(vu_char *)(CFG_BCSR + 8) |= 0x04)
+#define MDIO_READ		(*(vu_char *)(CFG_BCSR + 8) & 1)
+
+#define MDIO(bit)		if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x01; \
+				else	*(vu_char *)(CFG_BCSR + 8) &= 0xFE
+
+#define MDC(bit)		if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x02; \
+				else	*(vu_char *)(CFG_BCSR + 8) &= 0xFD
+
+#define MIIDELAY		udelay(1)
+
+
+#ifndef CONFIG_8260_CLKIN
+#define CONFIG_8260_CLKIN	66000000 /* in Hz */
+#endif
+
+#define CONFIG_BAUDRATE		115200
+
+#define CFG_VXWORKS_MAC_PTR 0x4300 /* Pass Ethernet MAC to VxWorks */
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL   \
+				| CFG_CMD_DHCP    \
+				| CFG_CMD_ECHO    \
+				| CFG_CMD_I2C     \
+				| CFG_CMD_IMMAP   \
+				| CFG_CMD_MII     \
+				| CFG_CMD_PING    \
+				| CFG_CMD_DATE    \
+				| CFG_CMD_DTT	  \
+				| CFG_CMD_EEPROM  \
+				| CFG_CMD_PCI	  \
+				| CFG_CMD_DIAG	  \
+				)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_ETHADDR		00:10:EC:00:88:65
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR		00:10:EC:80:88:65
+#define CONFIG_IPADDR		10.0.0.245
+#define CONFIG_HOSTNAME		EP82xxM
+#define CONFIG_SERVERIP		10.0.0.26
+#define CONFIG_GATEWAYIP	10.0.0.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+#define CFG_ENV_IN_OWN_SECT	1
+#define CFG_AUTO_COMPLETE
+#define	CONFIG_EXTRA_ENV_SETTINGS	"ethprime=FCC3 ETHERNET"
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
+#define CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
+#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
+#define CONFIG_KGDB_INDEX	1	/* which serial channel for kgdb */
+#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
+#endif
+
+#define CONFIG_BZIP2	/* include support for bzip2 compressed images */
+#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#define CFG_LONGHELP			/* undef to save memory	    */
+#define CFG_PROMPT		"ep82xxm=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size  */
+#define CFG_MAXARGS		16		/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size  */
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+/*
+ * Define here the location of the environment variables (FLASH or EEPROM).
+ * Note: DENX encourages to use redundant environment in FLASH.
+ */
+#if 1
+#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+#else
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_BASE		0xFC000000
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks	*/
+#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector in flinfo */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x20000
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+/* EEPROM Configuration */
+#define CFG_EEPROM_SIZE	0x1000
+#define CFG_I2C_EEPROM_ADDR	0x54
+#define CFG_I2C_EEPROM_ADDR_LEN	1
+#define CFG_EEPROM_PAGE_WRITE_BITS	3
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_SIZE		0x200	    /* Size of Environment vars */
+#define CFG_ENV_OFFSET		0x0
+#endif /* CFG_ENV_IS_IN_EEPROM */
+
+/* RTC Configuration */
+#define CONFIG_RTC_M41T11	1 	/* uses a M41T81 */
+#define CFG_I2C_RTC_ADDR	0x68
+#define CONFIG_M41T11_BASE_YEAR	1900
+
+/* I2C SYSMON (LM75) */
+#define CONFIG_DTT_LM75		1
+#define CONFIG_DTT_SENSORS	{0}
+#define CFG_DTT_MAX_TEMP	70
+#define CFG_DTT_LOW_TEMP	-30
+#define	CFG_DTT_HYSTERESIS	3
+
+/*-----------------------------------------------------------------------
+ * NVRAM Configuration
+ *-----------------------------------------------------------------------
+ */
+#define CFG_NVRAM_BASE_ADDR	0xFA080000
+#define CFG_NVRAM_SIZE		(128*1024)-16
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play   */
+#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
+#define CONFIG_PCI_BOOTDELAY	0
+
+/* PCI Memory map (if different from default map */
+#define CFG_PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE		/* Local base */
+#define CFG_PCI_SLV_MEM_BUS		0x00000000	/* PCI base */
+#define CFG_PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
+				 PICMR_PREFETCH_EN)
+
+/*
+ * These are the windows that allow the CPU to access PCI address space.
+ * All three PCI master windows, which allow the CPU to access PCI
+ * prefetch, non prefetch, and IO space (see below), must all fit within
+ * these windows.
+ */
+
+/*
+ * Master window that allows the CPU to access PCI Memory (prefetch).
+ * This window will be setup with the second set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CFG_PCI_MSTR_MEM_LOCAL	0x80000000          /* Local base */
+#define CFG_PCI_MSTR_MEM_BUS	0x80000000          /* PCI base   */
+#define	CFG_CPU_PCI_MEM_START	PCI_MSTR_MEM_LOCAL
+#define CFG_PCI_MSTR_MEM_SIZE	0x20000000          /* 512MB */
+#define CFG_POCMR0_MASK_ATTRIB	(POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
+
+/*
+ * Master window that allows the CPU to access PCI Memory (non-prefetch).
+ * This window will be setup with the second set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CFG_PCI_MSTR_MEMIO_LOCAL    0xA0000000          /* Local base */
+#define CFG_PCI_MSTR_MEMIO_BUS      0xA0000000          /* PCI base   */
+#define CFG_CPU_PCI_MEMIO_START     PCI_MSTR_MEMIO_LOCAL
+#define CFG_PCI_MSTR_MEMIO_SIZE     0x20000000          /* 512MB */
+#define CFG_POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
+
+/*
+ * Master window that allows the CPU to access PCI IO space.
+ * This window will be setup with the first set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CFG_PCI_MSTR_IO_LOCAL       0xF6000000          /* Local base */
+#define CFG_PCI_MSTR_IO_BUS         0x00000000          /* PCI base   */
+#define CFG_CPU_PCI_IO_START        PCI_MSTR_IO_LOCAL
+#define CFG_PCI_MSTR_IO_SIZE        0x02000000          /* 64MB */
+#define CFG_POCMR2_MASK_ATTRIB      (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
+
+
+/* PCIBR0 - for PCI IO*/
+#define CFG_PCI_MSTR0_LOCAL		CFG_PCI_MSTR_IO_LOCAL		/* Local base */
+#define CFG_PCIMSK0_MASK		~(CFG_PCI_MSTR_IO_SIZE - 1U)	/* Size of window */
+/* PCIBR1 - prefetch and non-prefetch regions joined together */
+#define CFG_PCI_MSTR1_LOCAL		CFG_PCI_MSTR_MEM_LOCAL
+#define CFG_PCIMSK1_MASK		~(CFG_PCI_MSTR_MEM_SIZE + CFG_PCI_MSTR_MEMIO_SIZE - 1U)
+
+
+#define	CFG_DIRECT_FLASH_TFTP
+
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+#define CFG_JFFS2_FIRST_BANK	0
+#define CFG_JFFS2_NUM_BANKS	CFG_MAX_FLASH_BANKS
+#define CFG_JFFS2_FIRST_SECTOR  0
+#define CFG_JFFS2_LAST_SECTOR   62
+#define CFG_JFFS2_SORT_FRAGMENTS
+#define CFG_JFFS_CUSTOM_PART
+#endif /* CFG_CMD_JFFS2 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+#define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
+#define CFG_I2C_SPEED		100000	/* I2C speed			*/
+#define CFG_I2C_SLAVE		0x7F	/* I2C slave address		*/
+#endif /* CFG_CMD_I2C */
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#endif
+
+#define CFG_MONITOR_LEN		(512 << 10)	/* Reserve 256KB for Monitor */
+
+#define CFG_DEFAULT_IMMR	0x00010000
+#define CFG_IMMR		0xF0000000
+
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+
+/* Hard reset configuration word */
+#define CFG_HRCW_MASTER		0 /*0x1C800641*/  /* Not used - provided by CPLD */
+/* No slaves */
+#define CFG_HRCW_SLAVE1 	0
+#define CFG_HRCW_SLAVE2 	0
+#define CFG_HRCW_SLAVE3 	0
+#define CFG_HRCW_SLAVE4 	0
+#define CFG_HRCW_SLAVE5 	0
+#define CFG_HRCW_SLAVE6 	0
+#define CFG_HRCW_SLAVE7 	0
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02	/* Software reboot                  */
+
+#define CFG_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+#define CFG_HID0_INIT		0
+#define CFG_HID0_FINAL		0
+
+#define CFG_HID2		0
+
+#define CFG_SIUMCR		0x02610000
+#define CFG_SYPCR		0xFFFF0689
+#define CFG_BCR			0x8080E000
+#define CFG_SCCR		0x00000001
+
+#define CFG_RMR			0
+#define CFG_TMCNTSC		0x000000C3
+#define CFG_PISCR		0x00000083
+#define CFG_RCCR		0
+
+#define CFG_MPTPR		0x0A00
+#define CFG_PSDMR		0xC432246E
+#define CFG_PSRT		0x32
+
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_SDRAM_BR		(CFG_SDRAM_BASE | 0x00000041)
+#define CFG_SDRAM_OR		0xF0002900
+
+#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | 0x00001801)
+#define CFG_OR0_PRELIM		0xFC000882
+#define CFG_BR4_PRELIM		(CFG_BCSR | 0x00001001)
+#define CFG_OR4_PRELIM		0xFFF00050
+
+#define CFG_RESET_ADDRESS	0xFFF00100
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 639765d..f67fd91 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -31,8 +31,13 @@
 /*-----------------------------------------------------------------------
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
+/* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */
+#ifndef CONFIG_RAINIER
 #define CONFIG_SEQUOIA		1		/* Board is Sequoia	*/
 #define CONFIG_440EPX		1		/* Specific PPC440EPx	*/
+#else
+#define CONFIG_440GRX		1		/* Specific PPC440GRx	*/
+#endif
 #define CONFIG_4xx		1		/* ... PPC4xx family	*/
 #define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/
 
@@ -272,12 +277,18 @@
 #define CONFIG_PHY1_ADDR	1
 
 /* USB */
+#ifdef CONFIG_440EPX
 #define CONFIG_USB_OHCI
 #define CONFIG_USB_STORAGE
 
 /* Comment this out to enable USB 1.1 device */
 #define USB_2_0_DEVICE
 
+#define CMD_USB			CFG_CMD_USB
+#else
+#define CMD_USB			0	/* no USB on 440GRx		*/
+#endif /* CONFIG_440EPX */
+
 /* Partitions */
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -301,7 +312,7 @@
 			       CFG_CMD_PING	|	\
 			       CFG_CMD_REGINFO	|	\
 			       CFG_CMD_SDRAM	|	\
-			       CFG_CMD_USB    )
+			       CMD_USB)
 
 #define CONFIG_SUPPORT_VFAT
 
diff --git a/include/flash.h b/include/flash.h
index 84b48a9..d91589a 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -209,6 +209,9 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
 #define AMD_ID_GL064M_3 0x22012201	/* 3rd ID word for S29GL064M-R6 */
 #define AMD_ID_GL064MT_2 0x22102210	/* 2nd ID word for S29GL064M-R3 (top boot sector) */
 #define AMD_ID_GL064MT_3 0x22012201	/* 3rd ID word for S29GL064M-R3 (top boot sector) */
+#define AMD_ID_GL128N_2	0x22212221	/* 2nd ID word for S29GL128N */
+#define AMD_ID_GL128N_3	0x22012201	/* 3rd ID word for S29GL128N */
+
 
 #define AMD_ID_LV320B_2 0x221A221A	/* 2d ID word for AM29LV320MB at 0x38 */
 #define AMD_ID_LV320B_3 0x22002200	/* 3d ID word for AM29LV320MB at 0x3c */
@@ -417,6 +420,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
 #define FLASH_FUJLV650	0x00D0		/* Fujitsu MBM 29LV650UE/651UE		*/
 #define FLASH_MT28S4M16LC 0x00E1	/* Micron MT28S4M16LC			*/
 #define FLASH_S29GL064M 0x00F0		/* Spansion S29GL064M-R6		*/
+#define FLASH_S29GL128N 0x00F1		/* Spansion S29GL128N			*/
 
 #define FLASH_UNKNOWN	0xFFFF		/* unknown flash type			*/
 
diff --git a/include/image.h b/include/image.h
index ea7e953..2f575fd 100644
--- a/include/image.h
+++ b/include/image.h
@@ -76,6 +76,7 @@
 #define IH_CPU_MICROBLAZE	14	/* MicroBlaze   */
 #define IH_CPU_NIOS2		15	/* Nios-II	*/
 #define IH_CPU_BLACKFIN		16	/* Blackfin	*/
+#define IH_CPU_AVR32		17	/* AVR32	*/
 
 /*
  * Image Types
diff --git a/include/ppc440.h b/include/ppc440.h
index c4a3ed5..e407320 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -1570,8 +1570,8 @@
 #define malrxctp0r  (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg   */
 #define malrxctp1r  (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg   */
 #if defined(CONFIG_440GX)
-#define malrxctp2r  (MAL_DCR_BASE+0x42) /* RX 0 Channel table pointer reg   */
-#define malrxctp3r  (MAL_DCR_BASE+0x43) /* RX 1 Channel table pointer reg   */
+#define malrxctp2r  (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg   */
+#define malrxctp3r  (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg   */
 #endif /* CONFIG_440GX */
 #define malrcbs0    (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg	    */
 #define malrcbs1    (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg	    */