at91sam9/at91cap: improve clock framework

calculate dynamically the clock rate and pllb setting for usb

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

10 files changed, 50 insertions, 40 deletions

diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h
index b57875d..07580da 100644
--- a/include/asm-arm/arch-at91/at91_pmc.h
+++ b/include/asm-arm/arch-at91/at91_pmc.h
@@ -1,5 +1,5 @@
 /*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91_pmc.h]
+ * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_pmc.h]
  *
  * Copyright (C) 2005 Ivan Kokshaysky
  * Copyright (C) SAN People
@@ -23,6 +23,7 @@
 #define		AT91_PMC_PCK		(1 <<  0)		/* Processor Clock */
 #define		AT91RM9200_PMC_UDP	(1 <<  1)		/* USB Devcice Port Clock [AT91RM9200 only] */
 #define		AT91RM9200_PMC_MCKUDP	(1 <<  2)		/* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
+#define		AT91CAP9_PMC_DDR	(1 <<  2)		/* DDR Clock [AT91CAP9 revC only] */
 #define		AT91RM9200_PMC_UHP	(1 <<  4)		/* USB Host Port Clock [AT91RM9200 only] */
 #define		AT91SAM926x_PMC_UHP	(1 <<  6)		/* USB Host Port Clock [AT91SAM926x only] */
 #define		AT91CAP9_PMC_UHP	(1 <<  6)		/* USB Host Port Clock [AT91CAP9 only] */
@@ -39,10 +40,14 @@
 #define	AT91_PMC_PCSR		(AT91_PMC + 0x18)	/* Peripheral Clock Status Register */
 
 #define	AT91_CKGR_UCKR		(AT91_PMC + 0x1C)	/* UTMI Clock Register [SAM9RL, CAP9] */
+#define		AT91_PMC_UPLLEN		(1   << 16)		/* UTMI PLL Enable */
+#define		AT91_PMC_UPLLCOUNT	(0xf << 20)		/* UTMI PLL Start-up Time */
+#define		AT91_PMC_BIASEN		(1   << 24)		/* UTMI BIAS Enable */
+#define		AT91_PMC_BIASCOUNT	(0xf << 28)		/* UTMI PLL Start-up Time */
 
 #define	AT91_CKGR_MOR		(AT91_PMC + 0x20)	/* Main Oscillator Register [not on SAM9RL] */
 #define		AT91_PMC_MOSCEN		(1    << 0)		/* Main Oscillator Enable */
-#define		AT91_PMC_OSCBYPASS	(1    << 1)		/* Oscillator Bypass [AT91SAM926x only] */
+#define		AT91_PMC_OSCBYPASS	(1    << 1)		/* Oscillator Bypass [SAM9x, CAP9] */
 #define		AT91_PMC_OSCOUNT	(0xff << 8)		/* Main Oscillator Start-up Time */
 
 #define	AT91_CKGR_MCFR		(AT91_PMC + 0x24)	/* Main Clock Frequency Register */
@@ -76,10 +81,17 @@
 #define			AT91_PMC_PRES_32		(5 << 2)
 #define			AT91_PMC_PRES_64		(6 << 2)
 #define		AT91_PMC_MDIV		(3 <<  8)		/* Master Clock Division */
-#define			AT91_PMC_MDIV_1			(0 << 8)
-#define			AT91_PMC_MDIV_2			(1 << 8)
-#define			AT91_PMC_MDIV_3			(2 << 8)
-#define			AT91_PMC_MDIV_4			(3 << 8)
+#define			AT91RM9200_PMC_MDIV_1		(0 << 8)	/* [AT91RM9200 only] */
+#define			AT91RM9200_PMC_MDIV_2		(1 << 8)
+#define			AT91RM9200_PMC_MDIV_3		(2 << 8)
+#define			AT91RM9200_PMC_MDIV_4		(3 << 8)
+#define			AT91SAM9_PMC_MDIV_1		(0 << 8)	/* [SAM9,CAP9 only] */
+#define			AT91SAM9_PMC_MDIV_2		(1 << 8)
+#define			AT91SAM9_PMC_MDIV_4		(2 << 8)
+#define			AT91SAM9_PMC_MDIV_6		(3 << 8)
+#define		AT91_PMC_PDIV		(1 << 12)		/* Processor Clock Division [some SAM9 only] */
+#define			AT91_PMC_PDIV_1			(0 << 12)
+#define			AT91_PMC_PDIV_2			(1 << 12)
 
 #define	AT91_PMC_PCKR(n)	(AT91_PMC + 0x40 + ((n) * 4))	/* Programmable Clock 0-3 Registers */
 
@@ -90,6 +102,8 @@
 #define		AT91_PMC_LOCKA		(1 <<  1)		/* PLLA Lock */
 #define		AT91_PMC_LOCKB		(1 <<  2)		/* PLLB Lock */
 #define		AT91_PMC_MCKRDY		(1 <<  3)		/* Master Clock */
+#define		AT91_PMC_LOCKU		(1 <<  6)		/* UPLL Lock [AT91CAP9 only] */
+#define		AT91_PMC_OSCSEL		(1 <<  7)		/* Slow Clock Oscillator [AT91CAP9 revC only] */
 #define		AT91_PMC_PCK0RDY	(1 <<  8)		/* Programmable Clock 0 */
 #define		AT91_PMC_PCK1RDY	(1 <<  9)		/* Programmable Clock 1 */
 #define		AT91_PMC_PCK2RDY	(1 << 10)		/* Programmable Clock 2 */
@@ -97,8 +111,8 @@
 #define	AT91_PMC_IMR		(AT91_PMC + 0x6c)	/* Interrupt Mask Register */
 
 #define AT91_PMC_PROT		(AT91_PMC + 0xe4)	/* Protect Register [AT91CAP9 revC only] */
-#define		AT91_PMC_PROTKEY	0x504d4301		/* Activation Code */
+#define		AT91_PMC_PROTKEY	0x504d4301	/* Activation Code */
 
-#define AT91_PMC_VER	(AT91_PMC + 0xfc)	/* PMC Module Version [AT91CAP9 only] */
+#define AT91_PMC_VER		(AT91_PMC + 0xfc)	/* PMC Module Version [AT91CAP9 only] */
 
 #endif
diff --git a/include/asm-arm/arch-at91/clk.h b/include/asm-arm/arch-at91/clk.h
index 1b502c8..6aaf82e 100644
--- a/include/asm-arm/arch-at91/clk.h
+++ b/include/asm-arm/arch-at91/clk.h
@@ -2,6 +2,7 @@
  * (C) Copyright 2007
  * Stelian Pop <stelian.pop@leadtechdesign.com>
  * Lead Tech Design <www.leadtechdesign.com>
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -26,20 +27,32 @@
 
 #include <asm/arch/hardware.h>
 
+unsigned long get_cpu_clk_rate(void);
+unsigned long get_main_clk_rate(void);
+unsigned long get_mck_clk_rate(void);
+unsigned long get_plla_clk_rate(void);
+unsigned long get_pllb_clk_rate(void);
+unsigned int  get_pllb_init(void);
+
 static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
 {
-	return AT91_MASTER_CLOCK;
+	return get_mck_clk_rate();
 }
 
 static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
 {
-	return AT91_MASTER_CLOCK;
+	return get_mck_clk_rate();
 }
 
 static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id)
 {
-	return AT91_MASTER_CLOCK;
+	return get_mck_clk_rate();
 }
 
+static inline unsigned long get_twi_clk_rate(unsigned int dev_id)
+{
+	return get_mck_clk_rate();
+}
 
+int at91_clock_init(unsigned long main_clock);
 #endif /* __ASM_ARM_ARCH_CLK_H__ */
diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h
index 4f0e1a7..6b46a36 100644
--- a/include/asm-arm/arch-at91/hardware.h
+++ b/include/asm-arm/arch-at91/hardware.h
@@ -48,4 +48,7 @@
 #error "Unsupported AT91 processor"
 #endif
 
+/* Clocks */
+#define AT91_SLOW_CLOCK		32768		/* slow clock */
+
 #endif
diff --git a/include/asm-arm/u-boot-arm.h b/include/asm-arm/u-boot-arm.h
index 4ee5a32..e7d58fe 100644
--- a/include/asm-arm/u-boot-arm.h
+++ b/include/asm-arm/u-boot-arm.h
@@ -40,6 +40,9 @@ extern ulong FIQ_STACK_START;	/* top of FIQ stack */
 int	cpu_init(void);
 int	cleanup_before_linux(void);
 
+/* cpu/.../arch/cpu.c */
+int	arch_cpu_init(void);
+
 /* board/.../... */
 int	board_init(void);
 int	dram_init (void);
diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h
index de938f7..d637a94 100644
--- a/include/configs/afeb9260.h
+++ b/include/configs/afeb9260.h
@@ -28,14 +28,11 @@
 
 /* ARM asynchronous clock */
 #define AT91_MAIN_CLOCK		18429952	/* from 18.432 MHz crystal */
-#define AT91_MASTER_CLOCK	89999598	/* peripheral = main / 2 */
-#define CONFIG_SYS_AT91_PLLB	0x107c3e18	/* PLLB settings for USB */
 #define CONFIG_SYS_HZ		1000000		/* 1us resolution */
 
-#define AT91_SLOW_CLOCK		32768	/* slow clock */
-
 #define CONFIG_AT91SAM9260	1	/* It's an Atmel AT91SAM9260 SoC*/
 #define CONFIG_AFEB9260		1	/* on an AFEB9260 Board	*/
+#define CONFIG_ARCH_CPU_INIT
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
 
 #define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h
index b978731..c61af08 100644
--- a/include/configs/at91cap9adk.h
+++ b/include/configs/at91cap9adk.h
@@ -30,16 +30,12 @@
 /* ARM asynchronous clock */
 #define AT91_CPU_NAME		"AT91CAP9"
 #define AT91_MAIN_CLOCK		12000000	/* 12 MHz crystal */
-#define AT91_MASTER_CLOCK	100000000	/* peripheral */
-#define AT91_CPU_CLOCK		200000000	/* cpu */
-#define CONFIG_SYS_AT91_PLLB	0x10073e01	/* PLLB settings for USB */
 #define CONFIG_SYS_HZ		1000000		/* 1us resolution */
 
-#define AT91_SLOW_CLOCK		32768	/* slow clock */
-
 #define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
 #define CONFIG_AT91CAP9		1	/* It's an Atmel AT91CAP9 SoC	*/
 #define CONFIG_AT91CAP9ADK	1	/* on an AT91CAP9ADK Board	*/
+#define CONFIG_ARCH_CPU_INIT
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
 
 #define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index bcc65bd..b6e2edf 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -29,25 +29,19 @@
 
 /* ARM asynchronous clock */
 #define AT91_MAIN_CLOCK		18432000	/* 18.432 MHz crystal */
-#define CONFIG_SYS_AT91_PLLB	0x107c3e18	/* PLLB settings for USB */
 #define CONFIG_SYS_HZ		1000000		/* 1us resolution */
 
-#define AT91_SLOW_CLOCK		32768	/* slow clock */
-
 #define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
 
 #ifdef CONFIG_AT91SAM9G20EK
 #define AT91_CPU_NAME		"AT91SAM9G20"
-#define AT91_MASTER_CLOCK	132000000	/* peripheral */
-#define AT91_CPU_CLOCK		396000000	/* cpu */
 #define CONFIG_AT91SAM9G20	1	/* It's an Atmel AT91SAM9G20 SoC*/
 #else
 #define AT91_CPU_NAME		"AT91SAM9260"
-#define AT91_MASTER_CLOCK	100000000	/* peripheral */
-#define AT91_CPU_CLOCK		200000000	/* cpu */
 #define CONFIG_AT91SAM9260	1	/* It's an Atmel AT91SAM9260 SoC*/
 #endif
 
+#define CONFIG_ARCH_CPU_INIT
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
 
 #define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h
index cc40d7b..7ec171c 100644
--- a/include/configs/at91sam9261ek.h
+++ b/include/configs/at91sam9261ek.h
@@ -30,15 +30,12 @@
 /* ARM asynchronous clock */
 #define AT91_CPU_NAME		"AT91SAM9261"
 #define AT91_MAIN_CLOCK		18432000	/* 18.432 MHz crystal */
-#define AT91_MASTER_CLOCK	100000000	/* peripheral */
-#define AT91_CPU_CLOCK		200000000	/* cpu */
 #define CONFIG_SYS_HZ		1000000		/* 1us resolution */
 
-#define AT91_SLOW_CLOCK		32768	/* slow clock */
-
 #define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
 #define CONFIG_AT91SAM9261	1	/* It's an Atmel AT91SAM9261 SoC*/
 #define CONFIG_AT91SAM9261EK	1	/* on an AT91SAM9261EK Board	*/
+#define CONFIG_ARCH_CPU_INIT
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
 
 #define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index ee1531f..34c7521 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -30,16 +30,12 @@
 /* ARM asynchronous clock */
 #define AT91_CPU_NAME		"AT91SAM9263"
 #define AT91_MAIN_CLOCK		16367660	/* 16.367 MHz crystal */
-#define AT91_MASTER_CLOCK	100000000	/* peripheral */
-#define AT91_CPU_CLOCK		200000000	/* cpu */
-#define CONFIG_SYS_AT91_PLLB	0x133a3e8d	/* PLLB settings for USB */
 #define CONFIG_SYS_HZ		1000000		/* 1us resolution */
 
-#define AT91_SLOW_CLOCK		32768	/* slow clock */
-
 #define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
 #define CONFIG_AT91SAM9263	1	/* It's an Atmel AT91SAM9263 SoC*/
 #define CONFIG_AT91SAM9263EK	1	/* on an AT91SAM9263EK Board	*/
+#define CONFIG_ARCH_CPU_INIT
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
 
 #define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index fec48b6..2ccf958 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -30,15 +30,12 @@
 /* ARM asynchronous clock */
 #define AT91_CPU_NAME		"AT91SAM9RL"
 #define AT91_MAIN_CLOCK		12000000	/* 12 MHz crystal */
-#define AT91_MASTER_CLOCK	100000000	/* peripheral */
-#define AT91_CPU_CLOCK		200000000	/* cpu */
 #define CONFIG_SYS_HZ		1000000		/* 1us resolution */
 
-#define AT91_SLOW_CLOCK		32768	/* slow clock */
-
 #define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
 #define CONFIG_AT91SAM9RL	1	/* It's an Atmel AT91SAM9RL SoC*/
 #define CONFIG_AT91SAM9RLEK	1	/* on an AT91SAM9RLEK Board	*/
+#define CONFIG_ARCH_CPU_INIT
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
 
 #define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/