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| author | Stefan Roese <sr@denx.de> | 2008-08-14 08:25:13 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-08-14 08:25:13 +0200 |
| commit | becbbc7b2a1be44d38779c80ce94fb20e5e13f12 (patch) | |
| tree | 38e933b70075e14b21fbb0eb891cc8c59d8e60be /include | |
| parent | bc9019e19758a19a388fb20ef18dc771cd39fdda (diff) | |
| parent | 2fd0aad443c966ce62008225e57b18e2dcf4e330 (diff) | |
| download | u-boot-imx-becbbc7b2a1be44d38779c80ce94fb20e5e13f12.zip u-boot-imx-becbbc7b2a1be44d38779c80ce94fb20e5e13f12.tar.gz u-boot-imx-becbbc7b2a1be44d38779c80ce94fb20e5e13f12.tar.bz2 | |
Merge branch 'master' of /home/stefan/git/u-boot/u-boot into next
Diffstat (limited to 'include')
266 files changed, 3831 insertions, 2806 deletions
diff --git a/include/asm-arm/arch-at91sam9/at91_pio.h b/include/asm-arm/arch-at91/at91_pio.h index f6ce1f9..f6ce1f9 100644 --- a/include/asm-arm/arch-at91sam9/at91_pio.h +++ b/include/asm-arm/arch-at91/at91_pio.h diff --git a/include/asm-arm/arch-at91sam9/at91_pit.h b/include/asm-arm/arch-at91/at91_pit.h index 94dd242..94dd242 100644 --- a/include/asm-arm/arch-at91sam9/at91_pit.h +++ b/include/asm-arm/arch-at91/at91_pit.h diff --git a/include/asm-arm/arch-at91sam9/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h index b57875d..b57875d 100644 --- a/include/asm-arm/arch-at91sam9/at91_pmc.h +++ b/include/asm-arm/arch-at91/at91_pmc.h diff --git a/include/asm-arm/arch-at91sam9/at91_rstc.h b/include/asm-arm/arch-at91/at91_rstc.h index e49caef..e49caef 100644 --- a/include/asm-arm/arch-at91sam9/at91_rstc.h +++ b/include/asm-arm/arch-at91/at91_rstc.h diff --git a/include/asm-arm/arch-at91sam9/at91_spi.h b/include/asm-arm/arch-at91/at91_spi.h index 30643c6..30643c6 100644 --- a/include/asm-arm/arch-at91sam9/at91_spi.h +++ b/include/asm-arm/arch-at91/at91_spi.h diff --git a/include/asm-arm/arch-at91sam9/at91cap9.h b/include/asm-arm/arch-at91/at91cap9.h index 0b52228..0b52228 100644 --- a/include/asm-arm/arch-at91sam9/at91cap9.h +++ b/include/asm-arm/arch-at91/at91cap9.h diff --git a/include/asm-arm/arch-at91sam9/at91cap9_matrix.h b/include/asm-arm/arch-at91/at91cap9_matrix.h index 22b7e9b..22b7e9b 100644 --- a/include/asm-arm/arch-at91sam9/at91cap9_matrix.h +++ b/include/asm-arm/arch-at91/at91cap9_matrix.h diff --git a/include/asm-arm/arch-at91sam9/at91sam9260.h b/include/asm-arm/arch-at91/at91sam9260.h index 920a7f3..920a7f3 100644 --- a/include/asm-arm/arch-at91sam9/at91sam9260.h +++ b/include/asm-arm/arch-at91/at91sam9260.h diff --git a/include/asm-arm/arch-at91sam9/at91sam9260_matrix.h b/include/asm-arm/arch-at91/at91sam9260_matrix.h index f8b023d..f8b023d 100644 --- a/include/asm-arm/arch-at91sam9/at91sam9260_matrix.h +++ b/include/asm-arm/arch-at91/at91sam9260_matrix.h diff --git a/include/asm-arm/arch-at91sam9/at91sam9261.h b/include/asm-arm/arch-at91/at91sam9261.h index 752d81d..752d81d 100644 --- a/include/asm-arm/arch-at91sam9/at91sam9261.h +++ b/include/asm-arm/arch-at91/at91sam9261.h diff --git a/include/asm-arm/arch-at91sam9/at91sam9261_matrix.h b/include/asm-arm/arch-at91/at91sam9261_matrix.h index e2bfc4b..e2bfc4b 100644 --- a/include/asm-arm/arch-at91sam9/at91sam9261_matrix.h +++ b/include/asm-arm/arch-at91/at91sam9261_matrix.h diff --git a/include/asm-arm/arch-at91sam9/at91sam9263.h b/include/asm-arm/arch-at91/at91sam9263.h index 98251cb..98251cb 100644 --- a/include/asm-arm/arch-at91sam9/at91sam9263.h +++ b/include/asm-arm/arch-at91/at91sam9263.h diff --git a/include/asm-arm/arch-at91sam9/at91sam9263_matrix.h b/include/asm-arm/arch-at91/at91sam9263_matrix.h index 83aaaab..83aaaab 100644 --- a/include/asm-arm/arch-at91sam9/at91sam9263_matrix.h +++ b/include/asm-arm/arch-at91/at91sam9263_matrix.h diff --git a/include/asm-arm/arch-at91sam9/at91sam9_smc.h b/include/asm-arm/arch-at91/at91sam9_smc.h index d64511b..d64511b 100644 --- a/include/asm-arm/arch-at91sam9/at91sam9_smc.h +++ b/include/asm-arm/arch-at91/at91sam9_smc.h diff --git a/include/asm-arm/arch-at91sam9/at91sam9rl.h b/include/asm-arm/arch-at91/at91sam9rl.h index 215bbc8..215bbc8 100644 --- a/include/asm-arm/arch-at91sam9/at91sam9rl.h +++ b/include/asm-arm/arch-at91/at91sam9rl.h diff --git a/include/asm-arm/arch-at91sam9/at91sam9rl_matrix.h b/include/asm-arm/arch-at91/at91sam9rl_matrix.h index af8d914..af8d914 100644 --- a/include/asm-arm/arch-at91sam9/at91sam9rl_matrix.h +++ b/include/asm-arm/arch-at91/at91sam9rl_matrix.h diff --git a/include/asm-arm/arch-at91sam9/clk.h b/include/asm-arm/arch-at91/clk.h index 1b502c8..1b502c8 100644 --- a/include/asm-arm/arch-at91sam9/clk.h +++ b/include/asm-arm/arch-at91/clk.h diff --git a/include/asm-arm/arch-at91sam9/gpio.h b/include/asm-arm/arch-at91/gpio.h index c4d7b97..c4d7b97 100644 --- a/include/asm-arm/arch-at91sam9/gpio.h +++ b/include/asm-arm/arch-at91/gpio.h diff --git a/include/asm-arm/arch-at91sam9/hardware.h b/include/asm-arm/arch-at91/hardware.h index f312419..f312419 100644 --- a/include/asm-arm/arch-at91sam9/hardware.h +++ b/include/asm-arm/arch-at91/hardware.h diff --git a/include/asm-arm/arch-at91sam9/io.h b/include/asm-arm/arch-at91/io.h index f09b2df..f09b2df 100644 --- a/include/asm-arm/arch-at91sam9/io.h +++ b/include/asm-arm/arch-at91/io.h diff --git a/include/asm-arm/arch-at91sam9/memory-map.h b/include/asm-arm/arch-at91/memory-map.h index 8015dad..8015dad 100644 --- a/include/asm-arm/arch-at91sam9/memory-map.h +++ b/include/asm-arm/arch-at91/memory-map.h diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h index 02b7dcb..b04a718 100644 --- a/include/asm-arm/arch-mx31/mx31-regs.h +++ b/include/asm-arm/arch-mx31/mx31-regs.h @@ -126,17 +126,32 @@ #define MUX_CTL_CSPI2_SS2 0x87 #define MUX_CTL_CSPI2_MOSI 0x8b -/* The modes a specific pin can be in - * these macros can be used in mx31_gpio_mux() and have the form - * MUX_[contact name]__[pin function] +/* + * Helper macros for the MUX_[contact name]__[pin function] macros */ -#define MUX_RXD1__UART1_RXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_RXD1) -#define MUX_TXD1__UART1_TXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_TXD1) -#define MUX_RTS1__UART1_RTS_B ((MUX_CTL_FUNC << 8) | MUX_CTL_RTS1) -#define MUX_RTS1__UART1_CTS_B ((MUX_CTL_FUNC << 8) | MUX_CTL_CTS1) +#define IOMUX_MODE_POS 9 +#define IOMUX_MODE(contact, mode) (((mode) << IOMUX_MODE_POS) | (contact)) -#define MUX_CSPI2_MOSI__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MOSI) -#define MUX_CSPI2_MISO__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MISO) +/* + * These macros can be used in mx31_gpio_mux() and have the form + * MUX_[contact name]__[pin function] + */ +#define MUX_RXD1__UART1_RXD_MUX IOMUX_MODE(MUX_CTL_RXD1, MUX_CTL_FUNC) +#define MUX_TXD1__UART1_TXD_MUX IOMUX_MODE(MUX_CTL_TXD1, MUX_CTL_FUNC) +#define MUX_RTS1__UART1_RTS_B IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC) +#define MUX_CTS1__UART1_CTS_B IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC) + +#define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC) +#define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC) +#define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC) +#define MUX_CSPI2_MOSI__CSPI2_MOSI IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_FUNC) +#define MUX_CSPI2_MISO__CSPI2_MISO IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_FUNC) +#define MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B \ + IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC) +#define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC) + +#define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1) +#define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1) /* * Memory regions and CS diff --git a/include/asm-ppc/interrupt.h b/include/asm-ppc/interrupt.h new file mode 100644 index 0000000..792836b --- /dev/null +++ b/include/asm-ppc/interrupt.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ +#ifndef INTERRUPT_H +#define INTERRUPT_H + +#if defined(CONFIG_XILINX_440) +#include <asm/xilinx_irq.h> +#else +#include <asm/ppc4xx-uic.h> +#endif + +void pic_enable(void); +void pic_irq_enable(unsigned int irq); +void pic_irq_disable(unsigned int irq); +void pic_irq_ack(unsigned int irq); +void external_interrupt(struct pt_regs *regs); +void interrupt_run_handler(int vec); + +#endif diff --git a/include/asm-ppc/ppc4xx-ebc.h b/include/asm-ppc/ppc4xx-ebc.h new file mode 100644 index 0000000..d180e04 --- /dev/null +++ b/include/asm-ppc/ppc4xx-ebc.h @@ -0,0 +1,156 @@ +/* + * (C) Copyright 2008 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PPC4xx_EBC_H_ +#define _PPC4xx_EBC_H_ + +/* + * Currently there are two register layout versions for the + * IBM EBC core used on 4xx PPC's: + */ +#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \ + defined(CONFIG_405EP) || \ + defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#define CONFIG_EBC_PPC4xx_IBM_VER1 +#endif + +/* Bank Configuration Register */ +#define EBC_BXCR_BAS_MASK PPC_REG_VAL(11, 0xFFF) +#define EBC_BXCR_BAS_ENCODE(n) (((static_cast(u32, n)) & EBC_BXCR_BAS_MASK)) +#define EBC_BXCR_BS_MASK PPC_REG_VAL(14, 0x7) +#define EBC_BXCR_BS_1MB PPC_REG_VAL(14, 0x0) +#define EBC_BXCR_BS_2MB PPC_REG_VAL(14, 0x1) +#define EBC_BXCR_BS_4MB PPC_REG_VAL(14, 0x2) +#define EBC_BXCR_BS_8MB PPC_REG_VAL(14, 0x3) +#define EBC_BXCR_BS_16MB PPC_REG_VAL(14, 0x4) +#define EBC_BXCR_BS_32MB PPC_REG_VAL(14, 0x5) +#define EBC_BXCR_BS_64MB PPC_REG_VAL(14, 0x6) +#define EBC_BXCR_BS_128MB PPC_REG_VAL(14, 0x7) +#define EBC_BXCR_BU_MASK PPC_REG_VAL(16, 0x3) +#define EBC_BXCR_BU_NONE PPC_REG_VAL(16, 0x0) +#define EBC_BXCR_BU_R PPC_REG_VAL(16, 0x1) +#define EBC_BXCR_BU_W PPC_REG_VAL(16, 0x2) +#define EBC_BXCR_BU_RW PPC_REG_VAL(16, 0x3) +#define EBC_BXCR_BW_MASK PPC_REG_VAL(18, 0x3) +#define EBC_BXCR_BW_8BIT PPC_REG_VAL(18, 0x0) +#define EBC_BXCR_BW_16BIT PPC_REG_VAL(18, 0x1) +#if defined(CONFIG_EBC_PPC4xx_IBM_VER1) +#define EBC_BXCR_BW_32BIT PPC_REG_VAL(18, 0x2) +#else +#define EBC_BXCR_BW_32BIT PPC_REG_VAL(18, 0x3) +#endif + +/* Bank Access Parameter Register */ +#define EBC_BXAP_BME_ENABLED PPC_REG_VAL(0, 0x1) +#define EBC_BXAP_BME_DISABLED PPC_REG_VAL(0, 0x0) +#define EBC_BXAP_TWT_ENCODE(n) PPC_REG_VAL(8, (static_cast(u32, n)) & 0xFF) +#define EBC_BXAP_FWT_ENCODE(n) PPC_REG_VAL(5, (static_cast(u32, n)) & 0x1F) +#define EBC_BXAP_BWT_ENCODE(n) PPC_REG_VAL(8, (static_cast(u32, n)) & 0x7) +#define EBC_BXAP_BCE_DISABLE PPC_REG_VAL(9, 0x0) +#define EBC_BXAP_BCE_ENABLE PPC_REG_VAL(9, 0x1) +#define EBC_BXAP_BCT_MASK PPC_REG_VAL(11, 0x3) +#define EBC_BXAP_BCT_2TRANS PPC_REG_VAL(11, 0x0) +#define EBC_BXAP_BCT_4TRANS PPC_REG_VAL(11, 0x1) +#define EBC_BXAP_BCT_8TRANS PPC_REG_VAL(11, 0x2) +#define EBC_BXAP_BCT_16TRANS PPC_REG_VAL(11, 0x3) +#define EBC_BXAP_CSN_ENCODE(n) PPC_REG_VAL(13, (static_cast(u32, n)) & 0x3) +#define EBC_BXAP_OEN_ENCODE(n) PPC_REG_VAL(15, (static_cast(u32, n)) & 0x3) +#define EBC_BXAP_WBN_ENCODE(n) PPC_REG_VAL(17, (static_cast(u32, n)) & 0x3) +#define EBC_BXAP_WBF_ENCODE(n) PPC_REG_VAL(19, (static_cast(u32, n)) & 0x3) +#define EBC_BXAP_TH_ENCODE(n) PPC_REG_VAL(22, (static_cast(u32, n)) & 0x7) +#define EBC_BXAP_RE_ENABLED PPC_REG_VAL(23, 0x1) +#define EBC_BXAP_RE_DISABLED PPC_REG_VAL(23, 0x0) +#define EBC_BXAP_SOR_DELAYED PPC_REG_VAL(24, 0x0) +#define EBC_BXAP_SOR_NONDELAYED PPC_REG_VAL(24, 0x1) +#define EBC_BXAP_BEM_WRITEONLY PPC_REG_VAL(25, 0x0) +#define EBC_BXAP_BEM_RW PPC_REG_VAL(25, 0x1) +#define EBC_BXAP_PEN_DISABLED PPC_REG_VAL(26, 0x0) +#define EBC_BXAP_PEN_ENABLED PPC_REG_VAL(26, 0x1) + +/* Common fields in EBC0_CFG register */ +#define EBC_CFG_PTD_MASK PPC_REG_VAL(1, 0x1) +#define EBC_CFG_PTD_ENABLE PPC_REG_VAL(1, 0x0) +#define EBC_CFG_PTD_DISABLE PPC_REG_VAL(1, 0x1) +#define EBC_CFG_RTC_MASK PPC_REG_VAL(4, 0x7) +#define EBC_CFG_RTC_16PERCLK PPC_REG_VAL(4, 0x0) +#define EBC_CFG_RTC_32PERCLK PPC_REG_VAL(4, 0x1) +#define EBC_CFG_RTC_64PERCLK PPC_REG_VAL(4, 0x2) +#define EBC_CFG_RTC_128PERCLK PPC_REG_VAL(4, 0x3) +#define EBC_CFG_RTC_256PERCLK PPC_REG_VAL(4, 0x4) +#define EBC_CFG_RTC_512PERCLK PPC_REG_VAL(4, 0x5) +#define EBC_CFG_RTC_1024PERCLK PPC_REG_VAL(4, 0x6) +#define EBC_CFG_RTC_2048PERCLK PPC_REG_VAL(4, 0x7) +#define EBC_CFG_PME_MASK PPC_REG_VAL(14, 0x1) +#define EBC_CFG_PME_DISABLE PPC_REG_VAL(14, 0x0) +#define EBC_CFG_PME_ENABLE PPC_REG_VAL(14, 0x1) +#define EBC_CFG_PMT_MASK PPC_REG_VAL(19, 0x1F) +#define EBC_CFG_PMT_ENCODE(n) PPC_REG_VAL(19, (static_cast(u32, n)) & 0x1F) + +/* Now the two versions of the other bits */ +#if defined(CONFIG_EBC_PPC4xx_IBM_VER1) +#define EBC_CFG_EBTC_MASK PPC_REG_VAL(0, 0x1) +#define EBC_CFG_EBTC_HI PPC_REG_VAL(0, 0x0) +#define EBC_CFG_EBTC_DRIVEN PPC_REG_VAL(0, 0x1) +#define EBC_CFG_EMPH_MASK PPC_REG_VAL(6, 0x3) +#define EBC_CFG_EMPH_ENCODE(n) PPC_REG_VAL(6, (static_cast(u32, n)) & 0x3) +#define EBC_CFG_EMPL_MASK PPC_REG_VAL(8, 0x3) +#define EBC_CFG_EMPL_ENCODE(n) PPC_REG_VAL(8, (static_cast(u32, n)) & 0x3) +#define EBC_CFG_CSTC_MASK PPC_REG_VAL(9, 0x1) +#define EBC_CFG_CSTC_HI PPC_REG_VAL(9, 0x0) +#define EBC_CFG_CSTC_DRIVEN PPC_REG_VAL(9, 0x1) +#define EBC_CFG_BPR_MASK PPC_REG_VAL(11, 0x3) +#define EBC_CFG_BPR_1DW PPC_REG_VAL(11, 0x0) +#define EBC_CFG_BPR_2DW PPC_REG_VAL(11, 0x1) +#define EBC_CFG_BPR_4DW PPC_REG_VAL(11, 0x2) +#define EBC_CFG_EMS_MASK PPC_REG_VAL(13, 0x3) +#define EBC_CFG_EMS_8BIT PPC_REG_VAL(13, 0x0) +#define EBC_CFG_EMS_16BIT PPC_REG_VAL(13, 0x1) +#define EBC_CFG_EMS_32BIT PPC_REG_VAL(13, 0x2) +#else +#define EBC_CFG_LE_MASK PPC_REG_VAL(0, 0x1) +#define EBC_CFG_LE_UNLOCK PPC_REG_VAL(0, 0x0) +#define EBC_CFG_LE_LOCK PPC_REG_VAL(0, 0x1) +#define EBC_CFG_ATC_MASK PPC_REG_VAL(5, 0x1) +#define EBC_CFG_ATC_HI PPC_REG_VAL(5, 0x0) +#define EBC_CFG_ATC_PREVIOUS PPC_REG_VAL(5, 0x1) +#define EBC_CFG_DTC_MASK PPC_REG_VAL(6, 0x1) +#define EBC_CFG_DTC_HI PPC_REG_VAL(6, 0x0) +#define EBC_CFG_DTC_PREVIOUS PPC_REG_VAL(6, 0x1) +#define EBC_CFG_CTC_MASK PPC_REG_VAL(7, 0x1) +#define EBC_CFG_CTC_HI PPC_REG_VAL(7, 0x0) +#define EBC_CFG_CTC_PREVIOUS PPC_REG_VAL(7, 0x1) +#define EBC_CFG_OEO_MASK PPC_REG_VAL(8, 0x1) +#define EBC_CFG_OEO_HI PPC_REG_VAL(8, 0x0) +#define EBC_CFG_OEO_PREVIOUS PPC_REG_VAL(8, 0x1) +#define EBC_CFG_EMC_MASK PPC_REG_VAL(9, 0x1) +#define EBC_CFG_EMC_NONDEFAULT PPC_REG_VAL(9, 0x0) +#define EBC_CFG_EMC_DEFAULT PPC_REG_VAL(9, 0x1) +#define EBC_CFG_PR_MASK PPC_REG_VAL(21, 0x3) +#define EBC_CFG_PR_16 PPC_REG_VAL(21, 0x0) +#define EBC_CFG_PR_32 PPC_REG_VAL(21, 0x1) +#define EBC_CFG_PR_64 PPC_REG_VAL(21, 0x2) +#define EBC_CFG_PR_128 PPC_REG_VAL(21, 0x3) +#endif + +#endif /* _PPC4xx_EBC_H_ */ diff --git a/include/asm-ppc/ppc4xx-intvec.h b/include/asm-ppc/ppc4xx-intvec.h deleted file mode 100644 index 5b45de4..0000000 --- a/include/asm-ppc/ppc4xx-intvec.h +++ /dev/null @@ -1,474 +0,0 @@ -/* -* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> -* -* See file CREDITS for list of people who contributed to this -* project. -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License as -* published by the Free Software Foundation; either version 2 of -* the License, or (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 59 Temple Place, Suite 330, Boston, -* MA 02111-1307 USA -*/ - -/* - * Interrupt vector number definitions to ease the - * 405 -- 440 porting pain ;-) - * - * NOTE: They're not all here yet ... update as needed. - * - */ - -#ifndef _VECNUMS_H_ -#define _VECNUMS_H_ - -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) - -/* UIC 0 */ -#define VECNUM_U0 0 /* UART 0 */ -#define VECNUM_U1 1 /* UART 1 */ -#define VECNUM_IIC0 2 /* IIC */ -#define VECNUM_KRD 3 /* Kasumi Ready for data */ -#define VECNUM_KDA 4 /* Kasumi Data Available */ -#define VECNUM_PCRW 5 /* PCI command register write */ -#define VECNUM_PPM 6 /* PCI power management */ -#define VECNUM_IIC1 7 /* IIC */ -#define VECNUM_SPI 8 /* SPI */ -#define VECNUM_EPCISER 9 /* External PCI SERR */ -#define VECNUM_MTE 10 /* MAL TXEOB */ -#define VECNUM_MRE 11 /* MAL RXEOB */ -#define VECNUM_D0 12 /* DMA channel 0 */ -#define VECNUM_D1 13 /* DMA channel 1 */ -#define VECNUM_D2 14 /* DMA channel 2 */ -#define VECNUM_D3 15 /* DMA channel 3 */ -#define VECNUM_UD0 16 /* UDMA irq 0 */ -#define VECNUM_UD1 17 /* UDMA irq 1 */ -#define VECNUM_UD2 18 /* UDMA irq 2 */ -#define VECNUM_UD3 19 /* UDMA irq 3 */ -#define VECNUM_HSB2D 20 /* USB2.0 Device */ -#define VECNUM_USBDEV 20 /* USB 1.1/USB 2.0 Device */ -#define VECNUM_OHCI1 21 /* USB2.0 Host OHCI irq 1 */ -#define VECNUM_OHCI2 22 /* USB2.0 Host OHCI irq 2 */ -#define VECNUM_EIP94 23 /* Security EIP94 */ -#define VECNUM_ETH0 24 /* Emac 0 */ -#define VECNUM_ETH1 25 /* Emac 1 */ -#define VECNUM_EHCI 26 /* USB2.0 Host EHCI */ -#define VECNUM_EIR4 27 /* External interrupt 4 */ -#define VECNUM_UIC2NC 28 /* UIC2 non-critical interrupt */ -#define VECNUM_UIC2C 29 /* UIC2 critical interrupt */ -#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ -#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ - -/* UIC 1 */ -#define VECNUM_MS (32 + 0) /* MAL SERR */ -#define VECNUM_MTDE (32 + 1) /* MAL TXDE */ -#define VECNUM_MRDE (32 + 2) /* MAL RXDE */ -#define VECNUM_U2 (32 + 3) /* UART 2 */ -#define VECNUM_U3 (32 + 4) /* UART 3 */ -#define VECNUM_EBCO (32 + 5) /* EBCO interrupt status */ -#define VECNUM_NDFC (32 + 6) /* NDFC */ -#define VECNUM_KSLE (32 + 7) /* KASUMI slave error */ -#define VECNUM_CT5 (32 + 8) /* GPT compare timer 5 */ -#define VECNUM_CT6 (32 + 9) /* GPT compare timer 6 */ -#define VECNUM_PLB34I0 (32 + 10) /* PLB3X4X MIRQ0 */ -#define VECNUM_PLB34I1 (32 + 11) /* PLB3X4X MIRQ1 */ -#define VECNUM_PLB34I2 (32 + 12) /* PLB3X4X MIRQ2 */ -#define VECNUM_PLB34I3 (32 + 13) /* PLB3X4X MIRQ3 */ -#define VECNUM_PLB34I4 (32 + 14) /* PLB3X4X MIRQ4 */ -#define VECNUM_PLB34I5 (32 + 15) /* PLB3X4X MIRQ5 */ -#define VECNUM_CT0 (32 + 16) /* GPT compare timer 0 */ -#define VECNUM_CT1 (32 + 17) /* GPT compare timer 1 */ -#define VECNUM_EIR7 (32 + 18) /* External interrupt 7 */ -#define VECNUM_EIR8 (32 + 19) /* External interrupt 8 */ -#define VECNUM_EIR9 (32 + 20) /* External interrupt 9 */ -#define VECNUM_CT2 (32 + 21) /* GPT compare timer 2 */ -#define VECNUM_CT3 (32 + 22) /* GPT compare timer 3 */ -#define VECNUM_CT4 (32 + 23) /* GPT compare timer 4 */ -#define VECNUM_SRE (32 + 24) /* Serial ROM error */ -#define VECNUM_GPTDC (32 + 25) /* GPT decrementer pulse */ -#define VECNUM_RSVD0 (32 + 26) /* Reserved */ -#define VECNUM_EPCIPER (32 + 27) /* External PCI PERR */ -#define VECNUM_EIR0 (32 + 28) /* External interrupt 0 */ -#define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */ -#define VECNUM_EIR1 (32 + 30) /* External interrupt 1 */ -#define VECNUM_EWU1 (32 + 31) /* Ethernet 1 wakeup */ - -#define VECNUM_TXDE VECNUM_MTDE -#define VECNUM_RXDE VECNUM_MRDE - -/* UIC 2 */ -#define VECNUM_EIR5 (64 + 0) /* External interrupt 5 */ -#define VECNUM_EIR6 (64 + 1) /* External interrupt 6 */ -#define VECNUM_OPB (64 + 2) /* OPB to PLB bridge int stat */ -#define VECNUM_EIR2 (64 + 3) /* External interrupt 2 */ -#define VECNUM_EIR3 (64 + 4) /* External interrupt 3 */ -#define VECNUM_DDR2 (64 + 5) /* DDR2 sdram */ -#define VECNUM_MCTX0 (64 + 6) /* MAl intp coalescence TX0 */ -#define VECNUM_MCTX1 (64 + 7) /* MAl intp coalescence TX1 */ -#define VECNUM_MCTR0 (64 + 8) /* MAl intp coalescence TR0 */ -#define VECNUM_MCTR1 (64 + 9) /* MAl intp coalescence TR1 */ - -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) - -/* UIC 0 */ -#define VECNUM_U1 1 /* UART1 */ -#define VECNUM_IIC0 2 /* IIC0 */ -#define VECNUM_IIC1 3 /* IIC1 */ -#define VECNUM_PIM 4 /* PCI inbound message */ -#define VECNUM_PCRW 5 /* PCI command reg write */ -#define VECNUM_PPM 6 /* PCI power management */ -#define VECNUM_MSI0 8 /* PCI MSI level 0 */ -#define VECNUM_EIR0 9 /* External interrupt 0 */ -#define VECNUM_UIC2NC 10 /* UIC2 non-critical interrupt */ -#define VECNUM_UIC2C 11 /* UIC2 critical interrupt */ -#define VECNUM_D0 12 /* DMA channel 0 */ -#define VECNUM_D1 13 /* DMA channel 1 */ -#define VECNUM_D2 14 /* DMA channel 2 */ -#define VECNUM_D3 15 /* DMA channel 3 */ -#define VECNUM_UIC3NC 16 /* UIC3 non-critical interrupt */ -#define VECNUM_UIC3C 17 /* UIC3 critical interrupt */ -#define VECNUM_EIR1 9 /* External interrupt 1 */ -#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ -#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ - -/* UIC 1 */ -#define VECNUM_EIR2 (32 + 0) /* External interrupt 0 */ -#define VECNUM_U0 (32 + 1) /* UART0 */ -#define VECNUM_EIR3 (32 + 20) /* External interrupt 3 */ -#define VECNUM_EIR4 (32 + 21) /* External interrupt 4 */ -#define VECNUM_EIR5 (32 + 26) /* External interrupt 5 */ -#define VECNUM_EIR6 (32 + 27) /* External interrupt 6 */ -#define VECNUM_U2 (32 + 28) /* UART2 */ -#define VECNUM_U3 (32 + 29) /* UART3 */ -#define VECNUM_EIR7 (32 + 30) /* External interrupt 7 */ -#define VECNUM_EIR8 (32 + 31) /* External interrupt 8 */ - -/* UIC 2 */ -#define VECNUM_EIR9 (64 + 2) /* External interrupt 9 */ -#define VECNUM_MS (64 + 3) /* MAL SERR */ -#define VECNUM_TXDE (64 + 4) /* MAL TXDE */ -#define VECNUM_RXDE (64 + 5) /* MAL RXDE */ -#define VECNUM_MTE (64 + 6) /* MAL TXEOB */ -#define VECNUM_MRE (64 + 7) /* MAL RXEOB */ -#define VECNUM_ETH0 (64 + 16) /* Ethernet 0 */ -#define VECNUM_ETH1 (64 + 17) /* Ethernet 1 */ -#define VECNUM_ETH2 (64 + 18) /* Ethernet 2 */ -#define VECNUM_ETH3 (64 + 19) /* Ethernet 3 */ -#define VECNUM_EWU0 (64 + 20) /* Emac 0 wakeup */ -#define VECNUM_EWU1 (64 + 21) /* Emac 1 wakeup */ -#define VECNUM_EWU2 (64 + 22) /* Emac 2 wakeup */ -#define VECNUM_EWU3 (64 + 23) /* Emac 3 wakeup */ -#define VECNUM_EIR10 (64 + 24) /* External interrupt 10 */ -#define VECNUM_EIR11 (64 + 25) /* External interrupt 11 */ - -/* UIC 3 */ -#define VECNUM_EIR12 (96 + 20) /* External interrupt 20 */ -#define VECNUM_EIR13 (96 + 21) /* External interrupt 21 */ -#define VECNUM_EIR14 (96 + 22) /* External interrupt 22 */ -#define VECNUM_EIR15 (96 + 23) /* External interrupt 23 */ -#define VECNUM_PCIEMSI0 (96 + 24) /* PCI Express MSI level 0 */ -#define VECNUM_PCIEMSI1 (96 + 25) /* PCI Express MSI level 1 */ -#define VECNUM_PCIEMSI2 (96 + 26) /* PCI Express MSI level 2 */ -#define VECNUM_PCIEMSI3 (96 + 27) /* PCI Express MSI level 3 */ -#define VECNUM_PCIEMSI4 (96 + 28) /* PCI Express MSI level 4 */ -#define VECNUM_PCIEMSI5 (96 + 29) /* PCI Express MSI level 5 */ -#define VECNUM_PCIEMSI6 (96 + 30) /* PCI Express MSI level 6 */ -#define VECNUM_PCIEMSI7 (96 + 31) /* PCI Express MSI level 7 */ - -#elif defined(CONFIG_440SPE) - -/* UIC 0 */ -#define VECNUM_U0 0 /* UART0 */ -#define VECNUM_U1 1 /* UART1 */ -#define VECNUM_IIC0 2 /* IIC0 */ -#define VECNUM_IIC1 3 /* IIC1 */ -#define VECNUM_PIM 4 /* PCI inbound message */ -#define VECNUM_PCRW 5 /* PCI command reg write */ -#define VECNUM_PPM 6 /* PCI power management */ -#define VECNUM_MSI0 7 /* PCI MSI level 0 */ -#define VECNUM_MSI1 8 /* PCI MSI level 0 */ -#define VECNUM_MSI2 9 /* PCI MSI level 0 */ -#define VECNUM_UIC2NC 10 /* UIC2 non-critical interrupt */ -#define VECNUM_UIC2C 11 /* UIC2 critical interrupt */ -#define VECNUM_D0 12 /* DMA channel 0 */ -#define VECNUM_D1 13 /* DMA channel 1 */ -#define VECNUM_D2 14 /* DMA channel 2 */ -#define VECNUM_D3 15 /* DMA channel 3 */ -#define VECNUM_UIC3NC 16 /* UIC3 non-critical interrupt */ -#define VECNUM_UIC3C 17 /* UIC3 critical interrupt */ -#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ -#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ - -/* UIC 1 */ -#define VECNUM_MS (32 + 1 ) /* MAL SERR */ -#define VECNUM_TXDE (32 + 2 ) /* MAL TXDE */ -#define VECNUM_RXDE (32 + 3 ) /* MAL RXDE */ -#define VECNUM_MTE (32 + 6 ) /* MAL Tx EOB */ -#define VECNUM_MRE (32 + 7 ) /* MAL Rx EOB */ -#define VECNUM_CT0 (32 + 12 ) /* GPT compare timer 0 */ -#define VECNUM_CT1 (32 + 13 ) /* GPT compare timer 1 */ -#define VECNUM_CT2 (32 + 14 ) /* GPT compare timer 2 */ -#define VECNUM_CT3 (32 + 15 ) /* GPT compare timer 3 */ -#define VECNUM_CT4 (32 + 16 ) /* GPT compare timer 4 */ -#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */ -#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */ - -/* UIC 2 */ -#define VECNUM_EIR5 (64 + 24) /* External interrupt 5 */ -#define VECNUM_EIR4 (64 + 25) /* External interrupt 4 */ -#define VECNUM_EIR3 (64 + 26) /* External interrupt 3 */ -#define VECNUM_EIR2 (64 + 27) /* External interrupt 2 */ -#define VECNUM_EIR1 (64 + 28) /* External interrupt 1 */ -#define VECNUM_EIR0 (64 + 29) /* External interrupt 0 */ - -#elif defined(CONFIG_440SP) - -/* UIC 0 */ -#define VECNUM_U0 0 /* UART0 */ -#define VECNUM_U1 1 /* UART1 */ -#define VECNUM_IIC0 2 /* IIC0 */ -#define VECNUM_IIC1 3 /* IIC1 */ -#define VECNUM_PIM 4 /* PCI inbound message */ -#define VECNUM_PCRW 5 /* PCI command reg write */ -#define VECNUM_PPM 6 /* PCI power management */ -#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ -#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ - -/* UIC 1 */ -#define VECNUM_EIR0 (32 + 0) /* External interrupt 0 */ -#define VECNUM_MS (32 + 1) /* MAL SERR */ -#define VECNUM_TXDE (32 + 2) /* MAL TXDE */ -#define VECNUM_RXDE (32 + 3) /* MAL RXDE */ -#define VECNUM_MTE (32 + 6) /* MAL Tx EOB */ -#define VECNUM_MRE (32 + 7) /* MAL Rx EOB */ -#define VECNUM_CT0 (32 + 12) /* GPT compare timer 0 */ -#define VECNUM_CT1 (32 + 13) /* GPT compare timer 1 */ -#define VECNUM_CT2 (32 + 14) /* GPT compare timer 2 */ -#define VECNUM_CT3 (32 + 15) /* GPT compare timer 3 */ -#define VECNUM_CT4 (32 + 16) /* GPT compare timer 4 */ -#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */ -#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */ - -#elif defined(CONFIG_440) - -/* UIC 0 */ -#define VECNUM_U0 0 /* UART0 */ -#define VECNUM_U1 1 /* UART1 */ -#define VECNUM_IIC0 2 /* IIC0 */ -#define VECNUM_IIC1 3 /* IIC1 */ -#define VECNUM_PIM 4 /* PCI inbound message */ -#define VECNUM_PCRW 5 /* PCI command reg write */ -#define VECNUM_PPM 6 /* PCI power management */ -#define VECNUM_MSI0 7 /* PCI MSI level 0 */ -#define VECNUM_MSI1 8 /* PCI MSI level 0 */ -#define VECNUM_MSI2 9 /* PCI MSI level 0 */ -#define VECNUM_MTE 10 /* MAL TXEOB */ -#define VECNUM_MRE 11 /* MAL RXEOB */ -#define VECNUM_D0 12 /* DMA channel 0 */ -#define VECNUM_D1 13 /* DMA channel 1 */ -#define VECNUM_D2 14 /* DMA channel 2 */ -#define VECNUM_D3 15 /* DMA channel 3 */ -#define VECNUM_CT0 18 /* GPT compare timer 0 */ -#define VECNUM_CT1 19 /* GPT compare timer 1 */ -#define VECNUM_CT2 20 /* GPT compare timer 2 */ -#define VECNUM_CT3 21 /* GPT compare timer 3 */ -#define VECNUM_CT4 22 /* GPT compare timer 4 */ -#define VECNUM_EIR0 23 /* External interrupt 0 */ -#define VECNUM_EIR1 24 /* External interrupt 1 */ -#define VECNUM_EIR2 25 /* External interrupt 2 */ -#define VECNUM_EIR3 26 /* External interrupt 3 */ -#define VECNUM_EIR4 27 /* External interrupt 4 */ -#define VECNUM_EIR5 28 /* External interrupt 5 */ -#define VECNUM_EIR6 29 /* External interrupt 6 */ -#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ -#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ - -/* UIC 1 */ -#define VECNUM_MS (32 + 0 ) /* MAL SERR */ -#define VECNUM_TXDE (32 + 1 ) /* MAL TXDE */ -#define VECNUM_RXDE (32 + 2 ) /* MAL RXDE */ -#define VECNUM_USBDEV (32 + 23) /* USB 1.1/USB 2.0 Device */ -#define VECNUM_ETH0 (32 + 28) /* Ethernet 0 interrupt status */ -#define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */ - -#else /* !defined(CONFIG_440) */ - -#if defined(CONFIG_405EZ) -#define VECNUM_D0 0 /* DMA channel 0 */ -#define VECNUM_D1 1 /* DMA channel 1 */ -#define VECNUM_D2 2 /* DMA channel 2 */ -#define VECNUM_D3 3 /* DMA channel 3 */ -#define VECNUM_1588 4 /* IEEE 1588 network synchronization */ -#define VECNUM_U0 5 /* UART0 */ -#define VECNUM_U1 6 /* UART1 */ -#define VECNUM_CAN0 7 /* CAN 0 */ -#define VECNUM_CAN1 8 /* CAN 1 */ -#define VECNUM_SPI 9 /* SPI */ -#define VECNUM_IIC0 10 /* I2C */ -#define VECNUM_CHT0 11 /* Chameleon timer high pri interrupt */ -#define VECNUM_CHT1 12 /* Chameleon timer high pri interrupt */ -#define VECNUM_USBH1 13 /* USB Host 1 */ -#define VECNUM_USBH2 14 /* USB Host 2 */ -#define VECNUM_USBDEV 15 /* USB Device */ -#define VECNUM_ETH0 16 /* 10/100 Ethernet interrupt status */ -#define VECNUM_EWU0 17 /* Ethernet wakeup sequence detected */ - -#define VECNUM_MADMAL 18 /* Logical OR of following MadMAL int */ -#define VECNUM_MS 18 /* MAL_SERR_INT */ -#define VECNUM_TXDE 18 /* MAL_TXDE_INT */ -#define VECNUM_RXDE 18 /* MAL_RXDE_INT */ - -#define VECNUM_MTE 19 /* MAL TXEOB */ -#define VECNUM_MTE1 20 /* MAL TXEOB1 */ -#define VECNUM_MRE 21 /* MAL RXEOB */ -#define VECNUM_NAND 22 /* NAND Flash controller */ -#define VECNUM_ADC 23 /* ADC */ -#define VECNUM_DAC 24 /* DAC */ -#define VECNUM_OPB2PLB 25 /* OPB to PLB bridge interrupt */ -#define VECNUM_RESERVED0 26 /* Reserved */ -#define VECNUM_EIR0 27 /* External interrupt 0 */ -#define VECNUM_EIR1 28 /* External interrupt 1 */ -#define VECNUM_EIR2 29 /* External interrupt 2 */ -#define VECNUM_EIR3 30 /* External interrupt 3 */ -#define VECNUM_EIR4 31 /* External interrupt 4 */ - -#elif defined(CONFIG_405EX) - -/* UIC 0 */ -#define VECNUM_U0 00 -#define VECNUM_U1 01 -#define VECNUM_IIC0 02 -#define VECNUM_PKA 03 -#define VECNUM_TRNG 04 -#define VECNUM_EBM 05 -#define VECNUM_BGI 06 -#define VECNUM_IIC1 07 -#define VECNUM_SPI 08 -#define VECNUM_EIR0 09 -#define VECNUM_MTE 10 /* MAL Tx EOB */ -#define VECNUM_MRE 11 /* MAL Rx EOB */ -#define VECNUM_DMA0 12 -#define VECNUM_DMA1 13 -#define VECNUM_DMA2 14 -#define VECNUM_DMA3 15 -#define VECNUM_PCIE0AL 16 -#define VECNUM_PCIE0VPD 17 -#define VECNUM_RPCIE0HRST 18 -#define VECNUM_FPCIE0HRST 19 -#define VECNUM_PCIE0TCR 20 -#define VECNUM_PCIEMSI0 21 -#define VECNUM_PCIEMSI1 22 -#define VECNUM_SECURITY 23 -#define VECNUM_ETH0 24 -#define VECNUM_ETH1 25 -#define VECNUM_PCIEMSI2 26 -#define VECNUM_EIR4 27 -#define VECNUM_UIC2NC 28 -#define VECNUM_UIC2C 29 -#define VECNUM_UIC1NC 30 -#define VECNUM_UIC1C 31 - -/* UIC 1 */ -#define VECNUM_MS (32 + 00) /* MAL SERR */ -#define VECNUM_TXDE (32 + 01) /* MAL TXDE */ -#define VECNUM_RXDE (32 + 02) /* MAL RXDE */ -#define VECNUM_PCIE0BMVC0 (32 + 03) -#define VECNUM_PCIE0DCRERR (32 + 04) -#define VECNUM_EBC (32 + 05) -#define VECNUM_NDFC (32 + 06) -#define VECNUM_PCEI1DCRERR (32 + 07) -#define VECNUM_CT8 (32 + 08) -#define VECNUM_CT9 (32 + 09) -#define VECNUM_PCIE1AL (32 + 10) -#define VECNUM_PCIE1VPD (32 + 11) -#define VECNUM_RPCE1HRST (32 + 12) -#define VECNUM_FPCE1HRST (32 + 13) -#define VECNUM_PCIE1TCR (32 + 14) -#define VECNUM_PCIE1VC0 (32 + 15) -#define VECNUM_CT3 (32 + 16) -#define VECNUM_CT4 (32 + 17) -#define VECNUM_EIR7 (32 + 18) -#define VECNUM_EIR8 (32 + 19) -#define VECNUM_EIR9 (32 + 20) -#define VECNUM_CT5 (32 + 21) -#define VECNUM_CT6 (32 + 22) -#define VECNUM_CT7 (32 + 23) -#define VECNUM_SROM (32 + 24) /* SERIAL ROM */ -#define VECNUM_GPTDECPULS (32 + 25) /* GPT Decrement pulse */ -#define VECNUM_EIR2 (32 + 26) -#define VECNUM_EIR5 (32 + 27) -#define VECNUM_EIR6 (32 + 28) -#define VECNUM_EMAC0WAKE (32 + 29) -#define VECNUM_EIR1 (32 + 30) -#define VECNUM_EMAC1WAKE (32 + 31) - -/* UIC 2 */ -#define VECNUM_PCIE0INTA (64 + 00) /* PCIE0 INTA */ -#define VECNUM_PCIE0INTB (64 + 01) /* PCIE0 INTB */ -#define VECNUM_PCIE0INTC (64 + 02) /* PCIE0 INTC */ -#define VECNUM_PCIE0INTD (64 + 03) /* PCIE0 INTD */ -#define VECNUM_EIR3 (64 + 04) /* External IRQ 3 */ -#define VECNUM_DDRMCUE (64 + 05) -#define VECNUM_DDRMCCE (64 + 06) -#define VECNUM_MALINTCOATX0 (64 + 07) /* Interrupt coalecence TX0 */ -#define VECNUM_MALINTCOATX1 (64 + 08) /* Interrupt coalecence TX1 */ -#define VECNUM_MALINTCOARX0 (64 + 09) /* Interrupt coalecence RX0 */ -#define VECNUM_MALINTCOARX1 (64 + 10) /* Interrupt coalecence RX1 */ -#define VECNUM_PCIE1INTA (64 + 11) /* PCIE0 INTA */ -#define VECNUM_PCIE1INTB (64 + 12) /* PCIE0 INTB */ -#define VECNUM_PCIE1INTC (64 + 13) /* PCIE0 INTC */ -#define VECNUM_PCIE1INTD (64 + 14) /* PCIE0 INTD */ -#define VECNUM_RPCIEMSI2 (64 + 15) /* MSI level 2 */ -#define VECNUM_PCIEMSI3 (64 + 16) /* MSI level 2 */ -#define VECNUM_PCIEMSI4 (64 + 17) /* MSI level 2 */ -#define VECNUM_PCIEMSI5 (64 + 18) /* MSI level 2 */ -#define VECNUM_PCIEMSI6 (64 + 19) /* MSI level 2 */ -#define VECNUM_PCIEMSI7 (64 + 20) /* MSI level 2 */ -#define VECNUM_PCIEMSI8 (64 + 21) /* MSI level 2 */ -#define VECNUM_PCIEMSI9 (64 + 22) /* MSI level 2 */ -#define VECNUM_PCIEMSI10 (64 + 23) /* MSI level 2 */ -#define VECNUM_PCIEMSI11 (64 + 24) /* MSI level 2 */ -#define VECNUM_PCIEMSI12 (64 + 25) /* MSI level 2 */ -#define VECNUM_PCIEMSI13 (64 + 26) /* MSI level 2 */ -#define VECNUM_PCIEMSI14 (64 + 27) /* MSI level 2 */ -#define VECNUM_PCIEMSI15 (64 + 28) /* MSI level 2 */ -#define VECNUM_PLB4XAHB (64 + 29) /* PLBxAHB bridge */ -#define VECNUM_USBWAKE (64 + 30) /* USB wakup */ -#define VECNUM_USBOTG (64 + 31) /* USB OTG */ - -#else /* !CONFIG_405EZ */ - -#define VECNUM_U0 0 /* UART0 */ -#define VECNUM_U1 1 /* UART1 */ -#define VECNUM_D0 5 /* DMA channel 0 */ -#define VECNUM_D1 6 /* DMA channel 1 */ -#define VECNUM_D2 7 /* DMA channel 2 */ -#define VECNUM_D3 8 /* DMA channel 3 */ -#define VECNUM_EWU0 9 /* Ethernet wakeup */ -#define VECNUM_MS 10 /* MAL SERR */ -#define VECNUM_MTE 11 /* MAL TXEOB */ -#define VECNUM_MRE 12 /* MAL RXEOB */ -#define VECNUM_TXDE 13 /* MAL TXDE */ -#define VECNUM_RXDE 14 /* MAL RXDE */ -#define VECNUM_ETH0 15 /* Ethernet interrupt status */ -#define VECNUM_EIR0 25 /* External interrupt 0 */ -#define VECNUM_EIR1 26 /* External interrupt 1 */ -#define VECNUM_EIR2 27 /* External interrupt 2 */ -#define VECNUM_EIR3 28 /* External interrupt 3 */ -#define VECNUM_EIR4 29 /* External interrupt 4 */ -#define VECNUM_EIR5 30 /* External interrupt 5 */ -#define VECNUM_EIR6 31 /* External interrupt 6 */ -#endif /* defined(CONFIG_405EZ) */ - -#endif /* defined(CONFIG_440) */ - -#endif /* _VECNUMS_H_ */ diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index e151f0c..df787b3 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -282,7 +282,8 @@ * Memory Bank 0-7 configuration */ #if defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) #define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */ #define SDRAM_RXBAS_SDBA_ENCODE(n) ((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000)) #define SDRAM_RXBAS_SDBA_DECODE(n) ((((phys_size_t)(n)) & 0xFFE00000) << 2) @@ -353,7 +354,19 @@ /* * Memory controller registers */ +#define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */ +#define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */ +#define SDRAM_BEARL 0x02 /* PLB bus error address low */ +#define SDRAM_BEARH 0x03 /* PLB bus error address high */ +#define SDRAM_WMIRQ 0x06 /* PLB write master interrupt (read/clear) */ +#define SDRAM_WMIRQT 0x07 /* PLB write master interrupt (test/set) */ +#define SDRAM_PLBOPT 0x08 /* PLB slave options */ +#define SDRAM_PUABA 0x09 /* PLB upper address base */ +#ifndef CONFIG_405EX #define SDRAM_MCSTAT 0x14 /* memory controller status */ +#else +#define SDRAM_MCSTAT 0x1F /* memory controller status */ +#endif #define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ #define SDRAM_MCOPT2 0x21 /* memory controller options 2 */ #define SDRAM_MODT0 0x22 /* on die termination for bank 0 */ @@ -398,9 +411,35 @@ #define SDRAM_MMODE 0x88 /* memory mode */ #define SDRAM_MEMODE 0x89 /* memory extended mode */ #define SDRAM_ECCCR 0x98 /* ECC error status */ +#define SDRAM_ECCES SDRAM_ECCCR #define SDRAM_CID 0xA4 /* core ID */ +#ifndef CONFIG_405EX #define SDRAM_RID 0xA8 /* revision ID */ +#endif +#define SDRAM_FCSR 0xB0 /* feedback calibration status */ #define SDRAM_RTSR 0xB1 /* run time status tracking */ +#ifdef CONFIG_405EX +#define SDRAM_RID 0xF8 /* revision ID */ +#endif + +/* + * Memory Controller Bus Error Status + */ +#define SDRAM_BESR_MASK PPC_REG_VAL(7, 0xFF) +#define SDRAM_BESR_M0ID_MASK PPC_REG_VAL(3, 0xF) +#define SDRAM_BESR_M0ID_ICU PPC_REG_VAL(3, 0x0) +#define SDRAM_BESR_M0ID_PCIE0 PPC_REG_VAL(3, 0x1) +#define SDRAM_BESR_M0ID_PCIE1 PPC_REG_VAL(3, 0x2) +#define SDRAM_BESR_M0ID_DMA PPC_REG_VAL(3, 0x3) +#define SDRAM_BESR_M0ID_DCU PPC_REG_VAL(3, 0x4) +#define SDRAM_BESR_M0ID_OPB PPC_REG_VAL(3, 0x5) +#define SDRAM_BESR_M0ID_MAL PPC_REG_VAL(3, 0x6) +#define SDRAM_BESR_M0ID_SEC PPC_REG_VAL(3, 0x7) +#define SDRAM_BESR_M0ET_MASK PPC_REG_VAL(6, 0x7) +#define SDRAM_BESR_M0ET_NONE PPC_REG_VAL(6, 0x0) +#define SDRAM_BESR_M0ET_ECC PPC_REG_VAL(6, 0x1) +#define SDRAM_BESR_M0RW_WRITE PPC_REG_VAL(7, 0) +#define SDRAM_BESR_M0RW_READ PPC_REG_VAL(8, 1) /* * Memory Controller Status @@ -523,7 +562,7 @@ * SDRAM Delay Line Calibration Register */ #define SDRAM_DLCR_DCLM_MASK 0x80000000 -#define SDRAM_DLCR_DCLM_MANUEL 0x80000000 +#define SDRAM_DLCR_DCLM_MANUAL 0x80000000 #define SDRAM_DLCR_DCLM_AUTO 0x00000000 #define SDRAM_DLCR_DLCR_MASK 0x08000000 #define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000 @@ -539,59 +578,234 @@ #define SDRAM_DLCR_DLCV_DECODE(n) ((((u32)(n))>>0)&0x1FF) /* + * SDRAM Memory On Die Terimination Control Register + */ +#define SDRAM_MODT_ODTON_DISABLE PPC_REG_VAL(0, 0) +#define SDRAM_MODT_ODTON_ENABLE PPC_REG_VAL(0, 1) +#define SDRAM_MODT_EB1W_DISABLE PPC_REG_VAL(1, 0) +#define SDRAM_MODT_EB1W_ENABLE PPC_REG_VAL(1, 1) +#define SDRAM_MODT_EB1R_DISABLE PPC_REG_VAL(2, 0) +#define SDRAM_MODT_EB1R_ENABLE PPC_REG_VAL(2, 1) +#define SDRAM_MODT_EB0W_DISABLE PPC_REG_VAL(7, 0) +#define SDRAM_MODT_EB0W_ENABLE PPC_REG_VAL(7, 1) +#define SDRAM_MODT_EB0R_DISABLE PPC_REG_VAL(8, 0) +#define SDRAM_MODT_EB0R_ENABLE PPC_REG_VAL(8, 1) + +/* * SDRAM Controller On Die Termination Register */ -#define SDRAM_CODT_ODT_ON 0x80000000 -#define SDRAM_CODT_ODT_OFF 0x00000000 -#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020 -#define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000 -#define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020 -#define SDRAM_CODT_DQS_MASK 0x00000010 -#define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000 -#define SDRAM_CODT_DQS_SINGLE_END 0x00000010 -#define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000 -#define SDRAM_CODT_CKSE_SINGLE_END 0x00000008 -#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004 -#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002 -#define SDRAM_CODT_IO_HIZ 0x00000000 -#define SDRAM_CODT_IO_NMODE 0x00000001 +#define SDRAM_CODT_ODT_ON PPC_REG_VAL(0, 1) +#define SDRAM_CODT_ODT_OFF PPC_REG_VAL(0, 0) +#define SDRAM_CODT_RK1W_ON PPC_REG_VAL(1, 1) +#define SDRAM_CODT_RK1W_OFF PPC_REG_VAL(1, 0) +#define SDRAM_CODT_RK1R_ON PPC_REG_VAL(2, 1) +#define SDRAM_CODT_RK1R_OFF PPC_REG_VAL(2, 0) +#define SDRAM_CODT_RK0W_ON PPC_REG_VAL(7, 1) +#define SDRAM_CODT_RK0W_OFF PPC_REG_VAL(7, 0) +#define SDRAM_CODT_RK0R_ON PPC_REG_VAL(8, 1) +#define SDRAM_CODT_RK0R_OFF PPC_REG_VAL(8, 0) +#define SDRAM_CODT_ODTSH_NORMAL PPC_REG_VAL(10, 0) +#define SDRAM_CODT_ODTSH_REMOVE_ONE_AT_END PPC_REG_VAL(10, 1) +#define SDRAM_CODT_ODTSH_ADD_ONE_AT_START PPC_REG_VAL(10, 2) +#define SDRAM_CODT_ODTSH_SHIFT_ONE_EARLIER PPC_REG_VAL(10, 3) +#define SDRAM_CODT_CODTZ_75OHM PPC_REG_VAL(11, 0) +#define SDRAM_CODT_CKEG_ON PPC_REG_VAL(12, 1) +#define SDRAM_CODT_CKEG_OFF PPC_REG_VAL(12, 0) +#define SDRAM_CODT_CTLG_ON PPC_REG_VAL(13, 1) +#define SDRAM_CODT_CTLG_OFF PPC_REG_VAL(13, 0) +#define SDRAM_CODT_FBDG_ON PPC_REG_VAL(14, 1) +#define SDRAM_CODT_FBDG_OFF PPC_REG_VAL(14, 0) +#define SDRAM_CODT_FBRG_ON PPC_REG_VAL(15, 1) +#define SDRAM_CODT_FBRG_OFF PPC_REG_VAL(15, 0) +#define SDRAM_CODT_CKLZ_36OHM PPC_REG_VAL(18, 1) +#define SDRAM_CODT_CKLZ_18OHM PPC_REG_VAL(18, 0) +#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK PPC_REG_VAL(26, 1) +#define SDRAM_CODT_DQS_2_5_V_DDR1 PPC_REG_VAL(26, 0) +#define SDRAM_CODT_DQS_1_8_V_DDR2 PPC_REG_VAL(26, 1) +#define SDRAM_CODT_DQS_MASK PPC_REG_VAL(27, 1) +#define SDRAM_CODT_DQS_DIFFERENTIAL PPC_REG_VAL(27, 0) +#define SDRAM_CODT_DQS_SINGLE_END PPC_REG_VAL(27, 1) +#define SDRAM_CODT_CKSE_DIFFERENTIAL PPC_REG_VAL(28, 0) +#define SDRAM_CODT_CKSE_SINGLE_END PPC_REG_VAL(28, 1) +#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END PPC_REG_VAL(29, 1) +#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END PPC_REG_VAL(30, 1) +#define SDRAM_CODT_IO_HIZ PPC_REG_VAL(31, 0) +#define SDRAM_CODT_IO_NMODE PPC_REG_VAL(31, 1) /* - * SDRAM Mode Register + * SDRAM Initialization Preload Register */ -#define SDRAM_MMODE_WR_MASK 0x00000E00 -#define SDRAM_MMODE_WR_DDR1 0x00000000 -#define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400 -#define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600 -#define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800 -#define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00 -#define SDRAM_MMODE_DCL_MASK 0x00000070 -#define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020 -#define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060 -#define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030 -#define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020 -#define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030 -#define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040 -#define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050 -#define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060 -#define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070 +#define SDRAM_INITPLR_ENABLE PPC_REG_VAL(0, 1) +#define SDRAM_INITPLR_DISABLE PPC_REG_VAL(0, 0) +#define SDRAM_INITPLR_IMWT_MASK PPC_REG_VAL(8, 0xFF) +#define SDRAM_INITPLR_IMWT_ENCODE(n) PPC_REG_VAL(8, \ + (static_cast(u32, \ + n)) \ + & 0xFF) +#define SDRAM_INITPLR_ICMD_MASK PPC_REG_VAL(12, 0x7) +#define SDRAM_INITPLR_ICMD_ENCODE(n) PPC_REG_VAL(12, \ + (static_cast(u32, \ + n)) \ + & 0x7) +#define SDRAM_INITPLR_IBA_MASK PPC_REG_VAL(15, 0x7) +#define SDRAM_INITPLR_IBA_ENCODE(n) PPC_REG_VAL(15, \ + (static_cast(u32, \ + n)) \ + & 0x7) +#define SDRAM_INITPLR_IMA_MASK PPC_REG_VAL(31, 0x7FFF) +#define SDRAM_INITPLR_IMA_ENCODE(n) PPC_REG_VAL(31, \ + (static_cast(u32, \ + n)) \ + & 0x7FFF) /* - * SDRAM Extended Mode Register + * JEDEC DDR Initialization Commands */ -#define SDRAM_MEMODE_DIC_MASK 0x00000002 -#define SDRAM_MEMODE_DIC_NORMAL 0x00000000 -#define SDRAM_MEMODE_DIC_WEAK 0x00000002 -#define SDRAM_MEMODE_DLL_MASK 0x00000001 -#define SDRAM_MEMODE_DLL_DISABLE 0x00000001 -#define SDRAM_MEMODE_DLL_ENABLE 0x00000000 -#define SDRAM_MEMODE_RTT_MASK 0x00000044 -#define SDRAM_MEMODE_RTT_DISABLED 0x00000000 -#define SDRAM_MEMODE_RTT_75OHM 0x00000004 -#define SDRAM_MEMODE_RTT_150OHM 0x00000040 -#define SDRAM_MEMODE_DQS_MASK 0x00000400 -#define SDRAM_MEMODE_DQS_DISABLE 0x00000400 -#define SDRAM_MEMODE_DQS_ENABLE 0x00000000 +#define JEDEC_CMD_NOP 7 +#define JEDEC_CMD_PRECHARGE 2 +#define JEDEC_CMD_REFRESH 1 +#define JEDEC_CMD_EMR 0 +#define JEDEC_CMD_READ 5 +#define JEDEC_CMD_WRITE 4 + +/* + * JEDEC Precharge Command Memory Address Arguments + */ +#define JEDEC_MA_PRECHARGE_ONE (0 << 10) +#define JEDEC_MA_PRECHARGE_ALL (1 << 10) + +/* + * JEDEC DDR EMR Command Bank Address Arguments + */ +#define JEDEC_BA_MR 0 +#define JEDEC_BA_EMR 1 +#define JEDEC_BA_EMR2 2 +#define JEDEC_BA_EMR3 3 + +/* + * JEDEC DDR Mode Register + */ +#define JEDEC_MA_MR_PDMODE_FAST_EXIT (0 << 12) +#define JEDEC_MA_MR_PDMODE_SLOW_EXIT (1 << 12) +#define JEDEC_MA_MR_WR_MASK (0x7 << 9) +#define JEDEC_MA_MR_WR_DDR1 (0x0 << 9) +#define JEDEC_MA_MR_WR_DDR2_2_CYC (0x1 << 9) +#define JEDEC_MA_MR_WR_DDR2_3_CYC (0x2 << 9) +#define JEDEC_MA_MR_WR_DDR2_4_CYC (0x3 << 9) +#define JEDEC_MA_MR_WR_DDR2_5_CYC (0x4 << 9) +#define JEDEC_MA_MR_WR_DDR2_6_CYC (0x5 << 9) +#define JEDEC_MA_MR_DLL_RESET (1 << 8) +#define JEDEC_MA_MR_MODE_NORMAL (0 << 8) +#define JEDEC_MA_MR_MODE_TEST (1 << 8) +#define JEDEC_MA_MR_CL_MASK (0x7 << 4) +#define JEDEC_MA_MR_CL_DDR1_2_0_CLK (0x2 << 4) +#define JEDEC_MA_MR_CL_DDR1_2_5_CLK (0x6 << 4) +#define JEDEC_MA_MR_CL_DDR1_3_0_CLK (0x3 << 4) +#define JEDEC_MA_MR_CL_DDR2_2_0_CLK (0x2 << 4) +#define JEDEC_MA_MR_CL_DDR2_3_0_CLK (0x3 << 4) +#define JEDEC_MA_MR_CL_DDR2_4_0_CLK (0x4 << 4) +#define JEDEC_MA_MR_CL_DDR2_5_0_CLK (0x5 << 4) +#define JEDEC_MA_MR_CL_DDR2_6_0_CLK (0x6 << 4) +#define JEDEC_MA_MR_CL_DDR2_7_0_CLK (0x7 << 4) +#define JEDEC_MA_MR_BTYP_SEQUENTIAL (0 << 3) +#define JEDEC_MA_MR_BTYP_INTERLEAVED (1 << 3) +#define JEDEC_MA_MR_BLEN_MASK (0x7 << 0) +#define JEDEC_MA_MR_BLEN_4 (2 << 0) +#define JEDEC_MA_MR_BLEN_8 (3 << 0) + +/* + * JEDEC DDR Extended Mode Register + */ +#define JEDEC_MA_EMR_OUTPUT_MASK (1 << 12) +#define JEDEC_MA_EMR_OUTPUT_ENABLE (0 << 12) +#define JEDEC_MA_EMR_OUTPUT_DISABLE (1 << 12) +#define JEDEC_MA_EMR_RQDS_MASK (1 << 11) +#define JEDEC_MA_EMR_RDQS_DISABLE (0 << 11) +#define JEDEC_MA_EMR_RDQS_ENABLE (1 << 11) +#define JEDEC_MA_EMR_DQS_MASK (1 << 10) +#define JEDEC_MA_EMR_DQS_DISABLE (1 << 10) +#define JEDEC_MA_EMR_DQS_ENABLE (0 << 10) +#define JEDEC_MA_EMR_OCD_MASK (0x7 << 7) +#define JEDEC_MA_EMR_OCD_EXIT (0 << 7) +#define JEDEC_MA_EMR_OCD_ENTER (7 << 7) +#define JEDEC_MA_EMR_AL_DDR1_0_CYC (0 << 3) +#define JEDEC_MA_EMR_AL_DDR2_1_CYC (1 << 3) +#define JEDEC_MA_EMR_AL_DDR2_2_CYC (2 << 3) +#define JEDEC_MA_EMR_AL_DDR2_3_CYC (3 << 3) +#define JEDEC_MA_EMR_AL_DDR2_4_CYC (4 << 3) +#define JEDEC_MA_EMR_RTT_MASK (0x11 << 2) +#define JEDEC_MA_EMR_RTT_DISABLED (0x00 << 2) +#define JEDEC_MA_EMR_RTT_75OHM (0x01 << 2) +#define JEDEC_MA_EMR_RTT_150OHM (0x10 << 2) +#define JEDEC_MA_EMR_RTT_50OHM (0x11 << 2) +#define JEDEC_MA_EMR_ODS_MASK (1 << 1) +#define JEDEC_MA_EMR_ODS_NORMAL (0 << 1) +#define JEDEC_MA_EMR_ODS_WEAK (1 << 1) +#define JEDEC_MA_EMR_DLL_MASK (1 << 0) +#define JEDEC_MA_EMR_DLL_ENABLE (0 << 0) +#define JEDEC_MA_EMR_DLL_DISABLE (1 << 0) + +/* + * JEDEC DDR Extended Mode Register 2 + */ +#define JEDEC_MA_EMR2_TEMP_COMMERCIAL (0 << 7) +#define JEDEC_MA_EMR2_TEMP_INDUSTRIAL (1 << 7) + +/* + * SDRAM Mode Register (Corresponds 1:1 w/ JEDEC Mode Register) + */ +#define SDRAM_MMODE_WR_MASK JEDEC_MA_MR_WR_MASK +#define SDRAM_MMODE_WR_DDR1 JEDEC_MA_MR_WR_DDR1 +#define SDRAM_MMODE_WR_DDR2_2_CYC JEDEC_MA_MR_WR_DDR2_2_CYC +#define SDRAM_MMODE_WR_DDR2_3_CYC JEDEC_MA_MR_WR_DDR2_3_CYC +#define SDRAM_MMODE_WR_DDR2_4_CYC JEDEC_MA_MR_WR_DDR2_4_CYC +#define SDRAM_MMODE_WR_DDR2_5_CYC JEDEC_MA_MR_WR_DDR2_5_CYC +#define SDRAM_MMODE_WR_DDR2_6_CYC JEDEC_MA_MR_WR_DDR2_6_CYC +#define SDRAM_MMODE_DCL_MASK JEDEC_MA_MR_CL_MASK +#define SDRAM_MMODE_DCL_DDR1_2_0_CLK JEDEC_MA_MR_CL_DDR1_2_0_CLK +#define SDRAM_MMODE_DCL_DDR1_2_5_CLK JEDEC_MA_MR_CL_DDR1_2_5_CLK +#define SDRAM_MMODE_DCL_DDR1_3_0_CLK JEDEC_MA_MR_CL_DDR1_3_0_CLK +#define SDRAM_MMODE_DCL_DDR2_2_0_CLK JEDEC_MA_MR_CL_DDR2_2_0_CLK +#define SDRAM_MMODE_DCL_DDR2_3_0_CLK JEDEC_MA_MR_CL_DDR2_3_0_CLK +#define SDRAM_MMODE_DCL_DDR2_4_0_CLK JEDEC_MA_MR_CL_DDR2_4_0_CLK +#define SDRAM_MMODE_DCL_DDR2_5_0_CLK JEDEC_MA_MR_CL_DDR2_5_0_CLK +#define SDRAM_MMODE_DCL_DDR2_6_0_CLK JEDEC_MA_MR_CL_DDR2_6_0_CLK +#define SDRAM_MMODE_DCL_DDR2_7_0_CLK JEDEC_MA_MR_CL_DDR2_7_0_CLK +#define SDRAM_MMODE_BTYP_SEQUENTIAL JEDEC_MA_MR_BTYP_SEQUENTIAL +#define SDRAM_MMODE_BTYP_INTERLEAVED JEDEC_MA_MR_BTYP_INTERLEAVED +#define SDRAM_MMODE_BLEN_MASK JEDEC_MA_MR_BLEN_MASK +#define SDRAM_MMODE_BLEN_4 JEDEC_MA_MR_BLEN_4 +#define SDRAM_MMODE_BLEN_8 JEDEC_MA_MR_BLEN_8 + +/* + * SDRAM Extended Mode Register (Corresponds 1:1 w/ JEDEC Extended + * Mode Register) + */ +#define SDRAM_MEMODE_QOFF_MASK JEDEC_MA_EMR_OUTPUT_MASK +#define SDRAM_MEMODE_QOFF_DISABLE JEDEC_MA_EMR_OUTPUT_DISABLE +#define SDRAM_MEMODE_QOFF_ENABLE JEDEC_MA_EMR_OUTPUT_ENABLE +#define SDRAM_MEMODE_RDQS_MASK JEDEC_MA_EMR_RQDS_MASK +#define SDRAM_MEMODE_RDQS_DISABLE JEDEC_MA_EMR_RDQS_DISABLE +#define SDRAM_MEMODE_RDQS_ENABLE JEDEC_MA_EMR_RDQS_ENABLE +#define SDRAM_MEMODE_DQS_MASK JEDEC_MA_EMR_DQS_MASK +#define SDRAM_MEMODE_DQS_DISABLE JEDEC_MA_EMR_DQS_DISABLE +#define SDRAM_MEMODE_DQS_ENABLE JEDEC_MA_EMR_DQS_ENABLE +#define SDRAM_MEMODE_AL_DDR1_0_CYC JEDEC_MA_EMR_AL_DDR1_0_CYC +#define SDRAM_MEMODE_AL_DDR2_1_CYC JEDEC_MA_EMR_AL_DDR2_1_CYC +#define SDRAM_MEMODE_AL_DDR2_2_CYC JEDEC_MA_EMR_AL_DDR2_2_CYC +#define SDRAM_MEMODE_AL_DDR2_3_CYC JEDEC_MA_EMR_AL_DDR2_3_CYC +#define SDRAM_MEMODE_AL_DDR2_4_CYC JEDEC_MA_EMR_AL_DDR2_4_CYC +#define SDRAM_MEMODE_RTT_MASK JEDEC_MA_EMR_RTT_MASK +#define SDRAM_MEMODE_RTT_DISABLED JEDEC_MA_EMR_RTT_DISABLED +#define SDRAM_MEMODE_RTT_75OHM JEDEC_MA_EMR_RTT_75OHM +#define SDRAM_MEMODE_RTT_150OHM JEDEC_MA_EMR_RTT_150OHM +#define SDRAM_MEMODE_RTT_50OHM JEDEC_MA_EMR_RTT_50OHM +#define SDRAM_MEMODE_DIC_MASK JEDEC_MA_EMR_ODS_MASK +#define SDRAM_MEMODE_DIC_NORMAL JEDEC_MA_EMR_ODS_NORMAL +#define SDRAM_MEMODE_DIC_WEAK JEDEC_MA_EMR_ODS_WEAK +#define SDRAM_MEMODE_DLL_MASK JEDEC_MA_EMR_DLL_MASK +#define SDRAM_MEMODE_DLL_DISABLE JEDEC_MA_EMR_DLL_DISABLE +#define SDRAM_MEMODE_DLL_ENABLE JEDEC_MA_EMR_DLL_ENABLE /* * SDRAM Clock Timing Register @@ -684,6 +898,24 @@ #define SDRAM_SDTR3_RFC_ENCODE(n) ((((u32)(n))&0x3F)<<0) /* + * ECC Error Status + */ +#define SDRAM_ECCES_MASK PPC_REG_VAL(21, 0x3FFFFF) +#define SDRAM_ECCES_BNCE_MASK PPC_REG_VAL(15, 0xFFFF) +#define SDRAM_ECCES_BNCE_ENCODE(lane) PPC_REG_VAL(((lane) & 0xF), 1) +#define SDRAM_ECCES_CKBER_MASK PPC_REG_VAL(17, 0x3) +#define SDRAM_ECCES_CKBER_NONE PPC_REG_VAL(17, 0) +#define SDRAM_ECCES_CKBER_16_ECC_0_3 PPC_REG_VAL(17, 2) +#define SDRAM_ECCES_CKBER_32_ECC_0_3 PPC_REG_VAL(17, 1) +#define SDRAM_ECCES_CKBER_32_ECC_4_8 PPC_REG_VAL(17, 2) +#define SDRAM_ECCES_CKBER_32_ECC_0_8 PPC_REG_VAL(17, 3) +#define SDRAM_ECCES_CE PPC_REG_VAL(18, 1) +#define SDRAM_ECCES_UE PPC_REG_VAL(19, 1) +#define SDRAM_ECCES_BKNER_MASK PPC_REG_VAL(21, 0x3) +#define SDRAM_ECCES_BK0ER PPC_REG_VAL(20, 1) +#define SDRAM_ECCES_BK1ER PPC_REG_VAL(21, 1) + +/* * Memory Bank 0-1 configuration */ #define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */ diff --git a/include/asm-ppc/ppc4xx-uic.h b/include/asm-ppc/ppc4xx-uic.h new file mode 100644 index 0000000..c908d42 --- /dev/null +++ b/include/asm-ppc/ppc4xx-uic.h @@ -0,0 +1,316 @@ +/* + * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> + * + * (C) Copyright 2008 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PPC4xx_UIC_H_ +#define _PPC4xx_UIC_H_ + +/* + * Define the number of UIC's + */ +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) +#define UIC_MAX 4 +#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) +#define UIC_MAX 3 +#elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \ + defined(CONFIG_440EP) || defined(CONFIG_440GR) +#define UIC_MAX 2 +#else +#define UIC_MAX 1 +#endif + +#define IRQ_MAX UIC_MAX * 32 + +/* + * UIC register + */ +#define UIC_SR 0x0 /* UIC status */ +#define UIC_ER 0x2 /* UIC enable */ +#define UIC_CR 0x3 /* UIC critical */ +#define UIC_PR 0x4 /* UIC polarity */ +#define UIC_TR 0x5 /* UIC triggering */ +#define UIC_MSR 0x6 /* UIC masked status */ +#define UIC_VR 0x7 /* UIC vector */ +#define UIC_VCR 0x8 /* UIC vector configuration */ + +/* + * On 440GX we use the UICB0 as UIC0. Its the root UIC where all other UIC's + * are cascaded on. With this trick we can use the common UIC code for 440GX + * too. + */ +#if defined(CONFIG_440GX) +#define UIC0_DCR_BASE 0x200 +#define UIC1_DCR_BASE 0xc0 +#define UIC2_DCR_BASE 0xd0 +#define UIC3_DCR_BASE 0x210 +#else +#define UIC0_DCR_BASE 0xc0 +#define UIC1_DCR_BASE 0xd0 +#define UIC2_DCR_BASE 0xe0 +#define UIC3_DCR_BASE 0xf0 +#endif + +#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */ +#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */ +#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */ +#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */ +#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */ +#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */ +#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */ +#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */ + +#define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */ +#define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */ +#define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */ +#define uic1pr (UIC1_DCR_BASE+0x4) /* UIC1 polarity */ +#define uic1tr (UIC1_DCR_BASE+0x5) /* UIC1 triggering */ +#define uic1msr (UIC1_DCR_BASE+0x6) /* UIC1 masked status */ +#define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */ +#define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */ + +#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */ +#define uic2srs (UIC2_DCR_BASE+0x1) /* UIC2 status-Read Set */ +#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */ +#define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */ +#define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */ +#define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */ +#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */ +#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */ +#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */ + +#define uic3sr (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */ +#define uic3srs (UIC3_DCR_BASE+0x1) /* UIC3 status-Read Set */ +#define uic3er (UIC3_DCR_BASE+0x2) /* UIC3 enable */ +#define uic3cr (UIC3_DCR_BASE+0x3) /* UIC3 critical */ +#define uic3pr (UIC3_DCR_BASE+0x4) /* UIC3 polarity */ +#define uic3tr (UIC3_DCR_BASE+0x5) /* UIC3 triggering */ +#define uic3msr (UIC3_DCR_BASE+0x6) /* UIC3 masked status */ +#define uic3vr (UIC3_DCR_BASE+0x7) /* UIC3 vector */ +#define uic3vcr (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */ + +/* The following is for compatibility with 405 code */ +#define uicsr uic0sr +#define uicer uic0er +#define uiccr uic0cr +#define uicpr uic0pr +#define uictr uic0tr +#define uicmsr uic0msr +#define uicvr uic0vr +#define uicvcr uic0vcr + +/* + * Now the interrupt vector definitions. They are different for most of + * the 4xx variants, so we need some more #ifdef's here. No mask + * definitions anymore here. For this please use the UIC_MASK macro below. + * + * Note: Please only define the interrupts really used in U-Boot here. + * Those are the cascading and EMAC/MAL related interrupt. + */ + +#if defined(CONFIG_405EP) || defined(CONFIG_405GP) +#define VECNUM_MAL_SERR 10 +#define VECNUM_MAL_TXEOB 11 +#define VECNUM_MAL_RXEOB 12 +#define VECNUM_MAL_TXDE 13 +#define VECNUM_MAL_RXDE 14 +#define VECNUM_ETH0 15 +#define VECNUM_ETH1_OFFS 2 +#define VECNUM_EIRQ6 29 +#endif /* defined(CONFIG_405EP) */ + +#if defined(CONFIG_405EZ) +#define VECNUM_USBDEV 15 +#define VECNUM_ETH0 16 +#define VECNUM_MAL_SERR 18 +#define VECNUM_MAL_TXDE 18 +#define VECNUM_MAL_RXDE 18 +#define VECNUM_MAL_TXEOB 19 +#define VECNUM_MAL_RXEOB 21 +#endif /* CONFIG_405EX */ + +#if defined(CONFIG_405EX) +/* UIC 0 */ +#define VECNUM_MAL_TXEOB 10 +#define VECNUM_MAL_RXEOB 11 +#define VECNUM_ETH0 24 +#define VECNUM_ETH1_OFFS 1 +#define VECNUM_UIC2NCI 28 +#define VECNUM_UIC2CI 29 +#define VECNUM_UIC1NCI 30 +#define VECNUM_UIC1CI 31 + +/* UIC 1 */ +#define VECNUM_MAL_SERR (32 + 0) +#define VECNUM_MAL_TXDE (32 + 1) +#define VECNUM_MAL_RXDE (32 + 2) +#endif /* CONFIG_405EX */ + +#if defined(CONFIG_440GP) || \ + defined(CONFIG_440EP) || defined(CONFIG_440GR) +/* UIC 0 */ +#define VECNUM_MAL_TXEOB 10 +#define VECNUM_MAL_RXEOB 11 +#define VECNUM_UIC1NCI 30 +#define VECNUM_UIC1CI 31 + +/* UIC 1 */ +#define VECNUM_MAL_SERR (32 + 0) +#define VECNUM_MAL_TXDE (32 + 1) +#define VECNUM_MAL_RXDE (32 + 2) +#define VECNUM_USBDEV (32 + 23) +#define VECNUM_ETH0 (32 + 28) +#define VECNUM_ETH1_OFFS 2 +#endif /* CONFIG_440GP */ + +#if defined(CONFIG_440GX) +/* UICB 0 (440GX only) */ +/* + * All those defines below are off-by-one, so that the common UIC code + * can be used. So VECNUM_UIC1CI refers to VECNUM_UIC0CI etc. + */ +#define VECNUM_UIC1CI 0 +#define VECNUM_UIC1NCI 1 +#define VECNUM_UIC2CI 2 +#define VECNUM_UIC2NCI 3 +#define VECNUM_UIC3CI 4 +#define VECNUM_UIC3NCI 5 + +/* UIC 0, used as UIC1 on 440GX because of UICB0 */ +#define VECNUM_MAL_TXEOB (32 + 10) +#define VECNUM_MAL_RXEOB (32 + 11) + +/* UIC 1, used as UIC2 on 440GX because of UICB0 */ +#define VECNUM_MAL_SERR (64 + 0) +#define VECNUM_MAL_TXDE (64 + 1) +#define VECNUM_MAL_RXDE (64 + 2) +#define VECNUM_ETH0 (64 + 28) +#define VECNUM_ETH1_OFFS 2 +#endif /* CONFIG_440GX */ + +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +/* UIC 0 */ +#define VECNUM_MAL_TXEOB 10 +#define VECNUM_MAL_RXEOB 11 +#define VECNUM_USBDEV 20 +#define VECNUM_ETH0 24 +#define VECNUM_ETH1_OFFS 1 +#define VECNUM_UIC2NCI 28 +#define VECNUM_UIC2CI 29 +#define VECNUM_UIC1NCI 30 +#define VECNUM_UIC1CI 31 + +/* UIC 1 */ +#define VECNUM_MAL_SERR (32 + 0) +#define VECNUM_MAL_TXDE (32 + 1) +#define VECNUM_MAL_RXDE (32 + 2) + +/* UIC 2 */ +#define VECNUM_EIRQ2 (64 + 3) +#endif /* CONFIG_440EPX */ + +#if defined(CONFIG_440SP) +/* UIC 0 */ +#define VECNUM_UIC1NCI 30 +#define VECNUM_UIC1CI 31 + +/* UIC 1 */ +#define VECNUM_MAL_SERR (32 + 1) +#define VECNUM_MAL_TXDE (32 + 2) +#define VECNUM_MAL_RXDE (32 + 3) +#define VECNUM_MAL_TXEOB (32 + 6) +#define VECNUM_MAL_RXEOB (32 + 7) +#define VECNUM_ETH0 (32 + 28) +#endif /* CONFIG_440SP */ + +#if defined(CONFIG_440SPE) +/* UIC 0 */ +#define VECNUM_UIC2NCI 10 +#define VECNUM_UIC2CI 11 +#define VECNUM_UIC3NCI 16 +#define VECNUM_UIC3CI 17 +#define VECNUM_UIC1NCI 30 +#define VECNUM_UIC1CI 31 + +/* UIC 1 */ +#define VECNUM_MAL_SERR (32 + 1) +#define VECNUM_MAL_TXDE (32 + 2) +#define VECNUM_MAL_RXDE (32 + 3) +#define VECNUM_MAL_TXEOB (32 + 6) +#define VECNUM_MAL_RXEOB (32 + 7) +#define VECNUM_ETH0 (32 + 28) +#endif /* CONFIG_440SPE */ + +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +/* UIC 0 */ +#define VECNUM_UIC2NCI 10 +#define VECNUM_UIC2CI 11 +#define VECNUM_UIC3NCI 16 +#define VECNUM_UIC3CI 17 +#define VECNUM_UIC1NCI 30 +#define VECNUM_UIC1CI 31 + +/* UIC 2 */ +#define VECNUM_MAL_SERR (64 + 3) +#define VECNUM_MAL_TXDE (64 + 4) +#define VECNUM_MAL_RXDE (64 + 5) +#define VECNUM_MAL_TXEOB (64 + 6) +#define VECNUM_MAL_RXEOB (64 + 7) +#define VECNUM_ETH0 (64 + 16) +#define VECNUM_ETH1_OFFS 1 +#endif /* CONFIG_460EX */ + +#if defined(CONFIG_460SX) +/* UIC 0 */ +#define VECNUM_UIC2NCI 10 +#define VECNUM_UIC2CI 11 +#define VECNUM_UIC3NCI 16 +#define VECNUM_UIC3CI 17 +#define VECNUM_ETH0 19 +#define VECNUM_ETH1_OFFS 1 +#define VECNUM_UIC1NCI 30 +#define VECNUM_UIC1CI 31 + +/* UIC 1 */ +#define VECNUM_MAL_SERR (32 + 1) +#define VECNUM_MAL_TXDE (32 + 2) +#define VECNUM_MAL_RXDE (32 + 3) +#define VECNUM_MAL_TXEOB (32 + 6) +#define VECNUM_MAL_RXEOB (32 + 7) +#endif /* CONFIG_460EX */ + +#if !defined(VECNUM_ETH1_OFFS) +#define VECNUM_ETH1_OFFS 1 +#endif + +/* + * Mask definitions (used for example in 4xx_enet.c) + */ +#define UIC_MASK(vec) (0x80000000 >> ((vec) & 0x1f)) +/* UIC_NR won't work for 440GX because of its specific UIC DCR addresses */ +#define UIC_NR(vec) ((vec) >> 5) + +#endif /* _PPC4xx_UIC_H_ */ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index e617868..dce4717 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -830,6 +830,10 @@ #define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */ #define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */ #define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */ +#define PVR_460SX_RA 0x13541800 /* 460SX rev A */ +#define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */ +#define PVR_460GX_RA 0x13541802 /* 460GX rev A */ +#define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */ #define PVR_601 0x00010000 #define PVR_602 0x00050000 #define PVR_603 0x00030000 @@ -855,6 +859,8 @@ #define PVR_86xx 0x80040000 #define PVR_86xx_REV1 (PVR_86xx | 0x0010) +#define PVR_VIRTEX5 0x7ff21912 + /* * For the 8xx processors, all of them report the same PVR family for * the PowerPC core. The various versions of these processors must be diff --git a/include/asm-ppc/xilinx_irq.h b/include/asm-ppc/xilinx_irq.h new file mode 100644 index 0000000..61171c2 --- /dev/null +++ b/include/asm-ppc/xilinx_irq.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ +#ifndef XILINX_IRQ_H +#define XILINX_IRQ_H + +#define intc XPAR_INTC_0_BASEADDR +#define ISR (intc + (0 * 4)) /* Interrupt Status Register */ +#define IPR (intc + (1 * 4)) /* Interrupt Pending Register */ +#define IER (intc + (2 * 4)) /* Interrupt Enable Register */ +#define IAR (intc + (3 * 4)) /* Interrupt Acknowledge Register */ +#define SIE (intc + (4 * 4)) /* Set Interrupt Enable bits */ +#define CIE (intc + (5 * 4)) /* Clear Interrupt Enable bits */ +#define IVR (intc + (6 * 4)) /* Interrupt Vector Register */ +#define MER (intc + (7 * 4)) /* Master Enable Register */ + +#define IRQ_MASK(irq) (1 << (irq & 0x1f)) + +#define IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS + +#endif diff --git a/include/common.h b/include/common.h index 2fcb1fd..06ed278 100644 --- a/include/common.h +++ b/include/common.h @@ -119,11 +119,13 @@ typedef volatile unsigned char vu_char; #define debugX(level,fmt,args...) #endif /* DEBUG */ +#ifndef BUG #define BUG() do { \ printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \ panic("BUG!"); \ } while (0) #define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0) +#endif /* BUG */ typedef void (interrupt_handler_t)(void *); diff --git a/include/configs/APC405.h b/include/configs/APC405.h index 2f266a2..6ee0a36 100644 --- a/include/configs/APC405.h +++ b/include/configs/APC405.h @@ -269,7 +269,7 @@ extern int flash_banks; #define CFG_FLASH_BASE 0xFE000000 #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ #define CFG_MAX_FLASH_BANKS flash_banks /* max num of flash banks */ /* updated in board_early_init_r */ diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h index f05c1d5..6aa881c 100644 --- a/include/configs/ATUM8548.h +++ b/include/configs/ATUM8548.h @@ -182,7 +182,7 @@ #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ -#define CFG_FLASH_CFI_DRIVER 1 +#define CONFIG_FLASH_CFI_DRIVER 1 #define CFG_FLASH_CFI 1 #define CFG_FLASH_EMPTY_INFO diff --git a/include/configs/Adder.h b/include/configs/Adder.h index cefdd29..07a9f4e 100644 --- a/include/configs/Adder.h +++ b/include/configs/Adder.h @@ -143,7 +143,7 @@ */ #define CFG_FLASH_BASE 0xFE000000 #define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ #define CFG_MAX_FLASH_SECT 128 /* Max num of sects on one chip */ diff --git a/include/configs/BAB7xx.h b/include/configs/BAB7xx.h index 8ec70aa..26a1a2d 100644 --- a/include/configs/BAB7xx.h +++ b/include/configs/BAB7xx.h @@ -338,7 +338,7 @@ extern unsigned char scsi_sym53c8xx_ccf; /* * Winbond Configuration */ -#define CFG_WINBOND_83C553 1 /* has a winbond bridge */ +#define CONFIG_WINBOND_83C553 1 /* has a winbond bridge */ #define CFG_USE_WINBOND_IDE 0 /* use winbond 83c553 internal ide */ #define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /* pci-isa bridge config addr */ #define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /* ide config addr */ @@ -346,7 +346,7 @@ extern unsigned char scsi_sym53c8xx_ccf; /* * NS87308 Configuration */ -#define CFG_NS87308 /* Nat Semi super-io cntr on ISA bus */ +#define CONFIG_NS87308 /* Nat Semi super-io cntr on ISA bus */ #define CFG_NS87308_BADDR_10 1 #define CFG_NS87308_DEVS (CFG_NS87308_UART1 | \ CFG_NS87308_UART2 | \ diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h index b7574bf..3c5d038 100644 --- a/include/configs/BC3450.h +++ b/include/configs/BC3450.h @@ -328,7 +328,7 @@ /* use CFI flash driver if no module variant is spezified */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */ diff --git a/include/configs/BMW.h b/include/configs/BMW.h index bb7856f..11d19c6 100644 --- a/include/configs/BMW.h +++ b/include/configs/BMW.h @@ -86,7 +86,7 @@ /* CONFIG_CMD_DOC required legacy NAND support */ -#define CFG_NAND_LEGACY +#define CONFIG_NAND_LEGACY #if 0 #define CONFIG_PCI 1 diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h index 89edbde..03756c3 100644 --- a/include/configs/CPCI750.h +++ b/include/configs/CPCI750.h @@ -294,7 +294,7 @@ * FLASH related *----------------------------------------------------------------------*/ -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ #define CFG_FLASH_PROTECTION 1 /* use hardware protection */ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h index 3879d9b..d325c4d 100644 --- a/include/configs/CPU87.h +++ b/include/configs/CPU87.h @@ -191,7 +191,7 @@ #endif -#define CFG_NAND_LEGACY +#define CONFIG_NAND_LEGACY /* * Miscellaneous configurable options diff --git a/include/configs/DU440.h b/include/configs/DU440.h index 64c9ac0..c757523 100644 --- a/include/configs/DU440.h +++ b/include/configs/DU440.h @@ -119,7 +119,7 @@ * FLASH related */ #define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } diff --git a/include/configs/EP88x.h b/include/configs/EP88x.h index 7824b90..5f1743b 100644 --- a/include/configs/EP88x.h +++ b/include/configs/EP88x.h @@ -138,7 +138,7 @@ */ #define CFG_FLASH_BASE 0xFC000000 #define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ #define CFG_MAX_FLASH_SECT 512 /* Max num of sects on one chip */ diff --git a/include/configs/FPS850L.h b/include/configs/FPS850L.h index e4b68ab..e694a02 100644 --- a/include/configs/FPS850L.h +++ b/include/configs/FPS850L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000 + * (C) Copyright 2000-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -65,10 +65,17 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/fps850L/uImage\0" \ + "hostname=FPS850L\0" \ + "bootfile=FPS850L/uImage\0" \ "fdt_addr=40040000\0" \ "kernel_addr=40060000\0" \ "ramdisk_addr=40200000\0" \ + "u-boot=FPS850L/u-image.bin\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=prot off 40000000 +${filesize};" \ + "era 40000000 +${filesize};" \ + "cp.b 200000 40000000 ${filesize};" \ + "sete filesize;save\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -106,10 +113,14 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP +#define CONFIG_NETCONSOLE + + /* * Miscellaneous configurable options */ @@ -180,11 +191,15 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ @@ -194,6 +209,20 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + +/*----------------------------------------------------------------------- + * Dynamic MTD partition support + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" + +#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ + "128k(dtb)," \ + "1664k(kernel)," \ + "2m(rootfs)," \ + "4m(data)" + /*----------------------------------------------------------------------- * Hardware Information Block */ diff --git a/include/configs/FPS860L.h b/include/configs/FPS860L.h index ed612c3..84b6824 100644 --- a/include/configs/FPS860L.h +++ b/include/configs/FPS860L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2005 + * (C) Copyright 2000-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -65,10 +65,17 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/fps850L/uImage\0" \ + "hostname=FPS860L\0" \ + "bootfile=FPS860L/uImage\0" \ "fdt_addr=40040000\0" \ "kernel_addr=40060000\0" \ "ramdisk_addr=40200000\0" \ + "u-boot=FPS860L/u-image.bin\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=prot off 40000000 +${filesize};" \ + "era 40000000 +${filesize};" \ + "cp.b 200000 40000000 ${filesize};" \ + "sete filesize;save\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -106,10 +113,14 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP +#define CONFIG_NETCONSOLE + + /* * Miscellaneous configurable options */ @@ -180,11 +191,15 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ @@ -194,6 +209,20 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + +/*----------------------------------------------------------------------- + * Dynamic MTD partition support + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" + +#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ + "128k(dtb)," \ + "1664k(kernel)," \ + "2m(rootfs)," \ + "4m(data)" + /*----------------------------------------------------------------------- * Hardware Information Block */ @@ -306,9 +335,11 @@ #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ - OR_SCY_5_CLK | OR_EHTR) +/* + * FLASH timing: + */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ + OR_SCY_3_CLK | OR_EHTR | OR_BI) #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) @@ -337,12 +368,42 @@ /* * Memory Periodic Timer Prescaler + * + * The Divider for PTA (refresh timer) configuration is based on an + * example SDRAM configuration (64 MBit, one bank). The adjustment to + * the number of chip selects (NCS) and the actually needed refresh + * rate is done by setting MPTPR. + * + * PTA is calculated from + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) + * + * gclk CPU clock (not bus clock!) + * Trefresh Refresh cycle * 4 (four word bursts used) + * + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + * -------------------------------------------- + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 + * + * 50 MHz => 50.000.000 / Divider = 98 + * 66 Mhz => 66.000.000 / Divider = 129 + * 80 Mhz => 80.000.000 / Divider = 156 */ -/* periodic timer for refresh */ -#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) +#define CFG_MAMR_PTA 98 -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ +/* + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + */ #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ @@ -372,4 +433,6 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_SCC1_ENET + #endif /* __CONFIG_H */ diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h index 037b115..422ed32 100644 --- a/include/configs/GEN860T.h +++ b/include/configs/GEN860T.h @@ -280,7 +280,7 @@ #define CFG_FPGA_PROG_FEEDBACK -#define CFG_NAND_LEGACY +#define CONFIG_NAND_LEGACY /* * Verbose help from command monitor. diff --git a/include/configs/HH405.h b/include/configs/HH405.h index 8ea1ac3..9bcbfe3 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -407,7 +407,7 @@ /* * define UIC_EXT0 ... UIC_EXT6 if external interrupt is active high */ -#define CFG_UIC0_POLARITY (0xFFFFFF80 | UIC_EXT6) +#define CFG_UIC0_POLARITY (0xFFFFFF80 | UIC_MASK(VECNUM_EIRQ6)) /*----------------------------------------------------------------------- * FPGA stuff diff --git a/include/configs/HIDDEN_DRAGON.h b/include/configs/HIDDEN_DRAGON.h index 26dd954..5deb84d 100644 --- a/include/configs/HIDDEN_DRAGON.h +++ b/include/configs/HIDDEN_DRAGON.h @@ -201,7 +201,7 @@ */ -#define CFG_WINBOND_83C553 1 /*has a winbond bridge */ +#define CONFIG_WINBOND_83C553 1 /*has a winbond bridge */ #define CFG_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */ #define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */ #define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */ @@ -214,7 +214,7 @@ /* * NS87308 Configuration */ -#define CFG_NS87308 /* Nat Semi super-io controller on ISA bus */ +#define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */ #define CFG_NS87308_BADDR_10 1 diff --git a/include/configs/HMI10.h b/include/configs/HMI10.h index 081ca6c..a7e7c57 100644 --- a/include/configs/HMI10.h +++ b/include/configs/HMI10.h @@ -227,7 +227,7 @@ /* use CFI flash driver */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_USE_BUFFER_WRITE 1 diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h index f7d4499..029bb99 100644 --- a/include/configs/IDS8247.h +++ b/include/configs/IDS8247.h @@ -227,7 +227,7 @@ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ #define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_FLASH_BANKS_LIST { 0xFF800000 } #define CFG_MAX_FLASH_BANKS_DETECT 1 /* What should the base address of the main FLASH be and how big is @@ -262,7 +262,7 @@ */ #if defined(CONFIG_CMD_NAND) -#define CFG_NAND_LEGACY +#define CONFIG_NAND_LEGACY #define CFG_NAND0_BASE 0xE1000000 #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ diff --git a/include/configs/ISPAN.h b/include/configs/ISPAN.h index 760f7cc..27e46a4 100644 --- a/include/configs/ISPAN.h +++ b/include/configs/ISPAN.h @@ -180,7 +180,7 @@ */ #define CFG_FLASH_BASE 0xFE000000 #define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_MAX_FLASH_BANKS 1 /* Max num of memory banks */ #define CFG_MAX_FLASH_SECT 142 /* Max num of sects on one chip */ diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index 3a347ea..0b90946 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -246,7 +246,7 @@ #undef CONFIG_FLASH_16BIT /* Flash is 8-bit */ #if defined(CONFIG_LITE5200B) -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #define CFG_FLASH_BANKS_LIST {CFG_CS1_START,CFG_CS0_START} #endif diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h index 3d28913..8713b02 100644 --- a/include/configs/M52277EVB.h +++ b/include/configs/M52277EVB.h @@ -207,7 +207,7 @@ #define CFG_FLASH_CFI #ifdef CFG_FLASH_CFI -# define CFG_FLASH_CFI_DRIVER 1 +# define CONFIG_FLASH_CFI_DRIVER 1 # define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */ # define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT # define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index 8af1c52..e836132 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -200,7 +200,7 @@ */ #define CFG_FLASH_CFI #ifdef CFG_FLASH_CFI -# define CFG_FLASH_CFI_DRIVER 1 +# define CONFIG_FLASH_CFI_DRIVER 1 # define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */ #ifdef NORFLASH_PS32BIT # define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index de7ea42..c2f5dd9 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -150,7 +150,7 @@ #define CFG_FLASH_CFI #ifdef CFG_FLASH_CFI -# define CFG_FLASH_CFI_DRIVER 1 +# define CONFIG_FLASH_CFI_DRIVER 1 # define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */ # define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT # define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h index f5e1b64..9dbd129 100644 --- a/include/configs/M5253EVBE.h +++ b/include/configs/M5253EVBE.h @@ -172,7 +172,7 @@ #define CFG_FLASH_ERASE_TOUT 1000 #define CFG_FLASH_CFI 1 -#define CFG_FLASH_CFI_DRIVER 1 +#define CONFIG_FLASH_CFI_DRIVER 1 #define CFG_FLASH_SIZE 0x200000 #define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h index a6fac4c..12f9783 100644 --- a/include/configs/M5271EVB.h +++ b/include/configs/M5271EVB.h @@ -210,7 +210,7 @@ #define CFG_FLASH_ERASE_TOUT 1000 #define CFG_FLASH_CFI 1 -#define CFG_FLASH_CFI_DRIVER 1 +#define CONFIG_FLASH_CFI_DRIVER 1 #define CFG_FLASH_SIZE 0x200000 /* Cache Configuration */ diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index 283c873..30c70e5 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -197,7 +197,7 @@ #define CFG_FLASH_ERASE_TOUT 1000 #define CFG_FLASH_CFI 1 -#define CFG_FLASH_CFI_DRIVER 1 +#define CONFIG_FLASH_CFI_DRIVER 1 #define CFG_FLASH_SIZE 0x200000 /*----------------------------------------------------------------------- diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index df46ee4..c2c7fab 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -194,7 +194,7 @@ #define CFG_FLASH_CFI #ifdef CFG_FLASH_CFI -# define CFG_FLASH_CFI_DRIVER 1 +# define CONFIG_FLASH_CFI_DRIVER 1 # define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */ # define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT # define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index b30d99c..58948a2 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -202,7 +202,7 @@ */ #define CFG_FLASH_CFI #ifdef CFG_FLASH_CFI -# define CFG_FLASH_CFI_DRIVER 1 +# define CONFIG_FLASH_CFI_DRIVER 1 # define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */ # define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT # define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index a710c6d..814c3a6 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -202,7 +202,7 @@ */ #define CFG_FLASH_CFI #ifdef CFG_FLASH_CFI -# define CFG_FLASH_CFI_DRIVER 1 +# define CONFIG_FLASH_CFI_DRIVER 1 # define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */ # define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT # define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index 3a022af..6620f03 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -302,7 +302,7 @@ #undef CFG_FLASH_CFI #ifdef CFG_FLASH_CFI -# define CFG_FLASH_CFI_DRIVER 1 +# define CONFIG_FLASH_CFI_DRIVER 1 # define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */ # define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT # define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h index e8804b5..4037efb 100644 --- a/include/configs/M5475EVB.h +++ b/include/configs/M5475EVB.h @@ -259,7 +259,7 @@ #define CFG_FLASH_CFI #ifdef CFG_FLASH_CFI # define CFG_FLASH_BASE (CFG_CS0_BASE) -# define CFG_FLASH_CFI_DRIVER 1 +# define CONFIG_FLASH_CFI_DRIVER 1 # define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT # define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ # define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h index 0f957ff..a14c55b 100644 --- a/include/configs/M5485EVB.h +++ b/include/configs/M5485EVB.h @@ -245,7 +245,7 @@ #define CFG_FLASH_CFI #ifdef CFG_FLASH_CFI # define CFG_FLASH_BASE (CFG_CS0_BASE) -# define CFG_FLASH_CFI_DRIVER 1 +# define CONFIG_FLASH_CFI_DRIVER 1 # define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT # define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ # define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index d683b87..66235e3 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -88,7 +88,7 @@ #endif -#define CFG_NAND_LEGACY +#define CONFIG_NAND_LEGACY #define CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index d547681..a4c4240 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -63,6 +63,10 @@ #define CFG_IMMR 0xE0000000 +#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#define CONFIG_DEFAULT_IMMR CFG_IMMR +#endif + #define CFG_MEMTEST_START 0x00001000 #define CFG_MEMTEST_END 0x07f00000 @@ -167,16 +171,16 @@ * FLASH on the Local Bus */ #define CFG_FLASH_CFI /* use the Common Flash Interface */ -#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ #define CFG_FLASH_SIZE 8 /* flash size in MB */ #define CFG_FLASH_EMPTY_INFO /* display empty sectors */ #define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ +#define CFG_NOR_BR_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ BR_V) /* valid */ -#define CFG_OR0_PRELIM ( 0xFF000000 /* 16 MByte */ \ +#define CFG_NOR_OR_PRELIM ( 0xFF800000 /* 8 MByte */ \ | OR_GPCM_XACS \ | OR_GPCM_SCY_9 \ | OR_GPCM_EHTR \ @@ -193,7 +197,7 @@ #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) && !defined(CONFIG_NAND_SPL) #define CFG_RAMBOOT #endif @@ -220,17 +224,31 @@ #define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */ /* drivers/mtd/nand/nand.c */ -#define CFG_NAND_BASE 0xE2800000 /* 0xF0000000 */ +#ifdef CONFIG_NAND_SPL +#define CFG_NAND_BASE 0xFFF00000 +#else +#define CFG_NAND_BASE 0xE2800000 +#endif + #define CFG_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1 #define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND 1 +#define CONFIG_NAND_FSL_ELBC 1 +#define CFG_NAND_BLOCK_SIZE 16384 + +#define CFG_NAND_U_BOOT_SIZE (512 << 10) +#define CFG_NAND_U_BOOT_DST 0x00100000 +#define CFG_NAND_U_BOOT_START 0x00100100 +#define CFG_NAND_U_BOOT_OFFS 16384 +#define CFG_NAND_U_BOOT_RELOC 0x00010000 -#define CFG_BR1_PRELIM ( CFG_NAND_BASE \ +#define CFG_NAND_BR_PRELIM ( CFG_NAND_BASE \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V ) /* valid */ -#define CFG_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \ +#define CFG_NAND_OR_PRELIM ( 0xFFFF8000 /* length 32K */ \ | OR_FCM_CSCT \ | OR_FCM_CST \ | OR_FCM_CHT \ @@ -238,9 +256,25 @@ | OR_FCM_TRLX \ | OR_FCM_EHTR ) /* 0xFFFF8396 */ + +#ifdef CONFIG_NAND_U_BOOT +#define CFG_BR0_PRELIM CFG_NAND_BR_PRELIM +#define CFG_OR0_PRELIM CFG_NAND_OR_PRELIM +#define CFG_BR1_PRELIM CFG_NOR_BR_PRELIM +#define CFG_OR1_PRELIM CFG_NOR_OR_PRELIM +#else +#define CFG_BR0_PRELIM CFG_NOR_BR_PRELIM +#define CFG_OR0_PRELIM CFG_NOR_OR_PRELIM +#define CFG_BR1_PRELIM CFG_NAND_BR_PRELIM +#define CFG_OR1_PRELIM CFG_NAND_OR_PRELIM +#endif + #define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE #define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ +#define CFG_NAND_LBLAWBAR_PRELIM CFG_LBLAWBAR1_PRELIM +#define CFG_NAND_LBLAWAR_PRELIM CFG_LBLAWAR1_PRELIM + /* local bus read write buffer mapping */ #define CFG_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */ #define CFG_OR3_PRELIM 0xFFFF8FF7 /* 32kB */ @@ -272,7 +306,6 @@ #define CFG_NS16550 #define CFG_NS16550_SERIAL #define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK get_bus_freq(0) #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} @@ -351,7 +384,15 @@ /* * Environment */ -#ifndef CFG_RAMBOOT +#if defined(CONFIG_NAND_U_BOOT) + #define CFG_ENV_IS_IN_NAND 1 + #define CFG_ENV_OFFSET (512 * 1024) + #define CFG_ENV_SECT_SIZE CFG_NAND_BLOCK_SIZE + #define CFG_ENV_SIZE CFG_ENV_SECT_SIZE + #define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE + #define CFG_ENV_RANGE (CFG_ENV_SECT_SIZE * 4) + #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_RANGE) +#elif !defined(CFG_RAMBOOT) #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ @@ -388,7 +429,7 @@ #define CONFIG_CMD_DATE #define CONFIG_CMD_PCI -#if defined(CFG_RAMBOOT) +#if defined(CFG_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) #undef CONFIG_CMD_ENV #undef CONFIG_CMD_LOADS #endif @@ -430,6 +471,8 @@ HRCWL_CSB_TO_CLKIN_2X1 |\ HRCWL_CORE_TO_CSB_2X1) +#define CFG_NS16550_CLK (CONFIG_83XX_CLKIN * 2) + #elif defined(CFG_33MHZ) /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ @@ -442,22 +485,31 @@ HRCWL_CSB_TO_CLKIN_5X1 |\ HRCWL_CORE_TO_CSB_2X1) +#define CFG_NS16550_CLK (CONFIG_83XX_CLKIN * 5) + #endif -/* 0xa0606c00 */ -#define CFG_HRCW_HIGH (\ +#define CFG_HRCW_HIGH_BASE (\ HRCWH_PCI_HOST |\ HRCWH_PCI1_ARBITER_ENABLE |\ HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ HRCWH_BOOTSEQ_DISABLE |\ HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY |\ HRCWH_TSEC1M_IN_RGMII |\ HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN |\ - HRCWH_LALE_NORMAL) + HRCWH_BIG_ENDIAN) + +#ifdef CONFIG_NAND_SPL +#define CFG_HRCW_HIGH (CFG_HRCW_HIGH_BASE |\ + HRCWH_FROM_0XFFF00100 |\ + HRCWH_ROM_LOC_NAND_SP_8BIT |\ + HRCWH_RL_EXT_NAND) +#else +#define CFG_HRCW_HIGH (CFG_HRCW_HIGH_BASE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_RL_EXT_LEGACY) +#endif /* System IO Config */ #define CFG_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 095f665..b0cc36d 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -188,7 +188,7 @@ * FLASH on the Local Bus */ #define CFG_FLASH_CFI /* use the Common Flash Interface */ -#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 977c041..94b3d5a 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -178,7 +178,7 @@ * FLASH on the Local Bus */ #define CFG_FLASH_CFI /* use the Common Flash Interface */ -#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CFG_FLASH_SIZE 16 /* FLASH size is 16M */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 9ca2a2b..401d0af 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -166,7 +166,7 @@ * FLASH on the Local Bus */ #define CFG_FLASH_CFI /* use the Common Flash Interface */ -#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CFG_FLASH_SIZE 16 /* FLASH size is 16M */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 8705838..a53f5cd 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -148,7 +148,7 @@ * FLASH on the Local Bus */ #define CFG_FLASH_CFI /* use the Common Flash Interface */ -#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ #define CFG_FLASH_SIZE 32 /* max flash size in MB */ /* #define CFG_FLASH_USE_BUFFER_WRITE */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 82d0686..45ddd5c 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -175,7 +175,7 @@ */ #define CFG_FLASH_CFI /* use the Common Flash Interface */ -#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ #define CFG_FLASH_EMPTY_INFO #define CFG_MAX_FLASH_SECT 135 /* 127 64KB sectors + 8 8KB sectors per device */ @@ -419,7 +419,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CFG_ENV_SIZE 0x2000 #else #define CFG_NO_FLASH /* Flash is not usable now */ - #undef CFG_FLASH_CFI_DRIVER + #undef CONFIG_FLASH_CFI_DRIVER #define CFG_ENV_IS_NOWHERE /* Store ENV in memory only */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) #define CFG_ENV_SIZE 0x2000 diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index b4bff9a..43d4118 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -191,7 +191,7 @@ * FLASH on the Local Bus */ #define CFG_FLASH_CFI /* use the Common Flash Interface */ -#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CFG_FLASH_SIZE 32 /* max FLASH size is 32M */ #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index ca8d53c..6898495 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -184,7 +184,7 @@ * FLASH on the Local Bus */ #define CFG_FLASH_CFI /* use the Common Flash Interface */ -#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CFG_FLASH_SIZE 8 /* max FLASH size is 32M */ #define CFG_FLASH_PROTECTION 1 /* Use intel Flash protection. */ diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 0dd0279..f9c1b17 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -226,7 +226,7 @@ * FLASH on the Local Bus */ #define CFG_FLASH_CFI /* use the Common Flash Interface */ -#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CFG_FLASH_SIZE 32 /* max FLASH size is 32M */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 29c2490..82b3353 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -249,7 +249,7 @@ * FLASH on the Local Bus */ #define CFG_FLASH_CFI /* use the Common Flash Interface */ -#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CFG_FLASH_SIZE 8 /* max FLASH size is 32M */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index d1d3cc3..6351925 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -152,7 +152,7 @@ #undef CFG_RAMBOOT #endif -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #define CFG_FLASH_EMPTY_INFO diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index a64565d..d948d76 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -154,7 +154,7 @@ extern unsigned long get_clock_freq(void); #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #define CFG_FLASH_EMPTY_INFO diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 091fd2e..9a77b7b 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -168,7 +168,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #define CFG_FLASH_EMPTY_INFO diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index acf6f0d..33c5c93 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -172,7 +172,7 @@ extern unsigned long get_clock_freq(void); #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #define CFG_FLASH_EMPTY_INFO diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 1948c0d..85c235c 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -154,7 +154,7 @@ extern unsigned long get_clock_freq(void); #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #define CFG_FLASH_EMPTY_INFO diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 27212162..3567d1ce 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -148,7 +148,7 @@ #undef CFG_RAMBOOT #endif -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #define CFG_FLASH_EMPTY_INFO diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 9e6bb44..a82d528 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -167,7 +167,7 @@ extern unsigned long get_clock_freq(void); #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #define CFG_FLASH_EMPTY_INFO diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 06899b1..e9371a2 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -192,7 +192,7 @@ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #define CFG_FLASH_EMPTY_INFO diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index cd35494..468fd08 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -214,7 +214,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #define CFG_FLASH_EMPTY_INFO diff --git a/include/configs/MVBC_P.h b/include/configs/MVBC_P.h index 8c8a445..0ce88d6 100644 --- a/include/configs/MVBC_P.h +++ b/include/configs/MVBC_P.h @@ -40,7 +40,7 @@ #define CONFIG_MISC_INIT_R 1 #define CFG_CACHELINE_SIZE 32 -#ifdef (CONFIG_CMD_KGDB) +#ifdef CONFIG_CMD_KGDB #define CFG_CACHELINE_SHIFT 5 #endif @@ -198,7 +198,7 @@ */ #undef CONFIG_FLASH_16BIT #define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI_AMD_RESET 1 #define CFG_FLASH_EMPTY_INFO @@ -268,7 +268,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #undef CFG_LONGHELP #define CFG_PROMPT "=> " -#ifdef (CONFIG_CMD_KGDB) +#ifdef CONFIG_CMD_KGDB #define CFG_CBSIZE 1024 #else #define CFG_CBSIZE 256 diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index b412655..0dce9b4 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -104,7 +104,7 @@ /* Flash */ #define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CFG_FLASH_BASE 0xFF800000 diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h index fa0e5db..40cf275 100644 --- a/include/configs/MigoR.h +++ b/include/configs/MigoR.h @@ -67,7 +67,7 @@ #define CFG_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */ /* SCIF */ -#define CFG_SCIF_CONSOLE 1 +#define CONFIG_SCIF_CONSOLE 1 #define CONFIG_CONS_SCIF0 1 #undef CFG_CONSOLE_INFO_QUIET /* Suppress display of console information at boot */ @@ -103,7 +103,7 @@ /* FLASH */ #define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #undef CFG_FLASH_QUIET_TEST /* print 'E' for empty sector on flinfo */ #define CFG_FLASH_EMPTY_INFO diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h index 27e7ab9..6c18b81 100644 --- a/include/configs/NETPHONE.h +++ b/include/configs/NETPHONE.h @@ -502,7 +502,7 @@ /****************************************************************/ /* NAND */ -#define CFG_NAND_LEGACY +#define CONFIG_NAND_LEGACY #define CFG_NAND_BASE NAND_BASE #define CONFIG_MTD_NAND_ECC_JFFS2 #define CONFIG_MTD_NAND_VERIFY_WRITE diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h index 56c76d3..1f1bc54 100644 --- a/include/configs/NETTA.h +++ b/include/configs/NETTA.h @@ -621,7 +621,7 @@ /****************************************************************/ /* NAND */ -#define CFG_NAND_LEGACY +#define CONFIG_NAND_LEGACY #define CFG_NAND_BASE NAND_BASE #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_MTD_NAND_UNSAFE diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h index b8c4848..9a1f1d6 100644 --- a/include/configs/NETTA2.h +++ b/include/configs/NETTA2.h @@ -503,7 +503,7 @@ /****************************************************************/ /* NAND */ -#define CFG_NAND_LEGACY +#define CONFIG_NAND_LEGACY #define CFG_NAND_BASE NAND_BASE #define CONFIG_MTD_NAND_ECC_JFFS2 #define CONFIG_MTD_NAND_VERIFY_WRITE diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h index 1293fb0..c029594 100644 --- a/include/configs/NETVIA.h +++ b/include/configs/NETVIA.h @@ -397,7 +397,7 @@ /*****************************************************************************/ -#define CFG_NAND_LEGACY +#define CONFIG_NAND_LEGACY #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 diff --git a/include/configs/NSCU.h b/include/configs/NSCU.h index 11e5c63..31762b9 100644 --- a/include/configs/NSCU.h +++ b/include/configs/NSCU.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2005 + * (C) Copyright 2000-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -67,9 +67,16 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/NSCU/uImage\0" \ + "hostname=NSCU\0" \ + "bootfile=${hostname}/uImage\0" \ "kernel_addr=40080000\0" \ "ramdisk_addr=40180000\0" \ + "u-boot=${hostname}/u-image.bin\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=prot off 40000000 +${filesize};" \ + "era 40000000 +${filesize};" \ + "cp.b 200000 40000000 ${filesize};" \ + "sete filesize;save\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -110,20 +117,24 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF #define CONFIG_CMD_IDE #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP +#define CONFIG_NETCONSOLE + + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 +#define CONFIG_CMDLINE_EDITING 1 /* add command line history +*/ #define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif @@ -186,21 +197,26 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ +#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + /*----------------------------------------------------------------------- * Hardware Information Block */ diff --git a/include/configs/PCIPPC2.h b/include/configs/PCIPPC2.h index 268b034..6ebaa85 100644 --- a/include/configs/PCIPPC2.h +++ b/include/configs/PCIPPC2.h @@ -84,7 +84,7 @@ #define CONFIG_PCI 1 #define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ -#define CFG_NAND_LEGACY +#define CONFIG_NAND_LEGACY /* * Miscellaneous configurable options diff --git a/include/configs/PCIPPC6.h b/include/configs/PCIPPC6.h index 250b586..9202794 100644 --- a/include/configs/PCIPPC6.h +++ b/include/configs/PCIPPC6.h @@ -86,7 +86,7 @@ #define CONFIG_PCI 1 #define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ -#define CFG_NAND_LEGACY +#define CONFIG_NAND_LEGACY /* * Miscellaneous configurable options diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index 5890012..2ceda00 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -77,7 +77,7 @@ #define CONFIG_CMD_BSP -#define CFG_NAND_LEGACY +#define CONFIG_NAND_LEGACY #define CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " diff --git a/include/configs/PM520.h b/include/configs/PM520.h index 259178f..5e0bb05 100644 --- a/include/configs/PM520.h +++ b/include/configs/PM520.h @@ -88,7 +88,7 @@ #if !defined(CONFIG_BOOT_ROM) /* DoC requires legacy NAND for now */ -#define CFG_NAND_LEGACY +#define CONFIG_NAND_LEGACY #endif diff --git a/include/configs/PM826.h b/include/configs/PM826.h index 36e9aa5..190e2a4 100644 --- a/include/configs/PM826.h +++ b/include/configs/PM826.h @@ -180,7 +180,7 @@ #endif -#define CFG_NAND_LEGACY +#define CONFIG_NAND_LEGACY /* * Disk-On-Chip configuration diff --git a/include/configs/PM828.h b/include/configs/PM828.h index abf593c..96c0edf 100644 --- a/include/configs/PM828.h +++ b/include/configs/PM828.h @@ -183,7 +183,7 @@ /* * Disk-On-Chip configuration */ -#define CFG_NAND_LEGACY +#define CONFIG_NAND_LEGACY #define CFG_DOC_SHORT_TIMEOUT #define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ diff --git a/include/configs/PM854.h b/include/configs/PM854.h index bd058fc..f2c11b0 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -148,7 +148,7 @@ #undef CFG_RAMBOOT #endif -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #define CFG_FLASH_EMPTY_INFO diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 9355aaf..b2cf060 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -149,7 +149,7 @@ #undef CFG_RAMBOOT #endif -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #define CFG_FLASH_EMPTY_INFO diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h index adbe8a9..966bbf9 100644 --- a/include/configs/PMC405.h +++ b/include/configs/PMC405.h @@ -214,7 +214,7 @@ #define CFG_FLASH_INCREMENT 0x01000000 #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #define CFG_FLASH_PROTECTION 1 /* don't use hardware protection */ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ #define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */ diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index 42f1d8d..9140287 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -120,7 +120,7 @@ * FLASH related *----------------------------------------------------------------------*/ #define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } diff --git a/include/configs/Rattler.h b/include/configs/Rattler.h index 01ebc8f..e8ed095 100644 --- a/include/configs/Rattler.h +++ b/include/configs/Rattler.h @@ -187,7 +187,7 @@ #define CFG_FLASH_BASE 0xFE000000 #define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 8a53fdd..6033d93 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -291,7 +291,7 @@ */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #if 0 #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ #define CFG_FLASH_PROTECTION /* use hardware protection */ diff --git a/include/configs/SX1.h b/include/configs/SX1.h index 50ad7dd..d233679 100644 --- a/include/configs/SX1.h +++ b/include/configs/SX1.h @@ -181,7 +181,7 @@ * FLASH driver setup */ #define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ #define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h index aefc7ee..c5d5386 100644 --- a/include/configs/SXNI855T.h +++ b/include/configs/SXNI855T.h @@ -195,7 +195,7 @@ */ /* NAND flash support */ -#define CFG_NAND_LEGACY +#define CONFIG_NAND_LEGACY #define CONFIG_MTD_NAND_ECC_JFFS2 #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define SECTORSIZE 512 diff --git a/include/configs/Sandpoint8240.h b/include/configs/Sandpoint8240.h index 5bbe3c5..cfd16d3 100644 --- a/include/configs/Sandpoint8240.h +++ b/include/configs/Sandpoint8240.h @@ -235,7 +235,7 @@ */ -#define CFG_WINBOND_83C553 1 /*has a winbond bridge */ +#define CONFIG_WINBOND_83C553 1 /*has a winbond bridge */ #define CFG_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */ #define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */ #define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */ @@ -246,7 +246,7 @@ /* * NS87308 Configuration */ -#define CFG_NS87308 /* Nat Semi super-io controller on ISA bus */ +#define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */ #define CFG_NS87308_BADDR_10 1 diff --git a/include/configs/Sandpoint8245.h b/include/configs/Sandpoint8245.h index a08451e..c0f2c57 100644 --- a/include/configs/Sandpoint8245.h +++ b/include/configs/Sandpoint8245.h @@ -203,7 +203,7 @@ */ -#define CFG_WINBOND_83C553 1 /*has a winbond bridge */ +#define CONFIG_WINBOND_83C553 1 /*has a winbond bridge */ #define CFG_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */ #define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */ #define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */ @@ -214,7 +214,7 @@ /* * NS87308 Configuration */ -#define CFG_NS87308 /* Nat Semi super-io controller on ISA bus */ +#define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */ #define CFG_NS87308_BADDR_10 1 diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h index d21783b..3b68166 100644 --- a/include/configs/TB5200.h +++ b/include/configs/TB5200.h @@ -255,7 +255,7 @@ /* use CFI flash driver */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */ diff --git a/include/configs/TK885D.h b/include/configs/TK885D.h index 7310abf..8073b7e 100644 --- a/include/configs/TK885D.h +++ b/include/configs/TK885D.h @@ -247,7 +247,7 @@ /* use CFI flash driver */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_USE_BUFFER_WRITE 1 diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index bfb478a..992439f 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -386,7 +386,7 @@ #else /* use CFI flash driver */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks (= chip selects) */ diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h index 100be7c..839b6be 100644 --- a/include/configs/TQM823L.h +++ b/include/configs/TQM823L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2005 + * (C) Copyright 2000-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -37,6 +37,8 @@ #define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */ #ifdef CONFIG_LCD /* with LCD controller ? */ +#define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */ +#define CONFIG_LCD_INFO 1 /* ... and some board info */ #define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ #endif @@ -69,10 +71,17 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM823L/uImage\0" \ + "hostname=TQM823L\0" \ + "bootfile=TQM823L/uImage\0" \ "fdt_addr=40040000\0" \ "kernel_addr=40060000\0" \ "ramdisk_addr=40200000\0" \ + "u-boot=TQM823L/u-image.bin\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=prot off 40000000 +${filesize};" \ + "era 40000000 +${filesize};" \ + "cp.b 200000 40000000 ${filesize};" \ + "sete filesize;save\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -113,7 +122,9 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF #define CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP @@ -122,6 +133,8 @@ #endif +#define CONFIG_NETCONSOLE + /* * Miscellaneous configurable options */ @@ -195,8 +208,8 @@ /* use CFI flash driver */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size } #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_USE_BUFFER_WRITE 1 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ @@ -213,6 +226,18 @@ #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- + * Dynamic MTD partition support + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" + +#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ + "128k(dtb)," \ + "1664k(kernel)," \ + "2m(rootfs)," \ + "4m(data)" + +/*----------------------------------------------------------------------- * Hardware Information Block */ #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h index 40dc26b..b9a7a59 100644 --- a/include/configs/TQM823M.h +++ b/include/configs/TQM823M.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2005 + * (C) Copyright 2000-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -69,10 +69,17 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM823M/uImage\0" \ + "hostname=TQM823M\0" \ + "bootfile=TQM823M/uImage\0" \ "fdt_addr=40080000\0" \ "kernel_addr=400A0000\0" \ "ramdisk_addr=40280000\0" \ + "u-boot=TQM823M/u-image.bin\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=prot off 40000000 +${filesize};" \ + "era 40000000 +${filesize};" \ + "cp.b 200000 40000000 ${filesize};" \ + "sete filesize;save\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -113,11 +120,16 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF #define CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP +#define CONFIG_NETCONSOLE + + /* * Miscellaneous configurable options */ @@ -191,7 +203,7 @@ /* use CFI flash driver */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_USE_BUFFER_WRITE 1 @@ -210,6 +222,18 @@ #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- + * Dynamic MTD partition support + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" + +#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ + "128k(dtb)," \ + "1920k(kernel)," \ + "5632(rootfs)," \ + "4m(data)" + +/*----------------------------------------------------------------------- * Hardware Information Block */ #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h index ba0402d..039ecf1 100644 --- a/include/configs/TQM8272.h +++ b/include/configs/TQM8272.h @@ -372,7 +372,7 @@ #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ #define CFG_FLASH_CFI /* flash is CFI compat. */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */ #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 0d2ca72..e8f69f6 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -78,7 +78,7 @@ * FLASH on the Local Bus */ #define CFG_FLASH_CFI /* use the Common Flash Interface */ -#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ #undef CFG_FLASH_CHECKSUM #define CFG_FLASH_BASE 0x80000000 /* start of FLASH */ #define CFG_FLASH_SIZE 8 /* FLASH size in MB */ diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h index 3097bc3..388fafc 100644 --- a/include/configs/TQM850L.h +++ b/include/configs/TQM850L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2005 + * (C) Copyright 2000-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -65,10 +65,17 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM850L/uImage\0" \ + "hostname=TQM850L\0" \ + "bootfile=TQM850L/uImage\0" \ "fdt_addr=40040000\0" \ "kernel_addr=40060000\0" \ "ramdisk_addr=40200000\0" \ + "u-boot=TQM850L/u-image.bin\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=prot off 40000000 +${filesize};" \ + "era 40000000 +${filesize};" \ + "cp.b 200000 40000000 ${filesize};" \ + "sete filesize;save\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -104,11 +111,15 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF #define CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP +#define CONFIG_NETCONSOLE + /* * Miscellaneous configurable options */ @@ -182,8 +193,8 @@ /* use CFI flash driver */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size } #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_USE_BUFFER_WRITE 1 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ @@ -200,6 +211,18 @@ #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- + * Dynamic MTD partition support + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" + +#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ + "128k(dtb)," \ + "1664k(kernel)," \ + "2m(rootfs)," \ + "4m(data)" + +/*----------------------------------------------------------------------- * Hardware Information Block */ #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h index becf82c..6f0864f 100644 --- a/include/configs/TQM850M.h +++ b/include/configs/TQM850M.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2005 + * (C) Copyright 2000-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -63,10 +63,17 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM850M/uImage\0" \ + "hostname=TQM850M\0" \ + "bootfile=TQM850M/uImage\0" \ "fdt_addr=40080000\0" \ "kernel_addr=400A0000\0" \ "ramdisk_addr=40280000\0" \ + "u-boot=TQM850M/u-image.bin\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=prot off 40000000 +${filesize};" \ + "era 40000000 +${filesize};" \ + "cp.b 200000 40000000 ${filesize};" \ + "sete filesize;save\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -102,11 +109,16 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF #define CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP +#define CONFIG_NETCONSOLE + + /* * Miscellaneous configurable options */ @@ -180,7 +192,7 @@ /* use CFI flash driver */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_USE_BUFFER_WRITE 1 @@ -199,6 +211,18 @@ #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- + * Dynamic MTD partition support + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" + +#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ + "128k(dtb)," \ + "1920k(kernel)," \ + "5632(rootfs)," \ + "4m(data)" + +/*----------------------------------------------------------------------- * Hardware Information Block */ #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h index 8ca8906..093d659 100644 --- a/include/configs/TQM855L.h +++ b/include/configs/TQM855L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2005 + * (C) Copyright 2000-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -68,10 +68,17 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM855L/uImage\0" \ + "hostname=TQM855L\0" \ + "bootfile=TQM855L/uImage\0" \ "fdt_addr=40040000\0" \ "kernel_addr=40060000\0" \ "ramdisk_addr=40200000\0" \ + "u-boot=TQM855L/u-image.bin\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=prot off 40000000 +${filesize};" \ + "era 40000000 +${filesize};" \ + "cp.b 200000 40000000 ${filesize};" \ + "sete filesize;save\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -108,11 +115,16 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF #define CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP +#define CONFIG_NETCONSOLE + + /* * Miscellaneous configurable options */ @@ -186,8 +198,8 @@ /* use CFI flash driver */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size } #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_USE_BUFFER_WRITE 1 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ @@ -204,6 +216,18 @@ #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- + * Dynamic MTD partition support + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" + +#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ + "128k(dtb)," \ + "1664k(kernel)," \ + "2m(rootfs)," \ + "4m(data)" + +/*----------------------------------------------------------------------- * Hardware Information Block */ #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h index 2696ea5..64bbc39 100644 --- a/include/configs/TQM855M.h +++ b/include/configs/TQM855M.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2005 + * (C) Copyright 2000-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -68,10 +68,17 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM855M/uImage\0" \ + "hostname=TQM855M\0" \ + "bootfile=TQM855M/uImage\0" \ "fdt_addr=40080000\0" \ "kernel_addr=400A0000\0" \ "ramdisk_addr=40280000\0" \ + "u-boot=TQM855M/u-image.bin\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=prot off 40000000 +${filesize};" \ + "era 40000000 +${filesize};" \ + "cp.b 200000 40000000 ${filesize};" \ + "sete filesize;save\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -141,12 +148,17 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF #define CONFIG_CMD_EEPROM #define CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP +#define CONFIG_NETCONSOLE + + /* * Miscellaneous configurable options */ @@ -220,7 +232,7 @@ /* use CFI flash driver */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_USE_BUFFER_WRITE 1 @@ -239,6 +251,18 @@ #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- + * Dynamic MTD partition support + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" + +#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ + "128k(dtb)," \ + "1920k(kernel)," \ + "5632(rootfs)," \ + "4m(data)" + +/*----------------------------------------------------------------------- * Hardware Information Block */ #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index d18f234..d84554e 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -204,7 +204,7 @@ #endif /* CONFIG_TQM_BIGFLASH */ #define CFG_FLASH_CFI /* flash is CFI compat. */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */ #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* speed up output to Flash */ @@ -345,7 +345,7 @@ /* NAND FLASH */ #ifdef CONFIG_NAND -#undef CFG_NAND_LEGACY +#undef CONFIG_NAND_LEGACY #define CONFIG_NAND_FSL_UPM 1 diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h index f66aace..dacc340 100644 --- a/include/configs/TQM860L.h +++ b/include/configs/TQM860L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2005 + * (C) Copyright 2000-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -68,10 +68,17 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM860L/uImage\0" \ + "hostname=TQM860L\0" \ + "bootfile=TQM860L/uImage\0" \ "fdt_addr=40040000\0" \ "kernel_addr=40060000\0" \ "ramdisk_addr=40200000\0" \ + "u-boot=TQM860L/u-image.bin\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=prot off 40000000 +${filesize};" \ + "era 40000000 +${filesize};" \ + "cp.b 200000 40000000 ${filesize};" \ + "sete filesize;save\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -110,6 +117,7 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_ELF #define CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP @@ -189,8 +197,8 @@ /* use CFI flash driver */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size } #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_USE_BUFFER_WRITE 1 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ @@ -207,6 +215,18 @@ #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- + * Dynamic MTD partition support + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" + +#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ + "128k(dtb)," \ + "1664k(kernel)," \ + "2m(rootfs)," \ + "4m(data)" + +/*----------------------------------------------------------------------- * Hardware Information Block */ #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h index 00b7853..3ec849c 100644 --- a/include/configs/TQM860M.h +++ b/include/configs/TQM860M.h @@ -68,15 +68,17 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM860M/uImage\0" \ + "hostname=TQM860M\0" \ + "bootfile=TQM860M/uImage\0" \ "fdt_addr=400C0000\0" \ "kernel_addr=40100000\0" \ "ramdisk_addr=40280000\0" \ + "u-boot=TQM860M/u-image.bin\0" \ "load=tftp 200000 ${u-boot}\0" \ - "update=protect off 40000000 +${filesize};" \ - "erase 40000000 +${filesize};" \ + "update=prot off 40000000 +${filesize};" \ + "era 40000000 +${filesize};" \ "cp.b 200000 40000000 ${filesize};" \ - "protect on 40000000 +${filesize}\0" \ + "sete filesize;save\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -115,10 +117,14 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_ELF #define CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP +#define CONFIG_NETCONSOLE + + /* * Miscellaneous configurable options */ @@ -191,7 +197,7 @@ */ /* use CFI flash driver */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_USE_BUFFER_WRITE 1 @@ -210,6 +216,18 @@ #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- + * Dynamic MTD partition support + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" + +#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ + "128k(dtb)," \ + "1920k(kernel)," \ + "5632(rootfs)," \ + "4m(data)" + +/*----------------------------------------------------------------------- * Hardware Information Block */ #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h index 7813a20..6c610ee 100644 --- a/include/configs/TQM862L.h +++ b/include/configs/TQM862L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2005 + * (C) Copyright 2000-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -71,10 +71,17 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM862L/uImage\0" \ + "hostname=TQM862L\0" \ + "bootfile=TQM862L/uImage\0" \ "fdt_addr=40040000\0" \ "kernel_addr=40060000\0" \ "ramdisk_addr=40200000\0" \ + "u-boot=TQM862L/u-image.bin\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=prot off 40000000 +${filesize};" \ + "era 40000000 +${filesize};" \ + "cp.b 200000 40000000 ${filesize};" \ + "sete filesize;save\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -111,11 +118,16 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF #define CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP +#define CONFIG_NETCONSOLE + + /* * Miscellaneous configurable options */ @@ -189,8 +201,8 @@ /* use CFI flash driver */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size } #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_USE_BUFFER_WRITE 1 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ @@ -207,6 +219,18 @@ #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- + * Dynamic MTD partition support + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" + +#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ + "128k(dtb)," \ + "1664k(kernel)," \ + "2m(rootfs)," \ + "4m(data)" + +/*----------------------------------------------------------------------- * Hardware Information Block */ #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h index 05395e0..2eca59b 100644 --- a/include/configs/TQM862M.h +++ b/include/configs/TQM862M.h @@ -71,10 +71,17 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM862M/uImage\0" \ + "hostname=TQM862M\0" \ + "bootfile=TQM862M/uImage\0" \ "fdt_addr=40080000\0" \ "kernel_addr=400A0000\0" \ "ramdisk_addr=40280000\0" \ + "u-boot=TQM862M/u-image.bin\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=prot off 40000000 +${filesize};" \ + "era 40000000 +${filesize};" \ + "cp.b 200000 40000000 ${filesize};" \ + "sete filesize;save\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -111,11 +118,16 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF #define CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP +#define CONFIG_NETCONSOLE + + /* * Miscellaneous configurable options */ @@ -189,7 +201,7 @@ /* use CFI flash driver */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_USE_BUFFER_WRITE 1 @@ -208,6 +220,18 @@ #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- + * Dynamic MTD partition support + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" + +#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ + "128k(dtb)," \ + "1920k(kernel)," \ + "5632(rootfs)," \ + "4m(data)" + +/*----------------------------------------------------------------------- * Hardware Information Block */ #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h index d033875..4683286 100644 --- a/include/configs/TQM866M.h +++ b/include/configs/TQM866M.h @@ -80,15 +80,17 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM866M/uImage\0" \ + "hostname=TQM866M\0" \ + "bootfile=TQM866M/uImage\0" \ "fdt_addr=400C0000\0" \ "kernel_addr=40100000\0" \ "ramdisk_addr=40280000\0" \ + "u-boot=TQM866M/u-image.bin\0" \ "load=tftp 200000 ${u-boot}\0" \ - "update=protect off 40000000 +${filesize};" \ - "erase 40000000 +${filesize};" \ + "update=prot off 40000000 +${filesize};" \ + "era 40000000 +${filesize};" \ "cp.b 200000 40000000 ${filesize};" \ - "protect on 40000000 +${filesize}\0" \ + "sete filesize;save\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -157,9 +159,14 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DHCP #define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C +#define CONFIG_CMD_ELF #define CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP + + +#define CONFIG_NETCONSOLE /* @@ -234,7 +241,7 @@ */ /* use CFI flash driver */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_USE_BUFFER_WRITE 1 @@ -253,6 +260,18 @@ #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- + * Dynamic MTD partition support + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" + +#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ + "128k(dtb)," \ + "1920k(kernel)," \ + "5632(rootfs)," \ + "4m(data)" + +/*----------------------------------------------------------------------- * Hardware Information Block */ #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h index f075442..5daaf04 100644 --- a/include/configs/TQM885D.h +++ b/include/configs/TQM885D.h @@ -244,7 +244,7 @@ /* use CFI flash driver */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_USE_BUFFER_WRITE 1 diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h index 598fe7b..25e98e2 100644 --- a/include/configs/Total5200.h +++ b/include/configs/Total5200.h @@ -204,7 +204,7 @@ * Flash configuration */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #if CONFIG_TOTAL5200_REV==2 # define CFG_MAX_FLASH_BANKS 3 /* max num of flash banks */ # define CFG_FLASH_BANKS_LIST { CFG_CS5_START, CFG_CS4_START, CFG_BOOTCS_START } diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index ad8db61..02cabb2 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -254,7 +254,7 @@ */ #if defined(CONFIG_CMD_NAND) -#define CFG_NAND_LEGACY +#define CONFIG_NAND_LEGACY #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define SECTORSIZE 512 diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h index b04be76..388c747 100644 --- a/include/configs/ZPC1900.h +++ b/include/configs/ZPC1900.h @@ -179,7 +179,7 @@ #define CFG_FLSIMM_BASE 0xFF000000 #define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */ #define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */ diff --git a/include/configs/acadia.h b/include/configs/acadia.h index 9092a7c..ed2754d 100644 --- a/include/configs/acadia.h +++ b/include/configs/acadia.h @@ -107,7 +107,7 @@ *----------------------------------------------------------------------*/ #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ diff --git a/include/configs/actux1.h b/include/configs/actux1.h index 4c4b1d1..33a7494 100644 --- a/include/configs/actux1.h +++ b/include/configs/actux1.h @@ -162,7 +162,7 @@ /* Use common CFI driver */ #define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER /* no byte writes on IXP4xx */ #define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* print 'E' for empty sector on flinfo */ diff --git a/include/configs/actux2.h b/include/configs/actux2.h index 873fced..75aaa11 100644 --- a/include/configs/actux2.h +++ b/include/configs/actux2.h @@ -136,7 +136,7 @@ /* Use common CFI driver */ #define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER /* no byte writes on IXP4xx */ #define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT diff --git a/include/configs/actux3.h b/include/configs/actux3.h index 5e468e6..693c284 100644 --- a/include/configs/actux3.h +++ b/include/configs/actux3.h @@ -135,7 +135,7 @@ /* Use common CFI driver */ #define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER /* no byte writes on IXP4xx */ #define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT diff --git a/include/configs/actux4.h b/include/configs/actux4.h index e4dca2a..7f8e0f4 100644 --- a/include/configs/actux4.h +++ b/include/configs/actux4.h @@ -134,7 +134,7 @@ /* Use common CFI driver */ #define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER /* board provides its own flash_init code */ #define CONFIG_FLASH_CFI_LEGACY 1 /* no byte writes on IXP4xx */ diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index f104e68..d129ea3 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -183,7 +183,7 @@ */ #undef CONFIG_BKUP_FLASH #define CFG_FLASH_CFI /* use the Common Flash Interface */ -#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ #ifdef CONFIG_BKUP_FLASH #define CFG_FLASH_BASE 0xFF800000 /* start of FLASH */ #define CFG_FLASH_SIZE 0x00800000 /* max flash size in bytes */ @@ -308,6 +308,7 @@ #define CONFIG_PHY_ADDR 0x1 #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_FEC_AN_TIMEOUT 1 +#define CONFIG_HAS_ETH0 /* * Configure on-board RTC @@ -478,10 +479,10 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1 #define OF_CPU "PowerPC,5121@0" -#define OF_SOC "soc@80000000" -#define OF_SOC_OLD "soc5121@80000000" +#define OF_SOC_COMPAT "fsl,mpc5121-immr" #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc@80000000/serial@11300" diff --git a/include/configs/aev.h b/include/configs/aev.h index c5e4759..f27cc4a 100644 --- a/include/configs/aev.h +++ b/include/configs/aev.h @@ -225,7 +225,7 @@ /* use CFI flash driver if no module variant is spezified */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */ diff --git a/include/configs/alpr.h b/include/configs/alpr.h index fb6feb5..f342c7a 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -86,7 +86,7 @@ * FLASH related *----------------------------------------------------------------------*/ #define CFG_FLASH_CFI 1 /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ diff --git a/include/configs/apollon.h b/include/configs/apollon.h index 5884611..c93e77a 100644 --- a/include/configs/apollon.h +++ b/include/configs/apollon.h @@ -215,7 +215,7 @@ * CFI FLASH driver setup */ # define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ -# define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +# define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ /* #define CFG_FLASH_USE_BUFFER_WRITE 1 */ /* Use buffered writes (~10x faster) */ # define CFG_FLASH_PROTECTION 1 /* Use h/w sector protection*/ diff --git a/include/configs/assabet.h b/include/configs/assabet.h index d10f092..ed7b5ef 100644 --- a/include/configs/assabet.h +++ b/include/configs/assabet.h @@ -152,7 +152,7 @@ #define CFG_FLASH_BASE PHYS_FLASH_1 #define CFG_FLASH_SIZE PHYS_FLASH_SIZE #define CFG_FLASH_CFI 1 /* flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ #define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */ #define CFG_FLASH_INCREMENT 0 /* there is only one bank */ diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h index 342ce2a..520c676 100644 --- a/include/configs/at91cap9adk.h +++ b/include/configs/at91cap9adk.h @@ -109,7 +109,7 @@ /* NOR flash */ #define CFG_FLASH_CFI 1 -#define CFG_FLASH_CFI_DRIVER 1 +#define CONFIG_FLASH_CFI_DRIVER 1 #define PHYS_FLASH_1 0x10000000 #define CFG_FLASH_BASE PHYS_FLASH_1 #define CFG_MAX_FLASH_SECT 256 diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h index cd2eae2..fca431e 100644 --- a/include/configs/at91rm9200dk.h +++ b/include/configs/at91rm9200dk.h @@ -116,7 +116,7 @@ #define CONFIG_CMD_MII #define CONFIG_CMD_NAND -#define CFG_NAND_LEGACY +#define CONFIG_NAND_LEGACY #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define SECTORSIZE 512 diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index a8194b5..5f90d39 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -113,7 +113,7 @@ #define CFG_NO_FLASH 1 #else #define CFG_FLASH_CFI 1 -#define CFG_FLASH_CFI_DRIVER 1 +#define CONFIG_FLASH_CFI_DRIVER 1 #define PHYS_FLASH_1 0x10000000 #define CFG_FLASH_BASE PHYS_FLASH_1 #define CFG_MAX_FLASH_SECT 256 diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h index f040b86..6d8c1b2 100644 --- a/include/configs/atngw100.h +++ b/include/configs/atngw100.h @@ -140,7 +140,7 @@ #define CONFIG_NR_DRAM_BANKS 1 #define CFG_FLASH_CFI 1 -#define CFG_FLASH_CFI_DRIVER 1 +#define CONFIG_FLASH_CFI_DRIVER 1 #define CFG_FLASH_BASE 0x00000000 #define CFG_FLASH_SIZE 0x800000 diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index 68f0cec..3a7d273 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -163,7 +163,7 @@ /* External flash on STK1000 */ #if 0 #define CFG_FLASH_CFI 1 -#define CFG_FLASH_CFI_DRIVER 1 +#define CONFIG_FLASH_CFI_DRIVER 1 #endif #define CFG_FLASH_BASE 0x00000000 diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h index d3a2f69..55ea7f2 100644 --- a/include/configs/atstk1003.h +++ b/include/configs/atstk1003.h @@ -146,7 +146,7 @@ /* External flash on STK1000 */ #if 0 #define CFG_FLASH_CFI 1 -#define CFG_FLASH_CFI_DRIVER 1 +#define CONFIG_FLASH_CFI_DRIVER 1 #endif #define CFG_FLASH_BASE 0x00000000 diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h index a37ba92..369c619 100644 --- a/include/configs/atstk1004.h +++ b/include/configs/atstk1004.h @@ -146,7 +146,7 @@ /* External flash on STK1000 */ #if 0 #define CFG_FLASH_CFI 1 -#define CFG_FLASH_CFI_DRIVER 1 +#define CONFIG_FLASH_CFI_DRIVER 1 #endif #define CFG_FLASH_BASE 0x00000000 diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h index a6c5b6e..902f822 100644 --- a/include/configs/atstk1006.h +++ b/include/configs/atstk1006.h @@ -163,7 +163,7 @@ /* External flash on STK1000 */ #if 0 #define CFG_FLASH_CFI 1 -#define CFG_FLASH_CFI_DRIVER 1 +#define CONFIG_FLASH_CFI_DRIVER 1 #endif #define CFG_FLASH_BASE 0x00000000 diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h index d70aa10..9f5667b 100644 --- a/include/configs/bf533-stamp.h +++ b/include/configs/bf533-stamp.h @@ -94,7 +94,7 @@ */ #define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_FLASH_CFI_AMD_RESET #define CFG_FLASH_BASE 0x20000000 diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index a881d53..a06c1dc 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -221,7 +221,7 @@ #define CFG_FLASH_BASE 0x20000000 #define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_FLASH_PROTECTION #define CFG_MAX_FLASH_BANKS 1 #define CFG_MAX_FLASH_SECT 71 /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */ diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h index e99e979..e4a7f9d 100644 --- a/include/configs/bf561-ezkit.h +++ b/include/configs/bf561-ezkit.h @@ -77,7 +77,7 @@ */ #define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_FLASH_CFI_AMD_RESET #define CFG_ENV_IS_IN_FLASH 1 #define CFG_FLASH_BASE 0x20000000 diff --git a/include/configs/canmb.h b/include/configs/canmb.h index f097e2c..38714cc 100644 --- a/include/configs/canmb.h +++ b/include/configs/canmb.h @@ -130,7 +130,7 @@ #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #define CFG_FLASH_EMPTY_INFO diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index ac2e5d9..3b5b280 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -188,7 +188,7 @@ * FLASH related *----------------------------------------------------------------------*/ #define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */ #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h index ef50c7c..0221dfe 100644 --- a/include/configs/cm5200.h +++ b/include/configs/cm5200.h @@ -177,7 +177,7 @@ * Flash configuration */ #define CFG_FLASH_CFI 1 -#define CFG_FLASH_CFI_DRIVER 1 +#define CONFIG_FLASH_CFI_DRIVER 1 #define CFG_FLASH_BASE 0xfc000000 /* we need these despite using CFI */ #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ diff --git a/include/configs/csb272.h b/include/configs/csb272.h index 15bf177..5145c00 100644 --- a/include/configs/csb272.h +++ b/include/configs/csb272.h @@ -264,7 +264,7 @@ * */ #define CFG_FLASH_CFI 1 /* flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ #define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */ #define CFG_FLASH_INCREMENT 0 /* there is only one bank */ diff --git a/include/configs/csb472.h b/include/configs/csb472.h index b06c0a2..d3e5ea8 100644 --- a/include/configs/csb472.h +++ b/include/configs/csb472.h @@ -263,7 +263,7 @@ * */ #define CFG_FLASH_CFI 1 /* flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ #define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */ #define CFG_FLASH_INCREMENT 0 /* there is only one bank */ diff --git a/include/configs/csb637.h b/include/configs/csb637.h index 735a211..88c8fdb 100644 --- a/include/configs/csb637.h +++ b/include/configs/csb637.h @@ -179,7 +179,7 @@ #define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */ #define CFG_FLASH_BASE PHYS_FLASH_1 #define CFG_FLASH_CFI 1 /* flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ #define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */ diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index 632c4c2..c27ce18 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -140,7 +140,7 @@ #endif #define CFG_ENV_IS_IN_FLASH #undef CFG_NO_FLASH -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */ #define CFG_FLASH_SECT_SZ 0x10000 /* 64KB sect size AMD Flash */ diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h index ba68605..c55766c 100644 --- a/include/configs/davinci_sonata.h +++ b/include/configs/davinci_sonata.h @@ -135,7 +135,7 @@ #endif #define CFG_ENV_IS_IN_FLASH #undef CFG_NO_FLASH -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */ #define CFG_FLASH_SECT_SZ 0x20000 /* 128KB sect size AMD Flash */ diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h index 0e10396..8941c5e 100644 --- a/include/configs/dbau1x00.h +++ b/include/configs/dbau1x00.h @@ -183,7 +183,7 @@ #define CFG_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2} #define CFG_FLASH_CFI 1 -#define CFG_FLASH_CFI_DRIVER 1 +#define CONFIG_FLASH_CFI_DRIVER 1 /* The following #defines are needed to get flash environment right */ #define CFG_MONITOR_BASE TEXT_BASE diff --git a/include/configs/delta.h b/include/configs/delta.h index 14fde1a..1db962a 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -217,7 +217,7 @@ /* * NAND Flash */ -#undef CFG_NAND_LEGACY +#undef CONFIG_NAND_LEGACY #define CFG_NAND0_BASE 0x0 /* 0x43100040 */ /* 0x10000000 */ #undef CFG_NAND1_BASE diff --git a/include/configs/eXalion.h b/include/configs/eXalion.h index f8e2c88..6ba0d3f 100644 --- a/include/configs/eXalion.h +++ b/include/configs/eXalion.h @@ -170,7 +170,7 @@ */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CFG_FLASH_INCREMENT 0 /* there is only one bank */ diff --git a/include/configs/ep8248.h b/include/configs/ep8248.h index 8a220b6..ccc0d5d 100644 --- a/include/configs/ep8248.h +++ b/include/configs/ep8248.h @@ -186,7 +186,7 @@ #define CFG_FLASH_BASE 0xFF800000 #define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h index ac5847c..ac68c86 100644 --- a/include/configs/ep82xxm.h +++ b/include/configs/ep82xxm.h @@ -202,7 +202,7 @@ *----------------------------------------------------------------------*/ #define CFG_FLASH_BASE 0xFC000000 #define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector in flinfo */ diff --git a/include/configs/gcplus.h b/include/configs/gcplus.h index 3b1b4ab..1d9c05b 100644 --- a/include/configs/gcplus.h +++ b/include/configs/gcplus.h @@ -169,7 +169,7 @@ #else /* REVISIT: This doesn't work on ADS GCPlus just yet: */ #define CFG_FLASH_CFI 1 /* flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ #define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */ #define CFG_FLASH_INCREMENT 0 /* there is only one bank */ diff --git a/include/configs/gr_cpci_ax2000.h b/include/configs/gr_cpci_ax2000.h index ffe7671..942609f 100644 --- a/include/configs/gr_cpci_ax2000.h +++ b/include/configs/gr_cpci_ax2000.h @@ -208,7 +208,7 @@ /*** CFI CONFIG ***/ #define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI /* Bypass cache when reading regs from flash memory */ #define CFG_FLASH_CFI_BYPASS_READ diff --git a/include/configs/gr_ep2s60.h b/include/configs/gr_ep2s60.h index 7b1d582..ae25fb2 100644 --- a/include/configs/gr_ep2s60.h +++ b/include/configs/gr_ep2s60.h @@ -196,7 +196,7 @@ /*** CFI CONFIG ***/ #define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI /* Bypass cache when reading regs from flash memory */ #define CFG_FLASH_CFI_BYPASS_READ diff --git a/include/configs/gr_xc3s_1500.h b/include/configs/gr_xc3s_1500.h index 6fe2b7c..f019bb4 100644 --- a/include/configs/gr_xc3s_1500.h +++ b/include/configs/gr_xc3s_1500.h @@ -172,7 +172,7 @@ /*** CFI CONFIG ***/ #define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI /* Bypass cache when reading regs from flash memory */ #define CFG_FLASH_CFI_BYPASS_READ diff --git a/include/configs/grsim.h b/include/configs/grsim.h index 3fb8eb3..f880a7b 100644 --- a/include/configs/grsim.h +++ b/include/configs/grsim.h @@ -202,7 +202,7 @@ /*** CFI CONFIG ***/ #define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #endif diff --git a/include/configs/grsim_leon2.h b/include/configs/grsim_leon2.h index 406ce3d..e5af9a6 100644 --- a/include/configs/grsim_leon2.h +++ b/include/configs/grsim_leon2.h @@ -199,7 +199,7 @@ /*** CFI CONFIG ***/ #define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #endif diff --git a/include/configs/hcu4.h b/include/configs/hcu4.h index 13b0358..d99ac53 100644 --- a/include/configs/hcu4.h +++ b/include/configs/hcu4.h @@ -105,7 +105,7 @@ /* Use common CFI driver */ #define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER /* board provides its own flash_init code */ #define CONFIG_FLASH_CFI_LEGACY 1 #define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h index 2080868..54d6721 100644 --- a/include/configs/hcu5.h +++ b/include/configs/hcu5.h @@ -351,7 +351,7 @@ /* Use common CFI driver */ #define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER /* board provides its own flash_init code */ #define CONFIG_FLASH_CFI_LEGACY 1 #define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h index ad7cf76..205f5cc 100644 --- a/include/configs/hmi1001.h +++ b/include/configs/hmi1001.h @@ -155,7 +155,7 @@ #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_CFI_AMD_RESET diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h index ec4ed1e..c476333 100644 --- a/include/configs/imx31_litekit.h +++ b/include/configs/imx31_litekit.h @@ -158,7 +158,7 @@ * CFI FLASH driver setup */ #define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ #define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index 7d6aaa1..237f361 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -164,7 +164,7 @@ * CFI FLASH driver setup */ #define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ #define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h index 6ec92c3..efa2802 100644 --- a/include/configs/inka4x0.h +++ b/include/configs/inka4x0.h @@ -160,7 +160,7 @@ * Flash configuration */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 +#define CONFIG_FLASH_CFI_DRIVER 1 #define CFG_FLASH_BASE 0xffe00000 #define CFG_FLASH_SIZE 0x00200000 #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ diff --git a/include/configs/ixdp425.h b/include/configs/ixdp425.h index b7c43fe..6b73abe 100644 --- a/include/configs/ixdp425.h +++ b/include/configs/ixdp425.h @@ -181,7 +181,7 @@ #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ #define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1 } diff --git a/include/configs/ixdpg425.h b/include/configs/ixdpg425.h index 05dc841..d4e4871 100644 --- a/include/configs/ixdpg425.h +++ b/include/configs/ixdpg425.h @@ -210,7 +210,7 @@ #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ #define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h index c985927..af88a3f 100644 --- a/include/configs/jupiter.h +++ b/include/configs/jupiter.h @@ -191,7 +191,7 @@ #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT diff --git a/include/configs/katmai.h b/include/configs/katmai.h index f07e470..5dcca75 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -54,7 +54,6 @@ #include "amcc-common.h" #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ #undef CONFIG_SHOW_BOOT_PROGRESS /*----------------------------------------------------------------------- @@ -208,7 +207,7 @@ * FLASH related *----------------------------------------------------------------------*/ #define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ diff --git a/include/configs/kb9202.h b/include/configs/kb9202.h index 7dcce83..e775e60 100644 --- a/include/configs/kb9202.h +++ b/include/configs/kb9202.h @@ -153,7 +153,7 @@ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #ifndef __ASSEMBLY__ diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 9c1a3a4..a475f97 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -131,7 +131,7 @@ * FLASH related *----------------------------------------------------------------------*/ #define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ @@ -233,39 +233,124 @@ #define CFG_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE #define CFG_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE #define CFG_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE -#define CFG_SDRAM0_MCOPT1 0x04322000 +#define CFG_SDRAM0_MCOPT1 (SDRAM_MCOPT1_PMU_OPEN | \ + SDRAM_MCOPT1_8_BANKS | \ + SDRAM_MCOPT1_DDR2_TYPE | \ + SDRAM_MCOPT1_QDEP | \ + SDRAM_MCOPT1_DCOO_DISABLED) #define CFG_SDRAM0_MCOPT2 0x00000000 -#define CFG_SDRAM0_MODT0 0x01800000 +#define CFG_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \ + SDRAM_MODT_EB0R_ENABLE) #define CFG_SDRAM0_MODT1 0x00000000 -#define CFG_SDRAM0_CODT 0x0080f837 -#define CFG_SDRAM0_RTR 0x06180000 -#define CFG_SDRAM0_INITPLR0 0xa8380000 -#define CFG_SDRAM0_INITPLR1 0x81900400 -#define CFG_SDRAM0_INITPLR2 0x81020000 -#define CFG_SDRAM0_INITPLR3 0x81030000 -#define CFG_SDRAM0_INITPLR4 0x81010404 -#define CFG_SDRAM0_INITPLR5 0x81000542 -#define CFG_SDRAM0_INITPLR6 0x81900400 -#define CFG_SDRAM0_INITPLR7 0x8D080000 -#define CFG_SDRAM0_INITPLR8 0x8D080000 -#define CFG_SDRAM0_INITPLR9 0x8D080000 -#define CFG_SDRAM0_INITPLR10 0x8D080000 -#define CFG_SDRAM0_INITPLR11 0x81000442 -#define CFG_SDRAM0_INITPLR12 0x81010780 -#define CFG_SDRAM0_INITPLR13 0x81010400 -#define CFG_SDRAM0_INITPLR14 0x00000000 -#define CFG_SDRAM0_INITPLR15 0x00000000 -#define CFG_SDRAM0_RQDC 0x80000038 -#define CFG_SDRAM0_RFDC 0x00000209 -#define CFG_SDRAM0_RDCC 0x40000000 -#define CFG_SDRAM0_DLCR 0x030000a5 -#define CFG_SDRAM0_CLKTR 0x80000000 +#define CFG_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \ + SDRAM_CODT_CKLZ_36OHM | \ + SDRAM_CODT_DQS_1_8_V_DDR2 | \ + SDRAM_CODT_IO_NMODE) +#define CFG_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560) +#define CFG_SDRAM0_INITPLR0 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(80) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP)) +#define CFG_SDRAM0_INITPLR1 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(3) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL)) +#define CFG_SDRAM0_INITPLR2 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL)) +#define CFG_SDRAM0_INITPLR3 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \ + SDRAM_INITPLR_IMA_ENCODE(0)) +#define CFG_SDRAM0_INITPLR4 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \ + JEDEC_MA_EMR_RTT_75OHM)) +#define CFG_SDRAM0_INITPLR5 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \ + JEDEC_MA_MR_CL_DDR2_4_0_CLK | \ + JEDEC_MA_MR_BLEN_4 | \ + JEDEC_MA_MR_DLL_RESET)) +#define CFG_SDRAM0_INITPLR6 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(3) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \ + SDRAM_INITPLR_IBA_ENCODE(0x0) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL)) +#define CFG_SDRAM0_INITPLR7 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(26) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) +#define CFG_SDRAM0_INITPLR8 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(26) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) +#define CFG_SDRAM0_INITPLR9 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(26) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) +#define CFG_SDRAM0_INITPLR10 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(26) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) +#define CFG_SDRAM0_INITPLR11 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \ + JEDEC_MA_MR_CL_DDR2_4_0_CLK | \ + JEDEC_MA_MR_BLEN_4)) +#define CFG_SDRAM0_INITPLR12 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \ + JEDEC_MA_EMR_RDQS_DISABLE | \ + JEDEC_MA_EMR_DQS_DISABLE | \ + JEDEC_MA_EMR_RTT_DISABLED | \ + JEDEC_MA_EMR_ODS_NORMAL)) +#define CFG_SDRAM0_INITPLR13 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \ + JEDEC_MA_EMR_RDQS_DISABLE | \ + JEDEC_MA_EMR_DQS_DISABLE | \ + JEDEC_MA_EMR_RTT_DISABLED | \ + JEDEC_MA_EMR_ODS_NORMAL)) +#define CFG_SDRAM0_INITPLR14 (SDRAM_INITPLR_DISABLE) +#define CFG_SDRAM0_INITPLR15 (SDRAM_INITPLR_DISABLE) +#define CFG_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \ + SDRAM_RQDC_RQFD_ENCODE(56)) +#define CFG_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(521) +#define CFG_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2) +#define CFG_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \ + SDRAM_DLCR_DLCS_CONT_DONE | \ + SDRAM_DLCR_DLCV_ENCODE(165)) +#define CFG_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV) #define CFG_SDRAM0_WRDTR 0x00000000 -#define CFG_SDRAM0_SDTR1 0x80201000 -#define CFG_SDRAM0_SDTR2 0x32204232 -#define CFG_SDRAM0_SDTR3 0x080b0d1a -#define CFG_SDRAM0_MMODE 0x00000442 -#define CFG_SDRAM0_MEMODE 0x00000404 +#define CFG_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \ + SDRAM_SDTR1_RTW_2_CLK | \ + SDRAM_SDTR1_RTRO_1_CLK) +#define CFG_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \ + SDRAM_SDTR2_WTR_2_CLK | \ + SDRAM_SDTR2_XSNR_32_CLK | \ + SDRAM_SDTR2_WPC_4_CLK | \ + SDRAM_SDTR2_RPC_2_CLK | \ + SDRAM_SDTR2_RP_3_CLK | \ + SDRAM_SDTR2_RRD_2_CLK) +#define CFG_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(8) | \ + SDRAM_SDTR3_RC_ENCODE(11) | \ + SDRAM_SDTR3_XCS | \ + SDRAM_SDTR3_RFC_ENCODE(26)) +#define CFG_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \ + SDRAM_MMODE_DCL_DDR2_4_0_CLK | \ + SDRAM_MMODE_BLEN_4) +#define CFG_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_DISABLE | \ + SDRAM_MEMODE_RTT_75OHM) /*----------------------------------------------------------------------- * I2C @@ -290,6 +375,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_M88E1111_PHY 1 #define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ diff --git a/include/configs/korat.h b/include/configs/korat.h index 4ca4ed0..a887446 100644 --- a/include/configs/korat.h +++ b/include/configs/korat.h @@ -110,7 +110,7 @@ * FLASH related */ #define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CONFIG_FLASH_CFI_LEGACY /* Allow hard-coded config for FLASH0 */ #define CFG_FLASH_BANKS_LIST { CFG_FLASH1_ADDR, CFG_FLASH0_ADDR } diff --git a/include/configs/kvme080.h b/include/configs/kvme080.h index 569800a..819e456 100644 --- a/include/configs/kvme080.h +++ b/include/configs/kvme080.h @@ -142,7 +142,7 @@ #define CFG_BOOTMAPSZ (8 << 20) #define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_USE_BUFFER_WRITE #define CFG_FLASH_PROTECTION #define CFG_FLASH_EMPTY_INFO diff --git a/include/configs/linkstation.h b/include/configs/linkstation.h index bc64294..e5a0fb9 100644 --- a/include/configs/linkstation.h +++ b/include/configs/linkstation.h @@ -434,7 +434,7 @@ * FLASH organization */ #define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #undef CFG_FLASH_PROTECTION #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 2f3a066..3d135c4 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -124,7 +124,7 @@ * FLASH related *----------------------------------------------------------------------*/ #define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_FLASH0 0xFC000000 #define CFG_FLASH1 0xF8000000 diff --git a/include/configs/m501sk.h b/include/configs/m501sk.h index e4be1ed..bc94cf4 100644 --- a/include/configs/m501sk.h +++ b/include/configs/m501sk.h @@ -57,7 +57,7 @@ * Hardware drivers */ #define CFG_FLASH_CFI 1 -#define CFG_FLASH_CFI_DRIVER 1 +#define CONFIG_FLASH_CFI_DRIVER 1 #define CFG_ENV_SECT_SIZE 0x20000 #define CFG_FLASH_USE_BUFFER_WRITE #define CFG_FLASH_PROTECTION /*for Intel P30 Flash*/ diff --git a/include/configs/makalu.h b/include/configs/makalu.h index 65b240e..cfc6fdc 100644 --- a/include/configs/makalu.h +++ b/include/configs/makalu.h @@ -125,7 +125,7 @@ * FLASH related *----------------------------------------------------------------------*/ #define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ @@ -223,6 +223,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_M88E1111_PHY 1 #define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII #define CONFIG_PHY_ADDR 6 /* PHY address, See schematics */ #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h index e4c3f72..f512847 100644 --- a/include/configs/mcc200.h +++ b/include/configs/mcc200.h @@ -211,7 +211,7 @@ #define CFG_FLASH_SIZE 0x04000000 #define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } diff --git a/include/configs/mcu25.h b/include/configs/mcu25.h index 4e9645e..6adba96 100644 --- a/include/configs/mcu25.h +++ b/include/configs/mcu25.h @@ -105,7 +105,7 @@ /* Use common CFI driver */ #define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER /* board provides its own flash_init code */ #define CONFIG_FLASH_CFI_LEGACY 1 #define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h index 8dfb9aa..75040fe 100644 --- a/include/configs/mecp5200.h +++ b/include/configs/mecp5200.h @@ -203,7 +203,7 @@ #define CONFIG_ENV_OVERWRITE 1 #endif -#define CFG_FLASH_CFI_DRIVER 1 /* Flash is CFI conformant */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Flash is CFI conformant */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ #define CFG_FLASH_PROTECTION 1 /* use hardware protection */ #if 0 diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h index 59ff96b..5fe3075 100644 --- a/include/configs/mgcoge.h +++ b/include/configs/mgcoge.h @@ -153,7 +153,7 @@ #define CFG_FLASH_BASE 0xFE000000 #define CFG_FLASH_SIZE 32 #define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */ #define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ diff --git a/include/configs/mgsuvd.h b/include/configs/mgsuvd.h index 9cbc9cc..6f1c640 100644 --- a/include/configs/mgsuvd.h +++ b/include/configs/mgsuvd.h @@ -189,7 +189,7 @@ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CFG_FLASH_SIZE 32 #define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ diff --git a/include/configs/ml401.h b/include/configs/ml401.h index 7e0df87..36a42ba 100644 --- a/include/configs/ml401.h +++ b/include/configs/ml401.h @@ -154,7 +154,7 @@ #define CFG_FLASH_BASE XILINX_FLASH_START #define CFG_FLASH_SIZE XILINX_FLASH_SIZE #define CFG_FLASH_CFI 1 - #define CFG_FLASH_CFI_DRIVER 1 + #define CONFIG_FLASH_CFI_DRIVER 1 #define CFG_FLASH_EMPTY_INFO 1 /* ?empty sector */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ diff --git a/include/configs/ml507.h b/include/configs/ml507.h new file mode 100644 index 0000000..c653a51 --- /dev/null +++ b/include/configs/ml507.h @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef __CONFIG_H +#define __CONFIG_H +/* +#define DEBUG +#define ET_DEBUG +*/ + /*CPU*/ +#define CONFIG_XILINX_ML507 1 +#define CONFIG_XILINX_440 1 +#define CONFIG_440 1 +#define CONFIG_4xx 1 +#include "../board/xilinx/ml507/xparameters.h" + +/*Mem Map*/ +#define CFG_SDRAM_BASE 0x0 +#define CFG_SDRAM_SIZE_MB 256 +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN ( 192 * 1024 ) +#define CFG_MALLOC_LEN ( CFG_ENV_SIZE + 128 * 1024 ) + +/*Uart*/ +#define CONFIG_XILINX_UARTLITE +#define CONFIG_BAUDRATE XPAR_UARTLITE_0_BAUDRATE +#define CFG_BAUDRATE_TABLE { XPAR_UARTLITE_0_BAUDRATE } +#define CONFIG_SERIAL_BASE XPAR_UARTLITE_0_BASEADDR + +/*Cmd*/ +#include <config_cmd_default.h> +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_ELF +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_JFFS2 +#define CONFIG_JFFS2_CMDLINE +#undef CONFIG_CMD_I2C +#undef CONFIG_CMD_DTT +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_PING +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_IMLS + +/*Env*/ +#define CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SIZE 0x20000 +#define CFG_ENV_SECT_SIZE 0x20000 +#define CFG_ENV_OFFSET 0x340000 +#define CFG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CFG_ENV_OFFSET) + +/*Misc*/ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "board:/# " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE ( CFG_CBSIZE + sizeof( CFG_PROMPT ) + 16 ) +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ +#define CFG_LOAD_ADDR 0x00400000 /* default load address */ +#define CFG_EXTBDINFO 1 /* Extended board_into (bd_t) */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_CMDLINE_EDITING /* add command line history */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_LOOPW /* enable loopw command */ +#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE /* include version env variable */ +#define CFG_CONSOLE_INFO_QUIET /* don't print console @ startup */ +#define CFG_HUSH_PARSER /* Use the HUSH parser */ +#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ +#define CFG_BOOTMAPSZ ( 8 << 20 ) /* Initial Memory map for Linux */ +#define CONFIG_PREBOOT "echo U-Boot is up and runnining;" + +/*Stack*/ +#define CFG_INIT_RAM_ADDR 0x800000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET ( CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE ) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +/*Speed*/ +#define CONFIG_SYS_CLK_FREQ XPAR_CORE_CLOCK_FREQ_HZ + +/*Flash*/ +#define CFG_FLASH_BASE XPAR_FLASH_MEM0_BASEADDR +#define CFG_FLASH_SIZE (32*1024*1024) +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 +#define CFG_FLASH_EMPTY_INFO 1 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 259 +#define CFG_FLASH_PROTECTION +#define MTDIDS_DEFAULT "nor0=ml507-flash" +#define MTDPARTS_DEFAULT "mtdparts=ml507-flash:-(user)" + + +#endif /* __CONFIG_H */ diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index 3d1eafe..f2a35ee 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -263,7 +263,7 @@ * Flash configuration */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 +#define CONFIG_FLASH_CFI_DRIVER 1 #define CFG_FLASH_BASE 0xff000000 #define CFG_FLASH_SIZE 0x01000000 #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index 2f24967..d379b1f 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -374,7 +374,7 @@ #define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */ #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, /* CFG_FLASH_BASE2 */ } -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #define CFG_WRITE_SWAPPED_DATA diff --git a/include/configs/mpr2.h b/include/configs/mpr2.h index 0fc0b97..3df6e39 100644 --- a/include/configs/mpr2.h +++ b/include/configs/mpr2.h @@ -67,7 +67,7 @@ /* Flash */ #define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_BASE 0xA0000000 #define CFG_MAX_FLASH_SECT 256 @@ -86,7 +86,7 @@ #define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER) /* UART */ -#define CFG_SCIF_CONSOLE 1 +#define CONFIG_SCIF_CONSOLE 1 #define CONFIG_CONS_SCIF0 1 #endif /* __MPR2_H */ diff --git a/include/configs/ms7720se.h b/include/configs/ms7720se.h index 5e79a27..1c3d277 100644 --- a/include/configs/ms7720se.h +++ b/include/configs/ms7720se.h @@ -63,7 +63,7 @@ #define CFG_BAUDRATE_TABLE { 115200 } /* SCIF */ -#define CFG_SCIF_CONSOLE 1 +#define CONFIG_SCIF_CONSOLE 1 #define CONFIG_CONS_SCIF0 1 #define CFG_MEMTEST_START MS7720SE_SDRAM_BASE @@ -82,7 +82,7 @@ /* FLASH */ #define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #undef CFG_FLASH_QUIET_TEST #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h index 7298e55..3809e71 100644 --- a/include/configs/ms7722se.h +++ b/include/configs/ms7722se.h @@ -62,7 +62,7 @@ #define CFG_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */ /* SCIF */ -#define CFG_SCIF_CONSOLE 1 +#define CONFIG_SCIF_CONSOLE 1 #define CONFIG_CONS_SCIF0 1 #undef CFG_CONSOLE_INFO_QUIET /* Suppress display of console information at boot */ #undef CFG_CONSOLE_OVERWRITE_ROUTINE @@ -90,7 +90,7 @@ /* FLASH */ #define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #undef CFG_FLASH_QUIET_TEST #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ diff --git a/include/configs/ms7750se.h b/include/configs/ms7750se.h index 3000c77..4356a67 100644 --- a/include/configs/ms7750se.h +++ b/include/configs/ms7750se.h @@ -42,7 +42,7 @@ #define CONFIG_CMD_FLASH #define CONFIG_CMD_ENV -#define CFG_SCIF_CONSOLE 1 +#define CONFIG_SCIF_CONSOLE 1 #define CONFIG_BAUDRATE 38400 #define CONFIG_CONS_SCIF1 1 #define BOARD_LATE_INIT 1 @@ -86,7 +86,7 @@ #define CFG_RX_ETH_BUFFER (8) #define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #undef CFG_FLASH_CFI_BROKEN_TABLE #undef CFG_FLASH_QUIET_TEST #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ diff --git a/include/configs/munices.h b/include/configs/munices.h index e0046ec..cea2834 100644 --- a/include/configs/munices.h +++ b/include/configs/munices.h @@ -133,7 +133,7 @@ */ #define CFG_FLASH_BASE 0xFF000000 #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_SIZE 0x01000000 /* 16 MByte */ diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h index 37ba872..9ede764 100644 --- a/include/configs/mx31ads.h +++ b/include/configs/mx31ads.h @@ -185,7 +185,7 @@ * CFI FLASH driver setup */ #define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ #define CONFIG_FLASH_SPANSION_S29WS_N 1 /* A non-standard buffered write algorithm */ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ #define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ diff --git a/include/configs/ns9750dev.h b/include/configs/ns9750dev.h index f30cb46..746a56e 100644 --- a/include/configs/ns9750dev.h +++ b/include/configs/ns9750dev.h @@ -56,7 +56,7 @@ /* * Hardware drivers */ -#define CFG_NS9750_UART 1 /* use on-chip UART */ +#define CONFIG_NS9750_UART 1 /* use on-chip UART */ #define CONFIG_DRIVER_NS9750_ETHERNET 1 /* use on-chip ethernet */ /* diff --git a/include/configs/omap1510inn.h b/include/configs/omap1510inn.h index 0be46ea..46b30e0 100644 --- a/include/configs/omap1510inn.h +++ b/include/configs/omap1510inn.h @@ -179,7 +179,7 @@ * FLASH driver setup */ #define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ #define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h index 88a3f6e..afdcba4 100644 --- a/include/configs/omap2420h4.h +++ b/include/configs/omap2420h4.h @@ -151,7 +151,7 @@ /* * Board NAND Info. */ -#define CFG_NAND_LEGACY +#define CONFIG_NAND_LEGACY #define CFG_NAND_ADDR 0x04000000 /* physical address to access nand at CS0*/ #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ @@ -283,7 +283,7 @@ * CFI FLASH driver setup */ #define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ #define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ diff --git a/include/configs/omap5912osk.h b/include/configs/omap5912osk.h index e3bde4f..1c44ce0 100644 --- a/include/configs/omap5912osk.h +++ b/include/configs/omap5912osk.h @@ -174,7 +174,7 @@ * FLASH driver setup */ #define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ #define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h index 0913b14..33a94bc 100644 --- a/include/configs/p3mx.h +++ b/include/configs/p3mx.h @@ -128,7 +128,7 @@ * FLASH related *----------------------------------------------------------------------*/ #define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h index 82f2391..ac0d83a 100644 --- a/include/configs/p3p440.h +++ b/include/configs/p3p440.h @@ -279,7 +279,7 @@ * FLASH related *----------------------------------------------------------------------*/ #define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_FLASH_BANKS_LIST { CFG_FLASH3, CFG_FLASH2, CFG_FLASH1, CFG_FLASH0 } diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h index aca70dc..889207a 100644 --- a/include/configs/pdnb3.h +++ b/include/configs/pdnb3.h @@ -218,7 +218,7 @@ */ #if defined(CONFIG_SCPU) #define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */ #endif diff --git a/include/configs/ppmc8260.h b/include/configs/ppmc8260.h index dee6643..6f1195b 100644 --- a/include/configs/ppmc8260.h +++ b/include/configs/ppmc8260.h @@ -452,7 +452,7 @@ */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CFG_FLASH_INCREMENT 0 /* there is only one bank */ diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h index a2f3650..179ff7a 100644 --- a/include/configs/pxa255_idp.h +++ b/include/configs/pxa255_idp.h @@ -333,7 +333,7 @@ * FLASH and environment organization */ #define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER 1 +#define CONFIG_FLASH_CFI_DRIVER 1 #define CFG_MONITOR_BASE 0 #define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index 3dfd218..19e627b 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -146,7 +146,7 @@ #define CFG_MAX_FLASH_BANKS 1 #define CFG_MAX_FLASH_SECT 128 #define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CFG_FLASH_CFI_DRIVER 1 +#define CONFIG_FLASH_CFI_DRIVER 1 #define CFG_FLASH_USE_BUFFER_WRITE 1 #define CFG_ENV_IS_IN_FLASH 1 diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h index 622a5d4..d464734 100644 --- a/include/configs/quad100hd.h +++ b/include/configs/quad100hd.h @@ -182,7 +182,7 @@ * FLASH organization */ #define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } diff --git a/include/configs/quantum.h b/include/configs/quantum.h index cc261c3..34a1ea6 100644 --- a/include/configs/quantum.h +++ b/include/configs/quantum.h @@ -170,13 +170,13 @@ #define CFG_FLASH_BASE 0xFF000000 #if 1 - #define CFG_FLASH_CFI_DRIVER + #define CONFIG_FLASH_CFI_DRIVER #else - #undef CFG_FLASH_CFI_DRIVER + #undef CONFIG_FLASH_CFI_DRIVER #endif -#ifdef CFG_FLASH_CFI_DRIVER +#ifdef CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI 1 #undef CFG_FLASH_USE_BUFFER_WRITE #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index e269336..06ede3e 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -26,7 +26,7 @@ #define CONFIG_DOS_PARTITION /* SCIF */ -#define CFG_SCIF_CONSOLE 1 +#define CONFIG_SCIF_CONSOLE 1 #define CONFIG_BAUDRATE 115200 #define CONFIG_CONS_SCIF1 1 #define BOARD_LATE_INIT 1 @@ -65,7 +65,7 @@ * NOR Flash ( Spantion S29GL256P ) */ #define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_BASE (0xA0000000) #define CFG_MAX_FLASH_BANKS (1) #define CFG_MAX_FLASH_SECT 256 diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h index 4c82c5a..77881e7 100644 --- a/include/configs/r7780mp.h +++ b/include/configs/r7780mp.h @@ -49,7 +49,7 @@ #define CONFIG_CMD_EXT2 #define CONFIG_DOS_PARTITION -#define CFG_SCIF_CONSOLE 1 +#define CONFIG_SCIF_CONSOLE 1 #define CONFIG_BAUDRATE 115200 #define CONFIG_CONS_SCIF0 1 @@ -106,7 +106,7 @@ #define CFG_RX_ETH_BUFFER (8) #define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #undef CFG_FLASH_CFI_BROKEN_TABLE #undef CFG_FLASH_QUIET_TEST /* print 'E' for empty sector on flinfo */ diff --git a/include/configs/redwood.h b/include/configs/redwood.h new file mode 100644 index 0000000..32ed574 --- /dev/null +++ b/include/configs/redwood.h @@ -0,0 +1,186 @@ +/* + * Configuration for AMCC 460SX Ref (redwood) + * + * (C) Copyright 2008 + * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_440 1 /* ... PPC460 family */ +#define CONFIG_460SX 1 /* ... PPC460 family */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +/*----------------------------------------------------------------------- + * Include common defines/options for all AMCC boards + *----------------------------------------------------------------------*/ +#define CONFIG_HOSTNAME redwood + +#include "amcc-common.h" + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */ +#define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */ +#define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */ + +#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ + +#define CFG_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */ +#define CFG_PCIE0_MEMBASE 0x90000000 /* mapped PCIe memory */ +#define CFG_PCIE1_MEMBASE 0xa0000000 /* mapped PCIe memory */ +#define CFG_PCIE_MEMSIZE 0x01000000 + +#define CFG_PCIE0_XCFGBASE 0xb0000000 +#define CFG_PCIE1_XCFGBASE 0xb2000000 +#define CFG_PCIE2_XCFGBASE 0xb4000000 +#define CFG_PCIE0_CFGBASE 0xb6000000 +#define CFG_PCIE1_CFGBASE 0xb8000000 +#define CFG_PCIE2_CFGBASE 0xba000000 + +/* PCIe mapped UTL registers */ +#define CFG_PCIE0_REGBASE 0xd0000000 +#define CFG_PCIE1_REGBASE 0xd0010000 +#define CFG_PCIE2_REGBASE 0xd0020000 + +/* System RAM mapped to PCI space */ +#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) + +#define CFG_FPGA_BASE 0xe2000000 /* epld */ +#define CFG_OPER_FLASH 0xe7000000 /* SRAM - OPER Flash */ + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer (placed in internal SRAM) + *----------------------------------------------------------------------*/ +#define CFG_TEMP_STACK_OCM 1 +#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE +#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ + +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) +#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ +#define CONFIG_DDR_ECC 1 /* with ECC support */ + +#define CFG_SPD_MAX_DIMMS 2 + +/* SPD i2c spd addresses */ +#define SPD_EEPROM_ADDRESS {IIC0_DIMM0_ADDR, IIC0_DIMM1_ADDR} +#define IIC0_DIMM0_ADDR 0x53 +#define IIC0_DIMM1_ADDR 0x52 + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CFG_I2C_SPEED 400000 /* I2C speed */ + +#define IIC0_BOOTPROM_ADDR 0x50 +#define IIC0_ALT_BOOTPROM_ADDR 0x54 + +/* Don't probe these addrs */ +#define CFG_I2C_NOPROBES {0x50, 0x52, 0x53, 0x54} + +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +#undef CFG_ENV_IS_IN_NVRAM /* ... not in NVRAM */ +#define CFG_ENV_IS_IN_FLASH 1 /* Environment uses flash */ +#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ + CONFIG_AMCC_DEF_ENV_NAND_UPD \ + "kernel_addr=fc000000\0" \ + "fdt_addr=fc1e0000\0" \ + "ramdisk_addr=fc200000\0" \ + "" + +/*----------------------------------------------------------------------------+ +| Commands in addition to amcc-common.h ++----------------------------------------------------------------------------*/ +#define CONFIG_CMD_SDRAM + +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_RESET_DELAY 1000 +#define CONFIG_M88E1141_PHY 1 /* Enable phy */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ +#define CONFIG_PHY1_ADDR 1 /* PHY address, See schematics */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */ + +#define CFG_MAX_FLASH_BANKS 3 /* number of banks */ +#define CFG_MAX_FLASH_SECT 256 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_ADDR 0xfffa0000 +#define CFG_ENV_SIZE 0x10000 /* Size of Environment vars */ +#endif /* CFG_ENV_IS_IN_FLASH */ + +/*---------------------------------------------------------------------------*/ + +#endif /* __CONFIG_H */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 7481556..261229c 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -133,7 +133,7 @@ * FLASH on the Local Bus */ #define CFG_FLASH_CFI /* use the Common Flash Interface */ -#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CFG_FLASH_BASE 0xFF800000 /* start of FLASH */ #define CFG_FLASH_SIZE 8 /* flash size in MB */ /* #define CFG_FLASH_USE_BUFFER_WRITE */ diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 358fc02..b4238e5 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -178,7 +178,7 @@ #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #define CFG_FLASH_EMPTY_INFO diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index 6345cce..b244eef 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -290,7 +290,7 @@ */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #if 0 #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ #define CFG_FLASH_PROTECTION /* use hardware protection */ diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 3cd9ff8..efc787e 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -58,6 +58,8 @@ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE +#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ + #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/ #undef CONFIG_DDR_DLL /* possible DLL fix needed */ #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ @@ -221,7 +223,7 @@ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #define CFG_WRITE_SWAPPED_DATA #define CFG_FLASH_EMPTY_INFO diff --git a/include/configs/sc3.h b/include/configs/sc3.h index 87311ea..659f74e 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -397,7 +397,7 @@ extern unsigned long offsetOfEnvironment; #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ #define CFG_FLASH_CFI /* flash is CFI compat. */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */ #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h index 0e830b8..e29655e 100644 --- a/include/configs/sc520_cdp.h +++ b/include/configs/sc520_cdp.h @@ -178,7 +178,7 @@ #define CFG_SATA_MAXBUS 2 /*Max Sata buses supported */ #define CFG_SATA_DEVS_PER_BUS 2 /*Max no. of devices per bus/port */ #define CFG_SATA_MAX_DEVICE (CFG_SATA_MAXBUS* CFG_SATA_DEVS_PER_BUS) -#define CFG_ATA_PIIX 1 /*Supports ata_piix driver */ +#define CONFIG_ATA_PIIX 1 /*Supports ata_piix driver */ /************************************************************ * DISK Partition support diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index f4eefae..18675c2 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -123,7 +123,7 @@ * FLASH related */ #define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } @@ -422,12 +422,12 @@ /* GPIO Core 1 */ \ {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \ {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ -{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ -{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \ -{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \ -{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ -{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_8PIN_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_CTS_N EBC_DATA(0) UART3_SIN*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_8PIN_DTR_N UART1_SOUT */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_8PIN_RI_N UART1_SIN */ \ {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \ {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \ {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \ diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h index 7713eaa..1306702 100644 --- a/include/configs/sh7763rdp.h +++ b/include/configs/sh7763rdp.h @@ -38,7 +38,11 @@ #define CONFIG_CMD_SDRAM #define CONFIG_CMD_FLASH #define CONFIG_CMD_MEMORY +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING #define CONFIG_CMD_ENV +#define CONFIG_CMD_NFS +#define CONFIG_CMD_JFFS2 #define CONFIG_BOOTDELAY -1 #define CONFIG_BOOTARGS "console=ttySC2,115200 root=1f01" @@ -48,7 +52,7 @@ #undef CONFIG_SHOW_BOOT_PROGRESS /* SCIF */ -#define CFG_SCIF_CONSOLE 1 +#define CONFIG_SCIF_CONSOLE 1 #define CONFIG_BAUDRATE 115200 #define CONFIG_CONS_SCIF2 1 @@ -85,7 +89,7 @@ #define CFG_BOOTMAPSZ (8 * 1024 * 1024) #define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #undef CFG_FLASH_QUIET_TEST #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ /* Timeout for Flash erase operations (in ms) */ @@ -113,4 +117,9 @@ #define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */ #define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER) +/* Ether */ +#define CONFIG_SH_ETHER 1 +#define CONFIG_SH_ETHER_USE_PORT (1) +#define CONFIG_SH_ETHER_PHY_ADDR (0x01) + #endif /* __SH7763RDP_H */ diff --git a/include/configs/smmaco4.h b/include/configs/smmaco4.h index 3e47eb8..1d202d4 100644 --- a/include/configs/smmaco4.h +++ b/include/configs/smmaco4.h @@ -196,7 +196,7 @@ /* use CFI flash driver if no module variant is spezified */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 1627413..8a64942 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -139,7 +139,7 @@ #define CFG_OR1_PRELIM 0xfe000ff7 /* 32MB Flash */ #define CFG_FLASH_CFI /* flash is CFI compat. */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */ #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ diff --git a/include/configs/sorcery.h b/include/configs/sorcery.h index 18f5533..f4e4608 100644 --- a/include/configs/sorcery.h +++ b/include/configs/sorcery.h @@ -189,7 +189,7 @@ #define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */ #define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, \ CFG_FLASH_BASE+0x04000000 } /* two banks */ diff --git a/include/configs/spc1920.h b/include/configs/spc1920.h index f46c464..daaa23f 100644 --- a/include/configs/spc1920.h +++ b/include/configs/spc1920.h @@ -180,7 +180,7 @@ */ #define CFG_FLASH_BASE 0xFE000000 #define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ #define CFG_MAX_FLASH_SECT 128 /* Max num of sects on one chip */ diff --git a/include/configs/spieval.h b/include/configs/spieval.h index 69d2d67..93798a4 100644 --- a/include/configs/spieval.h +++ b/include/configs/spieval.h @@ -287,7 +287,7 @@ /* use CFI flash driver if no module variant is spezified */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */ diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index a1e9789..4f1c156 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -98,7 +98,7 @@ #define CFG_OR0_PRELIM (CFG_FLASH_BASE | 0x0FF7) #define CFG_FLASH_CFI 1 -#define CFG_FLASH_CFI_DRIVER 1 +#define CONFIG_FLASH_CFI_DRIVER 1 #undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */ #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h index fcafba5..37a52cf 100644 --- a/include/configs/stxxtc.h +++ b/include/configs/stxxtc.h @@ -213,7 +213,7 @@ #define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE #define CFG_FLASH_CFI 1 -#define CFG_FLASH_CFI_DRIVER 1 +#define CONFIG_FLASH_CFI_DRIVER 1 #undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */ #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ @@ -449,7 +449,7 @@ /****************************************************************/ /* NAND */ -#define CFG_NAND_LEGACY +#define CONFIG_NAND_LEGACY #define CFG_NAND_BASE NAND_BASE #define CONFIG_MTD_NAND_ECC_JFFS2 #define CONFIG_MTD_NAND_VERIFY_WRITE diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h index 70336b5..bbbfa15 100644 --- a/include/configs/svm_sc8xx.h +++ b/include/configs/svm_sc8xx.h @@ -151,7 +151,7 @@ #define CONFIG_CMD_DATE -#define CFG_NAND_LEGACY +#define CONFIG_NAND_LEGACY /* * Miscellaneous configurable options diff --git a/include/configs/taishan.h b/include/configs/taishan.h index ba42192..81133bb 100644 --- a/include/configs/taishan.h +++ b/include/configs/taishan.h @@ -89,7 +89,7 @@ * FLASH related *----------------------------------------------------------------------*/ #define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h index f77dd14..6367f87 100644 --- a/include/configs/trizepsiv.h +++ b/include/configs/trizepsiv.h @@ -293,7 +293,7 @@ */ #define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER 1 +#define CONFIG_FLASH_CFI_DRIVER 1 #define CFG_MONITOR_BASE 0 #define CFG_MONITOR_LEN 0x40000 diff --git a/include/configs/uc100.h b/include/configs/uc100.h index e74b1bb..106e6f2 100644 --- a/include/configs/uc100.h +++ b/include/configs/uc100.h @@ -230,7 +230,7 @@ * FLASH organization */ #define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ diff --git a/include/configs/uc101.h b/include/configs/uc101.h index 042750e..a186188 100644 --- a/include/configs/uc101.h +++ b/include/configs/uc101.h @@ -168,7 +168,7 @@ #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_CFI_AMD_RESET diff --git a/include/configs/v38b.h b/include/configs/v38b.h index c203522..3574548 100644 --- a/include/configs/v38b.h +++ b/include/configs/v38b.h @@ -201,7 +201,7 @@ * Flash configuration - use CFI driver */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #define CFG_FLASH_CFI_AMD_RESET 1 #define CFG_FLASH_BASE 0xFF000000 #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ diff --git a/include/configs/virtlab2.h b/include/configs/virtlab2.h index 6bb075d..1a125f1 100644 --- a/include/configs/virtlab2.h +++ b/include/configs/virtlab2.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2006 + * (C) Copyright 2006-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -37,10 +37,6 @@ #define CONFIG_VIRTLAB2 1 /* ...on a virtlab2 module */ #define CONFIG_TQM8xxL 1 -#ifdef CONFIG_LCD /* with LCD controller ? */ -#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ -#endif - #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #undef CONFIG_8xx_CONS_SMC2 #undef CONFIG_8xx_CONS_NONE @@ -70,9 +66,17 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM823L/uImage\0" \ - "kernel_addr=40040000\0" \ - "ramdisk_addr=40100000\0" \ + "hostname=virtlab2\0" \ + "bootfile=virtlab2/uImage\0" \ + "fdt_addr=40040000\0" \ + "kernel_addr=40060000\0" \ + "ramdisk_addr=40200000\0" \ + "u-boot=virtlab2/u-image.bin\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=prot off 40000000 +${filesize};" \ + "era 40000000 +${filesize};" \ + "cp.b 200000 40000000 ${filesize};" \ + "sete filesize;save\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -114,6 +118,7 @@ #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP #define CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP @@ -122,15 +127,16 @@ #endif +#define CONFIG_NETCONSOLE + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif @@ -196,8 +202,8 @@ /* use CFI flash driver */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size } #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_USE_BUFFER_WRITE 1 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ @@ -214,6 +220,18 @@ #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- + * Dynamic MTD partition support + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" + +#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ + "128k(dtb)," \ + "1664k(kernel)," \ + "2m(rootfs)," \ + "4m(data)" + +/*----------------------------------------------------------------------- * Hardware Information Block */ #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ diff --git a/include/configs/voiceblue.h b/include/configs/voiceblue.h index 8c827af..20917ee 100644 --- a/include/configs/voiceblue.h +++ b/include/configs/voiceblue.h @@ -60,7 +60,7 @@ * FLASH organization */ #define CFG_FLASH_CFI /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER /* Use the common driver */ +#define CONFIG_FLASH_CFI_DRIVER /* Use the common driver */ #define CFG_MAX_FLASH_BANKS 1 #define CFG_FLASH_BASE PHYS_FLASH_1 diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index 891b515..cb2042c 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -105,7 +105,7 @@ * FLASH related *----------------------------------------------------------------------*/ #define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ diff --git a/include/configs/zeus.h b/include/configs/zeus.h index cd120df..b50cba5 100644 --- a/include/configs/zeus.h +++ b/include/configs/zeus.h @@ -210,7 +210,7 @@ * FLASH organization */ #define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } diff --git a/include/dataflash.h b/include/dataflash.h index 80f0633..de04139 100644 --- a/include/dataflash.h +++ b/include/dataflash.h @@ -135,9 +135,9 @@ struct dataflash_addr { int cs; }; /*-------------------------------------------------------------------------------------------------*/ - #define AT45DB161 0x2c #define AT45DB021 0x14 +#define AT45DB081 0x24 #define AT45DB321 0x34 #define AT45DB642 0x3c #define AT45DB128 0x10 diff --git a/include/image.h b/include/image.h index 46138fa..4b9c582 100644 --- a/include/image.h +++ b/include/image.h @@ -220,7 +220,6 @@ typedef struct bootm_headers { #endif int verify; /* getenv("verify")[0] != 'n' */ - int autostart; /* getenv("autostart")[0] != 'n' */ struct lmb *lmb; /* for memory mgmt */ } bootm_headers_t; diff --git a/include/linux/err.h b/include/linux/err.h new file mode 100644 index 0000000..4e08c4f --- /dev/null +++ b/include/linux/err.h @@ -0,0 +1,45 @@ +#ifndef _LINUX_ERR_H +#define _LINUX_ERR_H + +/* XXX U-BOOT XXX */ +#if 0 +#include <linux/compiler.h> +#else +#include <linux/mtd/compat.h> +#endif + +#include <asm/errno.h> + + +/* + * Kernel pointers have redundant information, so we can use a + * scheme where we can return either an error code or a dentry + * pointer with the same return value. + * + * This should be a per-architecture thing, to allow different + * error and pointer decisions. + */ +#define MAX_ERRNO 4095 + +#ifndef __ASSEMBLY__ + +#define IS_ERR_VALUE(x) unlikely((x) >= (unsigned long)-MAX_ERRNO) + +static inline void *ERR_PTR(long error) +{ + return (void *) error; +} + +static inline long PTR_ERR(const void *ptr) +{ + return (long) ptr; +} + +static inline long IS_ERR(const void *ptr) +{ + return IS_ERR_VALUE((unsigned long)ptr); +} + +#endif + +#endif /* _LINUX_ERR_H */ diff --git a/include/linux/mtd/blktrans.h b/include/linux/mtd/blktrans.h new file mode 100644 index 0000000..d1ded51 --- /dev/null +++ b/include/linux/mtd/blktrans.h @@ -0,0 +1,81 @@ +/* + * $Id: blktrans.h,v 1.6 2005/11/07 11:14:54 gleixner Exp $ + * + * (C) 2003 David Woodhouse <dwmw2@infradead.org> + * + * Interface to Linux block layer for MTD 'translation layers'. + * + */ + +#ifndef __MTD_TRANS_H__ +#define __MTD_TRANS_H__ + +/* XXX U-BOOT XXX */ +#if 0 +#include <linux/mutex.h> +#else +#include <linux/list.h> +#endif + +struct hd_geometry; +struct mtd_info; +struct mtd_blktrans_ops; +struct file; +struct inode; + +struct mtd_blktrans_dev { + struct mtd_blktrans_ops *tr; + struct list_head list; + struct mtd_info *mtd; +/* XXX U-BOOT XXX */ +#if 0 + struct mutex lock; +#endif + int devnum; + unsigned long size; + int readonly; + void *blkcore_priv; /* gendisk in 2.5, devfs_handle in 2.4 */ +}; + +struct blkcore_priv; /* Differs for 2.4 and 2.5 kernels; private */ + +struct mtd_blktrans_ops { + char *name; + int major; + int part_bits; + int blksize; + int blkshift; + + /* Access functions */ + int (*readsect)(struct mtd_blktrans_dev *dev, + unsigned long block, char *buffer); + int (*writesect)(struct mtd_blktrans_dev *dev, + unsigned long block, char *buffer); + + /* Block layer ioctls */ + int (*getgeo)(struct mtd_blktrans_dev *dev, struct hd_geometry *geo); + int (*flush)(struct mtd_blktrans_dev *dev); + + /* Called with mtd_table_mutex held; no race with add/remove */ + int (*open)(struct mtd_blktrans_dev *dev); + int (*release)(struct mtd_blktrans_dev *dev); + + /* Called on {de,}registration and on subsequent addition/removal + of devices, with mtd_table_mutex held. */ + void (*add_mtd)(struct mtd_blktrans_ops *tr, struct mtd_info *mtd); + void (*remove_dev)(struct mtd_blktrans_dev *dev); + + struct list_head devs; + struct list_head list; + struct module *owner; + + struct mtd_blkcore_priv *blkcore_priv; +}; + +extern int register_mtd_blktrans(struct mtd_blktrans_ops *tr); +extern int deregister_mtd_blktrans(struct mtd_blktrans_ops *tr); +extern int add_mtd_blktrans_dev(struct mtd_blktrans_dev *dev); +extern int del_mtd_blktrans_dev(struct mtd_blktrans_dev *dev); + + +#endif /* __MTD_TRANS_H__ */ diff --git a/include/linux/mtd/compat.h b/include/linux/mtd/compat.h index fe55087..9036b74 100644 --- a/include/linux/mtd/compat.h +++ b/include/linux/mtd/compat.h @@ -18,7 +18,12 @@ #define KERN_DEBUG #define kmalloc(size, flags) malloc(size) -#define kfree(ptr) free(ptr) +#define kzalloc(size, flags) calloc(size, 1) +#define vmalloc(size) malloc(size) +#define kfree(ptr) free(ptr) +#define vfree(ptr) free(ptr) + +#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c)) /* * ..and if you can't take the strict diff --git a/include/linux/mtd/doc2000.h b/include/linux/mtd/doc2000.h index 29f6767..12de284 100644 --- a/include/linux/mtd/doc2000.h +++ b/include/linux/mtd/doc2000.h @@ -1,15 +1,23 @@ - -/* Linux driver for Disk-On-Chip 2000 */ -/* (c) 1999 Machine Vision Holdings, Inc. */ -/* Author: David Woodhouse <dwmw2@mvhi.com> */ -/* $Id: doc2000.h,v 1.15 2001/09/19 00:22:15 dwmw2 Exp $ */ +/* + * Linux driver for Disk-On-Chip devices + * + * Copyright (C) 1999 Machine Vision Holdings, Inc. + * Copyright (C) 2001-2003 David Woodhouse <dwmw2@infradead.org> + * Copyright (C) 2002-2003 Greg Ungerer <gerg@snapgear.com> + * Copyright (C) 2002-2003 SnapGear Inc + * + * $Id: doc2000.h,v 1.25 2005/11/07 11:14:54 gleixner Exp $ + * + * Released under GPL + */ #ifndef __MTD_DOC2000_H__ #define __MTD_DOC2000_H__ -struct DiskOnChip; - -#include <linux/mtd/nftl.h> +#include <linux/mtd/mtd.h> +#if 0 +#include <linux/mutex.h> +#endif #define DoC_Sig1 0 #define DoC_Sig2 1 @@ -40,10 +48,58 @@ struct DiskOnChip; #define DoC_Mil_CDSN_IO 0x0800 #define DoC_2k_CDSN_IO 0x1800 -#define ReadDOC_(adr, reg) ((volatile unsigned char)(*(volatile __u8 *)(((unsigned long)adr)+((reg))))) -#define WriteDOC_(d, adr, reg) do{ *(volatile __u8 *)(((unsigned long)adr)+((reg))) = (__u8)d; eieio();} while(0) - -#define DOC_IOREMAP_LEN 0x4000 +#define DoC_Mplus_NOP 0x1002 +#define DoC_Mplus_AliasResolution 0x1004 +#define DoC_Mplus_DOCControl 0x1006 +#define DoC_Mplus_AccessStatus 0x1008 +#define DoC_Mplus_DeviceSelect 0x1008 +#define DoC_Mplus_Configuration 0x100a +#define DoC_Mplus_OutputControl 0x100c +#define DoC_Mplus_FlashControl 0x1020 +#define DoC_Mplus_FlashSelect 0x1022 +#define DoC_Mplus_FlashCmd 0x1024 +#define DoC_Mplus_FlashAddress 0x1026 +#define DoC_Mplus_FlashData0 0x1028 +#define DoC_Mplus_FlashData1 0x1029 +#define DoC_Mplus_ReadPipeInit 0x102a +#define DoC_Mplus_LastDataRead 0x102c +#define DoC_Mplus_LastDataRead1 0x102d +#define DoC_Mplus_WritePipeTerm 0x102e +#define DoC_Mplus_ECCSyndrome0 0x1040 +#define DoC_Mplus_ECCSyndrome1 0x1041 +#define DoC_Mplus_ECCSyndrome2 0x1042 +#define DoC_Mplus_ECCSyndrome3 0x1043 +#define DoC_Mplus_ECCSyndrome4 0x1044 +#define DoC_Mplus_ECCSyndrome5 0x1045 +#define DoC_Mplus_ECCConf 0x1046 +#define DoC_Mplus_Toggle 0x1046 +#define DoC_Mplus_DownloadStatus 0x1074 +#define DoC_Mplus_CtrlConfirm 0x1076 +#define DoC_Mplus_Power 0x1fff + +/* How to access the device? + * On ARM, it'll be mmap'd directly with 32-bit wide accesses. + * On PPC, it's mmap'd and 16-bit wide. + * Others use readb/writeb + */ +#if defined(__arm__) +#define ReadDOC_(adr, reg) ((unsigned char)(*(volatile __u32 *)(((unsigned long)adr)+((reg)<<2)))) +#define WriteDOC_(d, adr, reg) do{ *(volatile __u32 *)(((unsigned long)adr)+((reg)<<2)) = (__u32)d; wmb();} while(0) +#define DOC_IOREMAP_LEN 0x8000 +#elif defined(__ppc__) +#define ReadDOC_(adr, reg) ((unsigned char)(*(volatile __u16 *)(((unsigned long)adr)+((reg)<<1)))) +#define WriteDOC_(d, adr, reg) do{ *(volatile __u16 *)(((unsigned long)adr)+((reg)<<1)) = (__u16)d; wmb();} while(0) +#define DOC_IOREMAP_LEN 0x4000 +#else +#define ReadDOC_(adr, reg) readb((void __iomem *)(adr) + (reg)) +#define WriteDOC_(d, adr, reg) writeb(d, (void __iomem *)(adr) + (reg)) +#define DOC_IOREMAP_LEN 0x2000 + +#endif + +#if defined(__i386__) || defined(__x86_64__) +#define USE_MEMCPY +#endif /* These are provided to directly use the DoC_xxx defines */ #define ReadDOC(adr, reg) ReadDOC_(adr,DoC_##reg) @@ -54,14 +110,21 @@ struct DiskOnChip; #define DOC_MODE_RESERVED1 2 #define DOC_MODE_RESERVED2 3 -#define DOC_MODE_MDWREN 4 #define DOC_MODE_CLR_ERR 0x80 +#define DOC_MODE_RST_LAT 0x10 +#define DOC_MODE_BDECT 0x08 +#define DOC_MODE_MDWREN 0x04 -#define DOC_ChipID_UNKNOWN 0x00 #define DOC_ChipID_Doc2k 0x20 +#define DOC_ChipID_Doc2kTSOP 0x21 /* internal number for MTD */ #define DOC_ChipID_DocMil 0x30 +#define DOC_ChipID_DocMilPlus32 0x40 +#define DOC_ChipID_DocMilPlus16 0x41 #define CDSN_CTRL_FR_B 0x80 +#define CDSN_CTRL_FR_B0 0x40 +#define CDSN_CTRL_FR_B1 0x80 + #define CDSN_CTRL_ECC_IO 0x20 #define CDSN_CTRL_FLASH_IO 0x10 #define CDSN_CTRL_WP 0x08 @@ -77,41 +140,47 @@ struct DiskOnChip; #define DOC_ECC_RESV 0x02 #define DOC_ECC_IGNORE 0x01 +#define DOC_FLASH_CE 0x80 +#define DOC_FLASH_WP 0x40 +#define DOC_FLASH_BANK 0x02 + /* We have to also set the reserved bit 1 for enable */ #define DOC_ECC_EN (DOC_ECC__EN | DOC_ECC_RESV) #define DOC_ECC_DIS (DOC_ECC_RESV) +struct Nand { + char floor, chip; + unsigned long curadr; + unsigned char curmode; + /* Also some erase/write/pipeline info when we get that far */ +}; + #define MAX_FLOORS 4 #define MAX_CHIPS 4 -#define MAX_FLOORS_MIL 4 +#define MAX_FLOORS_MIL 1 #define MAX_CHIPS_MIL 1 +#define MAX_FLOORS_MPLUS 2 +#define MAX_CHIPS_MPLUS 1 + #define ADDR_COLUMN 1 #define ADDR_PAGE 2 #define ADDR_COLUMN_PAGE 3 -struct Nand { - char floor, chip; - unsigned long curadr; - unsigned char curmode; - /* Also some erase/write/pipeline info when we get that far */ -}; - struct DiskOnChip { unsigned long physadr; - unsigned long virtadr; + void __iomem *virtadr; unsigned long totlen; - char* name; - char ChipID; /* Type of DiskOnChip */ + unsigned char ChipID; /* Type of DiskOnChip */ int ioreg; - char* chips_name; unsigned long mfr; /* Flash IDs - only one type of flash per device */ unsigned long id; int chipshift; char page256; char pageadrlen; + char interleave; /* Internal interleaving - Millennium Plus style */ unsigned long erasesize; int curfloor; @@ -119,98 +188,22 @@ struct DiskOnChip { int numchips; struct Nand *chips; - - int nftl_found; - struct NFTLrecord nftl; + struct mtd_info *nextdoc; +/* XXX U-BOOT XXX */ +#if 0 + struct mutex lock; +#endif }; -#define SECTORSIZE 512 - -/* Return codes from doc_write(), doc_read(), and doc_erase(). - */ -#define DOC_OK 0 -#define DOC_EIO 1 -#define DOC_EINVAL 2 -#define DOC_EECC 3 -#define DOC_ETIMEOUT 4 - -/* - * Function Prototypes - */ int doc_decode_ecc(unsigned char sector[512], unsigned char ecc1[6]); -int doc_rw(struct DiskOnChip* this, int cmd, loff_t from, size_t len, - size_t *retlen, u_char *buf); -int doc_read_ecc(struct DiskOnChip* this, loff_t from, size_t len, - size_t *retlen, u_char *buf, u_char *eccbuf); -int doc_write_ecc(struct DiskOnChip* this, loff_t to, size_t len, - size_t *retlen, const u_char *buf, u_char *eccbuf); -int doc_read_oob(struct DiskOnChip* this, loff_t ofs, size_t len, - size_t *retlen, u_char *buf); -int doc_write_oob(struct DiskOnChip* this, loff_t ofs, size_t len, - size_t *retlen, const u_char *buf); -int doc_erase (struct DiskOnChip* this, loff_t ofs, size_t len); - -void doc_probe(unsigned long physadr); - -void doc_print(struct DiskOnChip*); - -/* - * Standard NAND flash commands - */ -#define NAND_CMD_READ0 0 -#define NAND_CMD_READ1 1 -#define NAND_CMD_PAGEPROG 0x10 -#define NAND_CMD_READOOB 0x50 -#define NAND_CMD_ERASE1 0x60 -#define NAND_CMD_STATUS 0x70 -#define NAND_CMD_SEQIN 0x80 -#define NAND_CMD_READID 0x90 -#define NAND_CMD_ERASE2 0xd0 -#define NAND_CMD_RESET 0xff - +/* XXX U-BOOT XXX */ +#if 1 /* * NAND Flash Manufacturer ID Codes */ -#define NAND_MFR_TOSHIBA 0x98 -#define NAND_MFR_SAMSUNG 0xec - -/* - * NAND Flash Device ID Structure - * - * Structure overview: - * - * name - Complete name of device - * - * manufacture_id - manufacturer ID code of device. - * - * model_id - model ID code of device. - * - * chipshift - total number of address bits for the device which - * is used to calculate address offsets and the total - * number of bytes the device is capable of. - * - * page256 - denotes if flash device has 256 byte pages or not. - * - * pageadrlen - number of bytes minus one needed to hold the - * complete address into the flash array. Keep in - * mind that when a read or write is done to a - * specific address, the address is input serially - * 8 bits at a time. This structure member is used - * by the read/write routines as a loop index for - * shifting the address out 8 bits at a time. - * - * erasesize - size of an erase block in the flash device. - */ -struct nand_flash_dev { - char * name; - int manufacture_id; - int model_id; - int chipshift; - char page256; - char pageadrlen; - unsigned long erasesize; - int bus16; -}; +#define NAND_MFR_TOSHIBA 0x98 +#define NAND_MFR_SAMSUNG 0xec +#endif #endif /* __MTD_DOC2000_H__ */ diff --git a/include/linux/mtd/fsl_upm.h b/include/linux/mtd/fsl_upm.h index 49fd8a6..638a4e4 100644 --- a/include/linux/mtd/fsl_upm.h +++ b/include/linux/mtd/fsl_upm.h @@ -31,6 +31,9 @@ struct fsl_upm_nand { int wait_pattern; int (*dev_ready)(void); int chip_delay; + + /* no need to fill */ + int last_ctrl; }; extern int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun); diff --git a/include/linux/mtd/inftl-user.h b/include/linux/mtd/inftl-user.h new file mode 100644 index 0000000..9b1e252 --- /dev/null +++ b/include/linux/mtd/inftl-user.h @@ -0,0 +1,91 @@ +/* + * $Id: inftl-user.h,v 1.2 2005/11/07 11:14:56 gleixner Exp $ + * + * Parts of INFTL headers shared with userspace + * + */ + +#ifndef __MTD_INFTL_USER_H__ +#define __MTD_INFTL_USER_H__ + +#define OSAK_VERSION 0x5120 +#define PERCENTUSED 98 + +#define SECTORSIZE 512 + +/* Block Control Information */ + +struct inftl_bci { + uint8_t ECCsig[6]; + uint8_t Status; + uint8_t Status1; +} __attribute__((packed)); + +struct inftl_unithead1 { + uint16_t virtualUnitNo; + uint16_t prevUnitNo; + uint8_t ANAC; + uint8_t NACs; + uint8_t parityPerField; + uint8_t discarded; +} __attribute__((packed)); + +struct inftl_unithead2 { + uint8_t parityPerField; + uint8_t ANAC; + uint16_t prevUnitNo; + uint16_t virtualUnitNo; + uint8_t NACs; + uint8_t discarded; +} __attribute__((packed)); + +struct inftl_unittail { + uint8_t Reserved[4]; + uint16_t EraseMark; + uint16_t EraseMark1; +} __attribute__((packed)); + +union inftl_uci { + struct inftl_unithead1 a; + struct inftl_unithead2 b; + struct inftl_unittail c; +}; + +struct inftl_oob { + struct inftl_bci b; + union inftl_uci u; +}; + + +/* INFTL Media Header */ + +struct INFTLPartition { + __u32 virtualUnits; + __u32 firstUnit; + __u32 lastUnit; + __u32 flags; + __u32 spareUnits; + __u32 Reserved0; + __u32 Reserved1; +} __attribute__((packed)); + +struct INFTLMediaHeader { + char bootRecordID[8]; + __u32 NoOfBootImageBlocks; + __u32 NoOfBinaryPartitions; + __u32 NoOfBDTLPartitions; + __u32 BlockMultiplierBits; + __u32 FormatFlags; + __u32 OsakVersion; + __u32 PercentUsed; + struct INFTLPartition Partitions[4]; +} __attribute__((packed)); + +/* Partition flag types */ +#define INFTL_BINARY 0x20000000 +#define INFTL_BDTL 0x40000000 +#define INFTL_LAST 0x80000000 + +#endif /* __MTD_INFTL_USER_H__ */ + + diff --git a/include/linux/mtd/jffs2-user.h b/include/linux/mtd/jffs2-user.h new file mode 100644 index 0000000..d508ef0 --- /dev/null +++ b/include/linux/mtd/jffs2-user.h @@ -0,0 +1,35 @@ +/* + * $Id: jffs2-user.h,v 1.1 2004/05/05 11:57:54 dwmw2 Exp $ + * + * JFFS2 definitions for use in user space only + */ + +#ifndef __JFFS2_USER_H__ +#define __JFFS2_USER_H__ + +/* This file is blessed for inclusion by userspace */ +#include <linux/jffs2.h> +#include <endian.h> +#include <byteswap.h> + +#undef cpu_to_je16 +#undef cpu_to_je32 +#undef cpu_to_jemode +#undef je16_to_cpu +#undef je32_to_cpu +#undef jemode_to_cpu + +extern int target_endian; + +#define t16(x) ({ uint16_t __b = (x); (target_endian==__BYTE_ORDER)?__b:bswap_16(__b); }) +#define t32(x) ({ uint32_t __b = (x); (target_endian==__BYTE_ORDER)?__b:bswap_32(__b); }) + +#define cpu_to_je16(x) ((jint16_t){t16(x)}) +#define cpu_to_je32(x) ((jint32_t){t32(x)}) +#define cpu_to_jemode(x) ((jmode_t){t32(x)}) + +#define je16_to_cpu(x) (t16((x).v16)) +#define je32_to_cpu(x) (t32((x).v32)) +#define jemode_to_cpu(x) (t32((x).m)) + +#endif /* __JFFS2_USER_H__ */ diff --git a/include/linux/mtd/mtd-abi.h b/include/linux/mtd/mtd-abi.h index 4cebea9..0ce2099 100644 --- a/include/linux/mtd/mtd-abi.h +++ b/include/linux/mtd/mtd-abi.h @@ -1,5 +1,5 @@ /* - * $Id: mtd-abi.h,v 1.7 2004/11/23 15:37:32 gleixner Exp $ + * $Id: mtd-abi.h,v 1.13 2005/11/07 11:14:56 gleixner Exp $ * * Portions of MTD ABI definition which are shared by kernel and user space */ @@ -7,6 +7,10 @@ #ifndef __MTD_ABI_H__ #define __MTD_ABI_H__ +#if 1 +#include <linux/mtd/compat.h> +#endif + struct erase_info_user { uint32_t start; uint32_t length; @@ -15,7 +19,7 @@ struct erase_info_user { struct mtd_oob_buf { uint32_t start; uint32_t length; - unsigned char *ptr; + unsigned char __user *ptr; }; #define MTD_ABSENT 0 @@ -23,47 +27,41 @@ struct mtd_oob_buf { #define MTD_ROM 2 #define MTD_NORFLASH 3 #define MTD_NANDFLASH 4 -#define MTD_PEROM 5 -#define MTD_OTHER 14 -#define MTD_UNKNOWN 15 - -#define MTD_CLEAR_BITS 1 /* Bits can be cleared (flash) */ -#define MTD_SET_BITS 2 /* Bits can be set */ -#define MTD_ERASEABLE 4 /* Has an erase function */ -#define MTD_WRITEB_WRITEABLE 8 /* Direct IO is possible */ -#define MTD_VOLATILE 16 /* Set for RAMs */ -#define MTD_XIP 32 /* eXecute-In-Place possible */ -#define MTD_OOB 64 /* Out-of-band data (NAND flash) */ -#define MTD_ECC 128 /* Device capable of automatic ECC */ -#define MTD_NO_VIRTBLOCKS 256 /* Virtual blocks not allowed */ - -/* Some common devices / combinations of capabilities */ -#define MTD_CAP_ROM 0 -#define MTD_CAP_RAM (MTD_CLEAR_BITS|MTD_SET_BITS|MTD_WRITEB_WRITEABLE) -#define MTD_CAP_NORFLASH (MTD_CLEAR_BITS|MTD_ERASEABLE) -#define MTD_CAP_NANDFLASH (MTD_CLEAR_BITS|MTD_ERASEABLE|MTD_OOB) -#define MTD_WRITEABLE (MTD_CLEAR_BITS|MTD_SET_BITS) +#define MTD_DATAFLASH 6 +#define MTD_UBIVOLUME 7 +#define MTD_WRITEABLE 0x400 /* Device is writeable */ +#define MTD_BIT_WRITEABLE 0x800 /* Single bits can be flipped */ +#define MTD_NO_ERASE 0x1000 /* No erase necessary */ +#define MTD_STUPID_LOCK 0x2000 /* Always locked after reset */ -/* Types of automatic ECC/Checksum available */ -#define MTD_ECC_NONE 0 /* No automatic ECC available */ -#define MTD_ECC_RS_DiskOnChip 1 /* Automatic ECC on DiskOnChip */ -#define MTD_ECC_SW 2 /* SW ECC for Toshiba & Samsung devices */ +// Some common devices / combinations of capabilities +#define MTD_CAP_ROM 0 +#define MTD_CAP_RAM (MTD_WRITEABLE | MTD_BIT_WRITEABLE | MTD_NO_ERASE) +#define MTD_CAP_NORFLASH (MTD_WRITEABLE | MTD_BIT_WRITEABLE) +#define MTD_CAP_NANDFLASH (MTD_WRITEABLE) /* ECC byte placement */ -#define MTD_NANDECC_OFF 0 /* Switch off ECC (Not recommended) */ -#define MTD_NANDECC_PLACE 1 /* Use the given placement in the structure (YAFFS1 legacy mode) */ -#define MTD_NANDECC_AUTOPLACE 2 /* Use the default placement scheme */ -#define MTD_NANDECC_PLACEONLY 3 /* Use the given placement in the structure (Do not store ecc result on read) */ -#define MTD_NANDECC_AUTOPL_USR 4 /* Use the given autoplacement scheme rather than using the default */ +#define MTD_NANDECC_OFF 0 // Switch off ECC (Not recommended) +#define MTD_NANDECC_PLACE 1 // Use the given placement in the structure (YAFFS1 legacy mode) +#define MTD_NANDECC_AUTOPLACE 2 // Use the default placement scheme +#define MTD_NANDECC_PLACEONLY 3 // Use the given placement in the structure (Do not store ecc result on read) +#define MTD_NANDECC_AUTOPL_USR 4 // Use the given autoplacement scheme rather than using the default + +/* OTP mode selection */ +#define MTD_OTP_OFF 0 +#define MTD_OTP_FACTORY 1 +#define MTD_OTP_USER 2 struct mtd_info_user { uint8_t type; uint32_t flags; - uint32_t size; /* Total size of the MTD */ + uint32_t size; // Total size of the MTD uint32_t erasesize; - uint32_t oobblock; /* Size of OOB blocks (e.g. 512) */ - uint32_t oobsize; /* Amount of OOB data per block (e.g. 16) */ + uint32_t writesize; + uint32_t oobsize; // Amount of OOB data per block (e.g. 16) + /* The below two fields are obsolete and broken, do not use them + * (TODO: remove at some point) */ uint32_t ecctype; uint32_t eccsize; }; @@ -76,19 +74,36 @@ struct region_info_user { uint32_t regionindex; }; -#define MEMGETINFO _IOR('M', 1, struct mtd_info_user) -#define MEMERASE _IOW('M', 2, struct erase_info_user) -#define MEMWRITEOOB _IOWR('M', 3, struct mtd_oob_buf) -#define MEMREADOOB _IOWR('M', 4, struct mtd_oob_buf) -#define MEMLOCK _IOW('M', 5, struct erase_info_user) -#define MEMUNLOCK _IOW('M', 6, struct erase_info_user) +struct otp_info { + uint32_t start; + uint32_t length; + uint32_t locked; +}; + +#define MEMGETINFO _IOR('M', 1, struct mtd_info_user) +#define MEMERASE _IOW('M', 2, struct erase_info_user) +#define MEMWRITEOOB _IOWR('M', 3, struct mtd_oob_buf) +#define MEMREADOOB _IOWR('M', 4, struct mtd_oob_buf) +#define MEMLOCK _IOW('M', 5, struct erase_info_user) +#define MEMUNLOCK _IOW('M', 6, struct erase_info_user) #define MEMGETREGIONCOUNT _IOR('M', 7, int) #define MEMGETREGIONINFO _IOWR('M', 8, struct region_info_user) #define MEMSETOOBSEL _IOW('M', 9, struct nand_oobinfo) #define MEMGETOOBSEL _IOR('M', 10, struct nand_oobinfo) #define MEMGETBADBLOCK _IOW('M', 11, loff_t) #define MEMSETBADBLOCK _IOW('M', 12, loff_t) +#define OTPSELECT _IOR('M', 13, int) +#define OTPGETREGIONCOUNT _IOW('M', 14, int) +#define OTPGETREGIONINFO _IOW('M', 15, struct otp_info) +#define OTPLOCK _IOR('M', 16, struct otp_info) +#define ECCGETLAYOUT _IOR('M', 17, struct nand_ecclayout) +#define ECCGETSTATS _IOR('M', 18, struct mtd_ecc_stats) +#define MTDFILEMODE _IO('M', 19) +/* + * Obsolete legacy interface. Keep it in order not to break userspace + * interfaces + */ struct nand_oobinfo { uint32_t useecc; uint32_t eccbytes; @@ -96,4 +111,46 @@ struct nand_oobinfo { uint32_t eccpos[48]; }; +struct nand_oobfree { + uint32_t offset; + uint32_t length; +}; + +#define MTD_MAX_OOBFREE_ENTRIES 8 +/* + * ECC layout control structure. Exported to userspace for + * diagnosis and to allow creation of raw images + */ +struct nand_ecclayout { + uint32_t eccbytes; + uint32_t eccpos[64]; + uint32_t oobavail; + struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES]; +}; + +/** + * struct mtd_ecc_stats - error correction stats + * + * @corrected: number of corrected bits + * @failed: number of uncorrectable errors + * @badblocks: number of bad blocks in this partition + * @bbtblocks: number of blocks reserved for bad block tables + */ +struct mtd_ecc_stats { + uint32_t corrected; + uint32_t failed; + uint32_t badblocks; + uint32_t bbtblocks; +}; + +/* + * Read/write file modes for access to MTD + */ +enum mtd_file_modes { + MTD_MODE_NORMAL = MTD_OTP_OFF, + MTD_MODE_OTP_FACTORY = MTD_OTP_FACTORY, + MTD_MODE_OTP_USER = MTD_OTP_USER, + MTD_MODE_RAW, +}; + #endif /* __MTD_ABI_H__ */ diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 05ba375..8e0dc00 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -1,5 +1,5 @@ /* - * $Id: mtd.h,v 1.56 2004/08/09 18:46:04 dmarlin Exp $ + * $Id: mtd.h,v 1.61 2005/11/07 11:14:54 gleixner Exp $ * * Copyright (C) 1999-2003 David Woodhouse <dwmw2@infradead.org> et al. * @@ -8,10 +8,13 @@ #ifndef __MTD_MTD_H__ #define __MTD_MTD_H__ + #include <linux/types.h> #include <linux/mtd/mtd-abi.h> -#define MAX_MTD_DEVICES 16 +#define MTD_CHAR_MAJOR 90 +#define MTD_BLOCK_MAJOR 31 +#define MAX_MTD_DEVICES 32 #define MTD_ERASE_PENDING 0x01 #define MTD_ERASING 0x02 @@ -41,32 +44,83 @@ struct mtd_erase_region_info { u_int32_t offset; /* At which this region starts, from the beginning of the MTD */ u_int32_t erasesize; /* For this region */ u_int32_t numblocks; /* Number of blocks of erasesize in this region */ + unsigned long *lockmap; /* If keeping bitmap of locks */ +}; + +/* + * oob operation modes + * + * MTD_OOB_PLACE: oob data are placed at the given offset + * MTD_OOB_AUTO: oob data are automatically placed at the free areas + * which are defined by the ecclayout + * MTD_OOB_RAW: mode to read raw data+oob in one chunk. The oob data + * is inserted into the data. Thats a raw image of the + * flash contents. + */ +typedef enum { + MTD_OOB_PLACE, + MTD_OOB_AUTO, + MTD_OOB_RAW, +} mtd_oob_mode_t; + +/** + * struct mtd_oob_ops - oob operation operands + * @mode: operation mode + * + * @len: number of data bytes to write/read + * + * @retlen: number of data bytes written/read + * + * @ooblen: number of oob bytes to write/read + * @oobretlen: number of oob bytes written/read + * @ooboffs: offset of oob data in the oob area (only relevant when + * mode = MTD_OOB_PLACE) + * @datbuf: data buffer - if NULL only oob data are read/written + * @oobbuf: oob data buffer + * + * Note, it is allowed to read more then one OOB area at one go, but not write. + * The interface assumes that the OOB write requests program only one page's + * OOB area. + */ +struct mtd_oob_ops { + mtd_oob_mode_t mode; + size_t len; + size_t retlen; + size_t ooblen; + size_t oobretlen; + uint32_t ooboffs; + uint8_t *datbuf; + uint8_t *oobbuf; }; struct mtd_info { u_char type; u_int32_t flags; - u_int32_t size; /* Total size of the MTD */ + u_int32_t size; // Total size of the MTD - /* "Major" erase size for the device. Naïve users may take this + /* "Major" erase size for the device. Naïve users may take this * to be the only erase size available, or may use the more detailed * information below if they desire */ u_int32_t erasesize; + /* Minimal writable flash unit size. In case of NOR flash it is 1 (even + * though individual bits can be cleared), in case of NAND flash it is + * one NAND page (or half, or one-fourths of it), in case of ECC-ed NOR + * it is of ECC block size, etc. It is illegal to have writesize = 0. + * Any driver registering a struct mtd_info must ensure a writesize of + * 1 or larger. + */ + u_int32_t writesize; - u_int32_t oobblock; /* Size of OOB blocks (e.g. 512) */ - u_int32_t oobsize; /* Amount of OOB data per block (e.g. 16) */ - u_int32_t oobavail; /* Number of bytes in OOB area available for fs */ - u_int32_t ecctype; - u_int32_t eccsize; - + u_int32_t oobsize; // Amount of OOB data per block (e.g. 16) + u_int32_t oobavail; // Available OOB bytes per block - /* Kernel-only stuff starts here. */ + // Kernel-only stuff starts here. char *name; int index; - /* oobinfo is a nand_oobinfo structure, which can be set by iotcl (MEMSETOOBINFO) */ - struct nand_oobinfo oobinfo; + /* ecc layout structure pointer - read only ! */ + struct nand_ecclayout *ecclayout; /* Data for variable erase regions. If numeraseregions is zero, * it means that the whole device has erasesize as given above. @@ -74,9 +128,6 @@ struct mtd_info { int numeraseregions; struct mtd_erase_region_info *eraseregions; - /* This really shouldn't be here. It can go away in 2.5 */ - u_int32_t bank_size; - int (*erase) (struct mtd_info *mtd, struct erase_info *instr); /* This stuff for eXecute-In-Place */ @@ -89,39 +140,35 @@ struct mtd_info { int (*read) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); int (*write) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf); - int (*read_ecc) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf, u_char *eccbuf, struct nand_oobinfo *oobsel); - int (*write_ecc) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf, u_char *eccbuf, struct nand_oobinfo *oobsel); - - int (*read_oob) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); - int (*write_oob) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf); + int (*read_oob) (struct mtd_info *mtd, loff_t from, + struct mtd_oob_ops *ops); + int (*write_oob) (struct mtd_info *mtd, loff_t to, + struct mtd_oob_ops *ops); /* * Methods to access the protection register area, present in some * flash devices. The user data is one time programmable but the * factory data is read only. */ - int (*read_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); - + int (*get_fact_prot_info) (struct mtd_info *mtd, struct otp_info *buf, size_t len); int (*read_fact_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); - - /* This function is not yet implemented */ + int (*get_user_prot_info) (struct mtd_info *mtd, struct otp_info *buf, size_t len); + int (*read_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); int (*write_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); + int (*lock_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len); + +/* XXX U-BOOT XXX */ #if 0 - /* kvec-based read/write methods. We need these especially for NAND flash, - with its limited number of write cycles per erase. + /* kvec-based read/write methods. NB: The 'count' parameter is the number of _vectors_, each of which contains an (ofs, len) tuple. */ - int (*readv) (struct mtd_info *mtd, struct kvec *vecs, unsigned long count, loff_t from, size_t *retlen); - int (*readv_ecc) (struct mtd_info *mtd, struct kvec *vecs, unsigned long count, loff_t from, - size_t *retlen, u_char *eccbuf, struct nand_oobinfo *oobsel); int (*writev) (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count, loff_t to, size_t *retlen); - int (*writev_ecc) (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count, loff_t to, - size_t *retlen, u_char *eccbuf, struct nand_oobinfo *oobsel); #endif + /* Sync */ void (*sync) (struct mtd_info *mtd); -#if 0 + /* Chip-supported device locking */ int (*lock) (struct mtd_info *mtd, loff_t ofs, size_t len); int (*unlock) (struct mtd_info *mtd, loff_t ofs, size_t len); @@ -129,15 +176,32 @@ struct mtd_info { /* Power Management functions */ int (*suspend) (struct mtd_info *mtd); void (*resume) (struct mtd_info *mtd); -#endif + /* Bad block management functions */ int (*block_isbad) (struct mtd_info *mtd, loff_t ofs); int (*block_markbad) (struct mtd_info *mtd, loff_t ofs); +/* XXX U-BOOT XXX */ +#if 0 + struct notifier_block reboot_notifier; /* default mode before reboot */ +#endif + + /* ECC status information */ + struct mtd_ecc_stats ecc_stats; + /* Subpage shift (NAND) */ + int subpage_sft; + void *priv; struct module *owner; int usecount; + + /* If the driver is something smart, like UBI, it may need to maintain + * its own reference counting. The below functions are only for driver. + * The driver may register its callbacks. These callbacks are not + * supposed to be called by MTD users */ + int (*get_device) (struct mtd_info *mtd); + void (*put_device) (struct mtd_info *mtd); }; @@ -147,9 +211,11 @@ extern int add_mtd_device(struct mtd_info *mtd); extern int del_mtd_device (struct mtd_info *mtd); extern struct mtd_info *get_mtd_device(struct mtd_info *mtd, int num); +extern struct mtd_info *get_mtd_device_nm(const char *name); extern void put_mtd_device(struct mtd_info *mtd); +/* XXX U-BOOT XXX */ #if 0 struct mtd_notifier { void (*add)(struct mtd_info *mtd); @@ -157,7 +223,6 @@ struct mtd_notifier { struct list_head list; }; - extern void register_mtd_user (struct mtd_notifier *new); extern int unregister_mtd_user (struct mtd_notifier *old); @@ -168,20 +233,6 @@ int default_mtd_readv(struct mtd_info *mtd, struct kvec *vecs, unsigned long count, loff_t from, size_t *retlen); #endif -#define MTD_ERASE(mtd, args...) (*(mtd->erase))(mtd, args) -#define MTD_POINT(mtd, a,b,c,d) (*(mtd->point))(mtd, a,b,c, (u_char **)(d)) -#define MTD_UNPOINT(mtd, arg) (*(mtd->unpoint))(mtd, (u_char *)arg) -#define MTD_READ(mtd, args...) (*(mtd->read))(mtd, args) -#define MTD_WRITE(mtd, args...) (*(mtd->write))(mtd, args) -#define MTD_READV(mtd, args...) (*(mtd->readv))(mtd, args) -#define MTD_WRITEV(mtd, args...) (*(mtd->writev))(mtd, args) -#define MTD_READECC(mtd, args...) (*(mtd->read_ecc))(mtd, args) -#define MTD_WRITEECC(mtd, args...) (*(mtd->write_ecc))(mtd, args) -#define MTD_READOOB(mtd, args...) (*(mtd->read_oob))(mtd, args) -#define MTD_WRITEOOB(mtd, args...) (*(mtd->write_oob))(mtd, args) -#define MTD_SYNC(mtd) do { if (mtd->sync) (*(mtd->sync))(mtd); } while (0) - - #ifdef CONFIG_MTD_PARTITIONS void mtd_erase_callback(struct erase_info *instr); #else @@ -208,7 +259,6 @@ static inline void mtd_erase_callback(struct erase_info *instr) } while(0) #else /* CONFIG_MTD_DEBUG */ #define MTDDEBUG(n, args...) do { } while(0) - #endif /* CONFIG_MTD_DEBUG */ #endif /* __MTD_MTD_H__ */ diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index e2a25a6..2993a89 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -2,114 +2,123 @@ * linux/include/linux/mtd/nand.h * * Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com> - * Steven J. Hill <sjhill@realitydiluted.com> + * Steven J. Hill <sjhill@realitydiluted.com> * Thomas Gleixner <tglx@linutronix.de> * - * $Id: nand.h,v 1.68 2004/11/12 10:40:37 gleixner Exp $ + * $Id: nand.h,v 1.74 2005/09/15 13:58:50 vwool Exp $ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * - * Info: - * Contains standard defines and IDs for NAND flash devices + * Info: + * Contains standard defines and IDs for NAND flash devices * - * Changelog: - * 01-31-2000 DMW Created - * 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers - * so it can be used by other NAND flash device - * drivers. I also changed the copyright since none - * of the original contents of this file are specific - * to DoC devices. David can whack me with a baseball - * bat later if I did something naughty. - * 10-11-2000 SJH Added private NAND flash structure for driver - * 10-24-2000 SJH Added prototype for 'nand_scan' function - * 10-29-2001 TG changed nand_chip structure to support - * hardwarespecific function for accessing control lines - * 02-21-2002 TG added support for different read/write adress and - * ready/busy line access function - * 02-26-2002 TG added chip_delay to nand_chip structure to optimize - * command delay times for different chips - * 04-28-2002 TG OOB config defines moved from nand.c to avoid duplicate - * defines in jffs2/wbuf.c - * 08-07-2002 TG forced bad block location to byte 5 of OOB, even if - * CONFIG_MTD_NAND_ECC_JFFS2 is not set - * 08-10-2002 TG extensions to nand_chip structure to support HW-ECC - * - * 08-29-2002 tglx nand_chip structure: data_poi for selecting - * internal / fs-driver buffer - * support for 6byte/512byte hardware ECC - * read_ecc, write_ecc extended for different oob-layout - * oob layout selections: NAND_NONE_OOB, NAND_JFFS2_OOB, - * NAND_YAFFS_OOB - * 11-25-2002 tglx Added Manufacturer code FUJITSU, NATIONAL - * Split manufacturer and device ID structures - * - * 02-08-2004 tglx added option field to nand structure for chip anomalities - * 05-25-2004 tglx added bad block table support, ST-MICRO manufacturer id - * update of nand_chip structure description + * Changelog: + * See git changelog. */ #ifndef __LINUX_MTD_NAND_H #define __LINUX_MTD_NAND_H -#include <linux/mtd/compat.h> +/* XXX U-BOOT XXX */ +#if 0 +#include <linux/wait.h> +#include <linux/spinlock.h> #include <linux/mtd/mtd.h> +#endif + +#include "config.h" + +#include "linux/mtd/compat.h" +#include "linux/mtd/mtd.h" + struct mtd_info; /* Scan and identify a NAND device */ extern int nand_scan (struct mtd_info *mtd, int max_chips); +/* Separate phases of nand_scan(), allowing board driver to intervene + * and override command or ECC setup according to flash type */ +extern int nand_scan_ident(struct mtd_info *mtd, int max_chips); +extern int nand_scan_tail(struct mtd_info *mtd); + /* Free resources held by the NAND device */ extern void nand_release (struct mtd_info *mtd); -/* Read raw data from the device without ECC */ -extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, size_t ooblen); +/* Internal helper for board drivers which need to override command function */ +extern void nand_wait_ready(struct mtd_info *mtd); +/* The maximum number of NAND chips in an array */ +#ifndef NAND_MAX_CHIPS +#define NAND_MAX_CHIPS 8 +#endif /* This constant declares the max. oobsize / page, which * is supported now. If you add a chip with bigger oobsize/page * adjust this accordingly. */ -#define NAND_MAX_OOBSIZE 64 +#define NAND_MAX_OOBSIZE 128 +#define NAND_MAX_PAGESIZE 4096 /* * Constants for hardware specific CLE/ALE/NCE function -*/ + * + * These are bits which can be or'ed to set/clear multiple + * bits in one go. + */ /* Select the chip by setting nCE to low */ -#define NAND_CTL_SETNCE 1 -/* Deselect the chip by setting nCE to high */ -#define NAND_CTL_CLRNCE 2 +#define NAND_NCE 0x01 /* Select the command latch by setting CLE to high */ -#define NAND_CTL_SETCLE 3 -/* Deselect the command latch by setting CLE to low */ -#define NAND_CTL_CLRCLE 4 +#define NAND_CLE 0x02 /* Select the address latch by setting ALE to high */ -#define NAND_CTL_SETALE 5 -/* Deselect the address latch by setting ALE to low */ -#define NAND_CTL_CLRALE 6 -/* Set write protection by setting WP to high. Not used! */ -#define NAND_CTL_SETWP 7 -/* Clear write protection by setting WP to low. Not used! */ -#define NAND_CTL_CLRWP 8 +#define NAND_ALE 0x04 + +#define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) +#define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) +#define NAND_CTRL_CHANGE 0x80 /* * Standard NAND flash commands */ #define NAND_CMD_READ0 0 #define NAND_CMD_READ1 1 +#define NAND_CMD_RNDOUT 5 #define NAND_CMD_PAGEPROG 0x10 #define NAND_CMD_READOOB 0x50 #define NAND_CMD_ERASE1 0x60 #define NAND_CMD_STATUS 0x70 #define NAND_CMD_STATUS_MULTI 0x71 #define NAND_CMD_SEQIN 0x80 +#define NAND_CMD_RNDIN 0x85 #define NAND_CMD_READID 0x90 #define NAND_CMD_ERASE2 0xd0 #define NAND_CMD_RESET 0xff /* Extended commands for large page devices */ #define NAND_CMD_READSTART 0x30 +#define NAND_CMD_RNDOUTSTART 0xE0 #define NAND_CMD_CACHEDPROG 0x15 +/* Extended commands for AG-AND device */ +/* + * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but + * there is no way to distinguish that from NAND_CMD_READ0 + * until the remaining sequence of commands has been completed + * so add a high order bit and mask it off in the command. + */ +#define NAND_CMD_DEPLETE1 0x100 +#define NAND_CMD_DEPLETE2 0x38 +#define NAND_CMD_STATUS_MULTI 0x71 +#define NAND_CMD_STATUS_ERROR 0x72 +/* multi-bank error status (banks 0-3) */ +#define NAND_CMD_STATUS_ERROR0 0x73 +#define NAND_CMD_STATUS_ERROR1 0x74 +#define NAND_CMD_STATUS_ERROR2 0x75 +#define NAND_CMD_STATUS_ERROR3 0x76 +#define NAND_CMD_STATUS_RESET 0x7f +#define NAND_CMD_STATUS_CLEAR 0xff + +#define NAND_CMD_NONE -1 + /* Status bits */ #define NAND_STATUS_FAIL 0x01 #define NAND_STATUS_FAIL_N1 0x02 @@ -120,25 +129,16 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_ /* * Constants for ECC_MODES */ - -/* No ECC. Usage is not recommended ! */ -#define NAND_ECC_NONE 0 -/* Software ECC 3 byte ECC per 256 Byte data */ -#define NAND_ECC_SOFT 1 -/* Hardware ECC 3 byte ECC per 256 Byte data */ -#define NAND_ECC_HW3_256 2 -/* Hardware ECC 3 byte ECC per 512 Byte data */ -#define NAND_ECC_HW3_512 3 -/* Hardware ECC 6 byte ECC per 512 Byte data */ -#define NAND_ECC_HW6_512 4 -/* Hardware ECC 8 byte ECC per 512 Byte data */ -#define NAND_ECC_HW8_512 6 -/* Hardware ECC 12 byte ECC per 2048 Byte data */ -#define NAND_ECC_HW12_2048 7 +typedef enum { + NAND_ECC_NONE, + NAND_ECC_SOFT, + NAND_ECC_HW, + NAND_ECC_HW_SYNDROME, +} nand_ecc_modes_t; /* * Constants for Hardware ECC -*/ + */ /* Reset Hardware ECC for read */ #define NAND_ECC_READ 0 /* Reset Hardware ECC for write */ @@ -146,6 +146,10 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_ /* Enable Hardware ECC before syndrom is read back from flash */ #define NAND_ECC_READSYN 2 +/* Bit mask for flags passed to do_nand_read_ecc */ +#define NAND_GET_DEVICE 0x80 + + /* Option constants for bizarre disfunctionality and real * features */ @@ -165,6 +169,17 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_ /* Chip has a array of 4 pages which can be read without * additional ready /busy waits */ #define NAND_4PAGE_ARRAY 0x00000040 +/* Chip requires that BBT is periodically rewritten to prevent + * bits from adjacent blocks from 'leaking' in altering data. + * This happens with the Renesas AG-AND chips, possibly others. */ +#define BBT_AUTO_REFRESH 0x00000080 +/* Chip does not require ready check on read. True + * for all large page devices, as they do not support + * autoincrement.*/ +#define NAND_NO_READRDY 0x00000100 +/* Chip does not allow subpage writes */ +#define NAND_NO_SUBPAGE_WRITE 0x00000200 + /* Options valid for Samsung large page devices */ #define NAND_SAMSUNG_LP_OPTIONS \ @@ -183,18 +198,20 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_ /* Use a flash based bad block table. This option is passed to the * default bad block table function. */ #define NAND_USE_FLASH_BBT 0x00010000 -/* The hw ecc generator provides a syndrome instead a ecc value on read - * This can only work if we have the ecc bytes directly behind the - * data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */ -#define NAND_HWECC_SYNDROME 0x00020000 - - +/* This option skips the bbt scan during initialization. */ +#define NAND_SKIP_BBTSCAN 0x00020000 +/* This option is defined if the board driver allocates its own buffers + (e.g. because it needs them DMA-coherent */ +#define NAND_OWN_BUFFERS 0x00040000 /* Options set by nand scan */ -/* Nand scan has allocated oob_buf */ -#define NAND_OOBBUF_ALLOC 0x40000000 -/* Nand scan has allocated data_buf */ -#define NAND_DATABUF_ALLOC 0x80000000 +/* bbt has already been read */ +#define NAND_BBT_SCANNED 0x40000000 +/* Nand scan has allocated controller struct */ +#define NAND_CONTROLLER_ALLOC 0x80000000 +/* Cell info constants */ +#define NAND_CI_CHIPNR_MSK 0x03 +#define NAND_CI_CELLTYPE_MSK 0x0C /* * nand_state_t - chip states @@ -207,135 +224,217 @@ typedef enum { FL_ERASING, FL_SYNCING, FL_CACHEDPRG, + FL_PM_SUSPENDED, } nand_state_t; /* Keep gcc happy */ struct nand_chip; -#if 0 /** - * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices - * @lock: protection lock + * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices + * @lock: protection lock * @active: the mtd device which holds the controller currently + * @wq: wait queue to sleep on if a NAND operation is in progress + * used instead of the per chip wait queue when a hw controller is available */ struct nand_hw_control { +/* XXX U-BOOT XXX */ +#if 0 spinlock_t lock; + wait_queue_head_t wq; +#endif struct nand_chip *active; }; -#endif + +/** + * struct nand_ecc_ctrl - Control structure for ecc + * @mode: ecc mode + * @steps: number of ecc steps per page + * @size: data bytes per ecc step + * @bytes: ecc bytes per step + * @total: total number of ecc bytes per page + * @prepad: padding information for syndrome based ecc generators + * @postpad: padding information for syndrome based ecc generators + * @layout: ECC layout control struct pointer + * @hwctl: function to control hardware ecc generator. Must only + * be provided if an hardware ECC is available + * @calculate: function for ecc calculation or readback from ecc hardware + * @correct: function for ecc correction, matching to ecc generator (sw/hw) + * @read_page_raw: function to read a raw page without ECC + * @write_page_raw: function to write a raw page without ECC + * @read_page: function to read a page according to the ecc generator requirements + * @write_page: function to write a page according to the ecc generator requirements + * @read_oob: function to read chip OOB data + * @write_oob: function to write chip OOB data + */ +struct nand_ecc_ctrl { + nand_ecc_modes_t mode; + int steps; + int size; + int bytes; + int total; + int prepad; + int postpad; + struct nand_ecclayout *layout; + void (*hwctl)(struct mtd_info *mtd, int mode); + int (*calculate)(struct mtd_info *mtd, + const uint8_t *dat, + uint8_t *ecc_code); + int (*correct)(struct mtd_info *mtd, uint8_t *dat, + uint8_t *read_ecc, + uint8_t *calc_ecc); + int (*read_page_raw)(struct mtd_info *mtd, + struct nand_chip *chip, + uint8_t *buf); + void (*write_page_raw)(struct mtd_info *mtd, + struct nand_chip *chip, + const uint8_t *buf); + int (*read_page)(struct mtd_info *mtd, + struct nand_chip *chip, + uint8_t *buf); + void (*write_page)(struct mtd_info *mtd, + struct nand_chip *chip, + const uint8_t *buf); + int (*read_oob)(struct mtd_info *mtd, + struct nand_chip *chip, + int page, + int sndcmd); + int (*write_oob)(struct mtd_info *mtd, + struct nand_chip *chip, + int page); +}; + +/** + * struct nand_buffers - buffer structure for read/write + * @ecccalc: buffer for calculated ecc + * @ecccode: buffer for ecc read from flash + * @databuf: buffer for data - dynamically sized + * + * Do not change the order of buffers. databuf and oobrbuf must be in + * consecutive order. + */ +struct nand_buffers { + uint8_t ecccalc[NAND_MAX_OOBSIZE]; + uint8_t ecccode[NAND_MAX_OOBSIZE]; + uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE]; +}; /** * struct nand_chip - NAND Private Flash Chip Data * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device * @read_byte: [REPLACEABLE] read one byte from the chip - * @write_byte: [REPLACEABLE] write one byte to the chip * @read_word: [REPLACEABLE] read one word from the chip - * @write_word: [REPLACEABLE] write one word to the chip * @write_buf: [REPLACEABLE] write data from the buffer to the chip * @read_buf: [REPLACEABLE] read data from the chip into the buffer * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data * @select_chip: [REPLACEABLE] select chip nr * @block_bad: [REPLACEABLE] check, if the block is bad * @block_markbad: [REPLACEABLE] mark the block bad - * @hwcontrol: [BOARDSPECIFIC] hardwarespecific function for accesing control-lines + * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling + * ALE/CLE/nCE. Also used to write command and address * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line * If set to NULL no access to ready/busy is available and the ready/busy information * is read from the chip status register * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready - * @calculate_ecc: [REPLACEABLE] function for ecc calculation or readback from ecc hardware - * @correct_data: [REPLACEABLE] function for ecc correction, matching to ecc generator (sw/hw) - * @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only - * be provided if a hardware ECC is available + * @ecc: [BOARDSPECIFIC] ecc control ctructure + * @buffers: buffer structure for read/write + * @hwcontrol: platform-specific hardware control structure + * @ops: oob operation operands * @erase_cmd: [INTERN] erase command write function, selectable due to AND support * @scan_bbt: [REPLACEABLE] function to scan bad block table - * @eccmode: [BOARDSPECIFIC] mode of ecc, see defines - * @eccsize: [INTERN] databytes used per ecc-calculation - * @eccbytes: [INTERN] number of ecc bytes per ecc-calculation step - * @eccsteps: [INTERN] number of ecc calculation steps per page * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR) - * @chip_lock: [INTERN] spinlock used to protect access to this structure and the chip * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress * @state: [INTERN] the current state of the NAND device + * @oob_poi: poison value buffer * @page_shift: [INTERN] number of address bits in a page (column address bits) * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry * @chip_shift: [INTERN] number of address bits in one chip - * @data_buf: [INTERN] internal buffer for one page + oob - * @oob_buf: [INTERN] oob buffer for one eraseblock + * @datbuf: [INTERN] internal buffer for one page + oob + * @oobbuf: [INTERN] oob buffer for one eraseblock * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized * @data_poi: [INTERN] pointer to a data buffer * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about * special functionality. See the defines for further explanation * @badblockpos: [INTERN] position of the bad block marker in the oob area + * @cellinfo: [INTERN] MLC/multichip data from chip ident * @numchips: [INTERN] number of physical chips * @chipsize: [INTERN] the size of one chip for multichip arrays * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf - * @autooob: [REPLACEABLE] the default (auto)placement scheme + * @subpagesize: [INTERN] holds the subpagesize + * @ecclayout: [REPLACEABLE] the default ecc placement scheme * @bbt: [INTERN] bad block table pointer * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup * @bbt_md: [REPLACEABLE] bad block table mirror descriptor * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan - * @controller: [OPTIONAL] a pointer to a hardware controller structure which is shared among multiple independend devices + * @controller: [REPLACEABLE] a pointer to a hardware controller structure + * which is shared among multiple independend devices * @priv: [OPTIONAL] pointer to private chip date + * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks + * (determine if errors are correctable) + * @write_page: [REPLACEABLE] High-level page write function */ struct nand_chip { void __iomem *IO_ADDR_R; void __iomem *IO_ADDR_W; - u_char (*read_byte)(struct mtd_info *mtd); - void (*write_byte)(struct mtd_info *mtd, u_char byte); + uint8_t (*read_byte)(struct mtd_info *mtd); u16 (*read_word)(struct mtd_info *mtd); - void (*write_word)(struct mtd_info *mtd, u16 word); - - void (*write_buf)(struct mtd_info *mtd, const u_char *buf, int len); - void (*read_buf)(struct mtd_info *mtd, u_char *buf, int len); - int (*verify_buf)(struct mtd_info *mtd, const u_char *buf, int len); + void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); + void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); + int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); void (*select_chip)(struct mtd_info *mtd, int chip); int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); - void (*hwcontrol)(struct mtd_info *mtd, int cmd); + void (*cmd_ctrl)(struct mtd_info *mtd, int dat, + unsigned int ctrl); int (*dev_ready)(struct mtd_info *mtd); void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr); - int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state); - int (*calculate_ecc)(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code); - int (*correct_data)(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc); - void (*enable_hwecc)(struct mtd_info *mtd, int mode); + int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); void (*erase_cmd)(struct mtd_info *mtd, int page); int (*scan_bbt)(struct mtd_info *mtd); - int eccmode; - int eccsize; - int eccbytes; - int eccsteps; + int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page); + int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, + const uint8_t *buf, int page, int cached, int raw); + int chip_delay; -#if 0 - spinlock_t chip_lock; - wait_queue_head_t wq; - nand_state_t state; -#endif + unsigned int options; + int page_shift; int phys_erase_shift; int bbt_erase_shift; int chip_shift; - u_char *data_buf; - u_char *oob_buf; - int oobdirty; - u_char *data_poi; - unsigned int options; - int badblockpos; int numchips; unsigned long chipsize; int pagemask; int pagebuf; - struct nand_oobinfo *autooob; + int subpagesize; + uint8_t cellinfo; + int badblockpos; + + nand_state_t state; + + uint8_t *oob_poi; + struct nand_hw_control *controller; + struct nand_ecclayout *ecclayout; + + struct nand_ecc_ctrl ecc; + struct nand_buffers *buffers; + + struct nand_hw_control hwcontrol; + + struct mtd_oob_ops ops; + uint8_t *bbt; struct nand_bbt_descr *bbt_td; struct nand_bbt_descr *bbt_md; + struct nand_bbt_descr *badblock_pattern; - struct nand_hw_control *controller; + void *priv; }; @@ -348,11 +447,11 @@ struct nand_chip { #define NAND_MFR_NATIONAL 0x8f #define NAND_MFR_RENESAS 0x07 #define NAND_MFR_STMICRO 0x20 +#define NAND_MFR_HYNIX 0xad #define NAND_MFR_MICRON 0x2c /** * struct nand_flash_dev - NAND Flash Device ID Structure - * * @name: Identify the device type * @id: device ID code * @pagesize: Pagesize in bytes. Either 256 or 512 or 0 @@ -403,7 +502,7 @@ extern struct nand_manufacturers nand_manuf_ids[]; * blocks is reserved at the end of the device where the tables are * written. * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than - * bad) block in the stored bbt + * bad) block in the stored bbt * @pattern: pattern to identify bad block table or factory marked good / * bad blocks, can be NULL, if len = 0 * @@ -417,11 +516,11 @@ struct nand_bbt_descr { int pages[NAND_MAX_CHIPS]; int offs; int veroffs; - uint8_t version[NAND_MAX_CHIPS]; + uint8_t version[NAND_MAX_CHIPS]; int len; int maxblocks; int reserved_block_code; - uint8_t *pattern; + uint8_t *pattern; }; /* Options for the bad block table descriptors */ @@ -433,7 +532,7 @@ struct nand_bbt_descr { #define NAND_BBT_4BIT 0x00000004 #define NAND_BBT_8BIT 0x00000008 /* The bad block table is in the last good block of the device */ -#define NAND_BBT_LASTBLOCK 0x00000010 +#define NAND_BBT_LASTBLOCK 0x00000010 /* The bbt is at the given page, else we must scan for the bbt */ #define NAND_BBT_ABSPAGE 0x00000020 /* The bbt is at the given page, else we must scan for the bbt */ @@ -456,13 +555,16 @@ struct nand_bbt_descr { #define NAND_BBT_SCAN2NDPAGE 0x00004000 /* The maximum number of blocks to scan for a bbt */ -#define NAND_BBT_SCAN_MAXBLOCKS 4 +#define NAND_BBT_SCAN_MAXBLOCKS 4 -extern int nand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd); -extern int nand_update_bbt (struct mtd_info *mtd, loff_t offs); -extern int nand_default_bbt (struct mtd_info *mtd); -extern int nand_isbad_bbt (struct mtd_info *mtd, loff_t offs, int allowbbt); -extern int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbbt); +extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd); +extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs); +extern int nand_default_bbt(struct mtd_info *mtd); +extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); +extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, + int allowbbt); +extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, + size_t * retlen, uint8_t * buf); /* * Constants for oob configuration @@ -470,4 +572,67 @@ extern int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int #define NAND_SMALL_BADBLOCK_POS 5 #define NAND_LARGE_BADBLOCK_POS 0 +/** + * struct platform_nand_chip - chip level device structure + * @nr_chips: max. number of chips to scan for + * @chip_offset: chip number offset + * @nr_partitions: number of partitions pointed to by partitions (or zero) + * @partitions: mtd partition list + * @chip_delay: R/B delay value in us + * @options: Option flags, e.g. 16bit buswidth + * @ecclayout: ecc layout info structure + * @part_probe_types: NULL-terminated array of probe types + * @priv: hardware controller specific settings + */ +struct platform_nand_chip { + int nr_chips; + int chip_offset; + int nr_partitions; + struct mtd_partition *partitions; + struct nand_ecclayout *ecclayout; + int chip_delay; + unsigned int options; + const char **part_probe_types; + void *priv; +}; + +/** + * struct platform_nand_ctrl - controller level device structure + * @hwcontrol: platform specific hardware control structure + * @dev_ready: platform specific function to read ready/busy pin + * @select_chip: platform specific chip select function + * @cmd_ctrl: platform specific function for controlling + * ALE/CLE/nCE. Also used to write command and address + * @priv: private data to transport driver specific settings + * + * All fields are optional and depend on the hardware driver requirements + */ +struct platform_nand_ctrl { + void (*hwcontrol)(struct mtd_info *mtd, int cmd); + int (*dev_ready)(struct mtd_info *mtd); + void (*select_chip)(struct mtd_info *mtd, int chip); + void (*cmd_ctrl)(struct mtd_info *mtd, int dat, + unsigned int ctrl); + void *priv; +}; + +/** + * struct platform_nand_data - container structure for platform-specific data + * @chip: chip level chip structure + * @ctrl: controller level device structure + */ +struct platform_nand_data { + struct platform_nand_chip chip; + struct platform_nand_ctrl ctrl; +}; + +/* Some helpers to access the data structures */ +static inline +struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + + return chip->priv; +} + #endif /* __LINUX_MTD_NAND_H */ diff --git a/include/linux/mtd/nand_ids.h b/include/linux/mtd/nand_ids.h index d9eb911..e7aa26d 100644 --- a/include/linux/mtd/nand_ids.h +++ b/include/linux/mtd/nand_ids.h @@ -28,7 +28,7 @@ #ifndef __LINUX_MTD_NAND_IDS_H #define __LINUX_MTD_NAND_IDS_H -#ifndef CFG_NAND_LEGACY +#ifndef CONFIG_NAND_LEGACY #error This module is for the legacy NAND support #endif diff --git a/include/linux/mtd/nand_legacy.h b/include/linux/mtd/nand_legacy.h index b05e726..4494bc5 100644 --- a/include/linux/mtd/nand_legacy.h +++ b/include/linux/mtd/nand_legacy.h @@ -36,7 +36,7 @@ #ifndef __LINUX_MTD_NAND_LEGACY_H #define __LINUX_MTD_NAND_LEGACY_H -#ifndef CFG_NAND_LEGACY +#ifndef CONFIG_NAND_LEGACY #error This module is for the legacy NAND support #endif diff --git a/include/linux/mtd/nftl-user.h b/include/linux/mtd/nftl-user.h new file mode 100644 index 0000000..b2bca18 --- /dev/null +++ b/include/linux/mtd/nftl-user.h @@ -0,0 +1,76 @@ +/* + * $Id: nftl-user.h,v 1.2 2005/11/07 11:14:56 gleixner Exp $ + * + * Parts of NFTL headers shared with userspace + * + */ + +#ifndef __MTD_NFTL_USER_H__ +#define __MTD_NFTL_USER_H__ + +/* Block Control Information */ + +struct nftl_bci { + unsigned char ECCSig[6]; + uint8_t Status; + uint8_t Status1; +}__attribute__((packed)); + +/* Unit Control Information */ + +struct nftl_uci0 { + uint16_t VirtUnitNum; + uint16_t ReplUnitNum; + uint16_t SpareVirtUnitNum; + uint16_t SpareReplUnitNum; +} __attribute__((packed)); + +struct nftl_uci1 { + uint32_t WearInfo; + uint16_t EraseMark; + uint16_t EraseMark1; +} __attribute__((packed)); + +struct nftl_uci2 { + uint16_t FoldMark; + uint16_t FoldMark1; + uint32_t unused; +} __attribute__((packed)); + +union nftl_uci { + struct nftl_uci0 a; + struct nftl_uci1 b; + struct nftl_uci2 c; +}; + +struct nftl_oob { + struct nftl_bci b; + union nftl_uci u; +}; + +/* NFTL Media Header */ + +struct NFTLMediaHeader { + char DataOrgID[6]; + uint16_t NumEraseUnits; + uint16_t FirstPhysicalEUN; + uint32_t FormattedSize; + unsigned char UnitSizeFactor; +} __attribute__((packed)); + +#define MAX_ERASE_ZONES (8192 - 512) + +#define ERASE_MARK 0x3c69 +#define SECTOR_FREE 0xff +#define SECTOR_USED 0x55 +#define SECTOR_IGNORE 0x11 +#define SECTOR_DELETED 0x00 + +#define FOLD_MARK_IN_PROGRESS 0x5555 + +#define ZONE_GOOD 0xff +#define ZONE_BAD_ORIGINAL 0 +#define ZONE_BAD_MARKED 7 + + +#endif /* __MTD_NFTL_USER_H__ */ diff --git a/include/linux/mtd/nftl.h b/include/linux/mtd/nftl.h index b0337c3..04963a5 100644 --- a/include/linux/mtd/nftl.h +++ b/include/linux/mtd/nftl.h @@ -1,75 +1,16 @@ - -/* Defines for NAND Flash Translation Layer */ -/* (c) 1999 Machine Vision Holdings, Inc. */ -/* Author: David Woodhouse <dwmw2@mvhi.com> */ -/* $Id: nftl.h,v 1.10 2000/12/29 00:25:38 dwmw2 Exp $ */ +/* + * $Id: nftl.h,v 1.16 2004/06/30 14:49:00 dbrown Exp $ + * + * (C) 1999-2003 David Woodhouse <dwmw2@infradead.org> + */ #ifndef __MTD_NFTL_H__ #define __MTD_NFTL_H__ -/* Block Control Information */ - -struct nftl_bci { - unsigned char ECCSig[6]; - __u8 Status; - __u8 Status1; -}__attribute__((packed)); - -/* Unit Control Information */ - -struct nftl_uci0 { - __u16 VirtUnitNum; - __u16 ReplUnitNum; - __u16 SpareVirtUnitNum; - __u16 SpareReplUnitNum; -} __attribute__((packed)); - -struct nftl_uci1 { - __u32 WearInfo; - __u16 EraseMark; - __u16 EraseMark1; -} __attribute__((packed)); +#include <linux/mtd/mtd.h> +#include <linux/mtd/blktrans.h> -struct nftl_uci2 { - __u16 FoldMark; - __u16 FoldMark1; - __u32 unused; -} __attribute__((packed)); - -union nftl_uci { - struct nftl_uci0 a; - struct nftl_uci1 b; - struct nftl_uci2 c; -}; - -struct nftl_oob { - struct nftl_bci b; - union nftl_uci u; -}; - -/* NFTL Media Header */ - -struct NFTLMediaHeader { - char DataOrgID[6]; - __u16 NumEraseUnits; - __u16 FirstPhysicalEUN; - __u32 FormattedSize; - unsigned char UnitSizeFactor; -} __attribute__((packed)); - -#define MAX_ERASE_ZONES (8192 - 512) - -#define ERASE_MARK 0x3c69 -#define SECTOR_FREE 0xff -#define SECTOR_USED 0x55 -#define SECTOR_IGNORE 0x11 -#define SECTOR_DELETED 0x00 - -#define FOLD_MARK_IN_PROGRESS 0x5555 - -#define ZONE_GOOD 0xff -#define ZONE_BAD_ORIGINAL 0 -#define ZONE_BAD_MARKED 7 +#include <linux/mtd/nftl-user.h> /* these info are used in ReplUnitTable */ #define BLOCK_NIL 0xffff /* last block of a chain */ @@ -78,7 +19,7 @@ struct NFTLMediaHeader { #define BLOCK_RESERVED 0xfffc /* bios block or bad block */ struct NFTLrecord { - struct DiskOnChip *mtd; + struct mtd_blktrans_dev mbd; __u16 MediaUnit, SpareMediaUnit; __u32 EraseSize; struct NFTLMediaHeader MediaHdr; @@ -90,16 +31,24 @@ struct NFTLrecord { __u16 lastEUN; /* should be suppressed */ __u16 numfreeEUNs; __u16 LastFreeEUN; /* To speed up finding a free EUN */ - __u32 nr_sects; int head,sect,cyl; __u16 *EUNtable; /* [numvunits]: First EUN for each virtual unit */ __u16 *ReplUnitTable; /* [numEUNs]: ReplUnitNumber for each */ - unsigned int nb_blocks; /* number of physical blocks */ - unsigned int nb_boot_blocks; /* number of blocks used by the bios */ + unsigned int nb_blocks; /* number of physical blocks */ + unsigned int nb_boot_blocks; /* number of blocks used by the bios */ + struct erase_info instr; + struct nand_ecclayout oobinfo; }; +int NFTL_mount(struct NFTLrecord *s); +int NFTL_formatblock(struct NFTLrecord *s, int block); + +#ifndef NFTL_MAJOR +#define NFTL_MAJOR 93 +#endif + #define MAX_NFTLS 16 -#define MAX_SECTORS_PER_UNIT 32 +#define MAX_SECTORS_PER_UNIT 64 #define NFTL_PARTN_BITS 4 #endif /* __MTD_NFTL_H__ */ diff --git a/include/linux/mtd/ubi-header.h b/include/linux/mtd/ubi-header.h new file mode 100644 index 0000000..fa479c7 --- /dev/null +++ b/include/linux/mtd/ubi-header.h @@ -0,0 +1,360 @@ +/* + * Copyright (c) International Business Machines Corp., 2006 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + * the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Authors: Artem Bityutskiy (Битюцкий Ðртём) + * Thomas Gleixner + * Frank Haverkamp + * Oliver Lohmann + * Andreas Arnez + */ + +/* + * This file defines the layout of UBI headers and all the other UBI on-flash + * data structures. May be included by user-space. + */ + +#ifndef __UBI_HEADER_H__ +#define __UBI_HEADER_H__ + +#include <asm/byteorder.h> + +/* The version of UBI images supported by this implementation */ +#define UBI_VERSION 1 + +/* The highest erase counter value supported by this implementation */ +#define UBI_MAX_ERASECOUNTER 0x7FFFFFFF + +/* The initial CRC32 value used when calculating CRC checksums */ +#define UBI_CRC32_INIT 0xFFFFFFFFU + +/* Erase counter header magic number (ASCII "UBI#") */ +#define UBI_EC_HDR_MAGIC 0x55424923 +/* Volume identifier header magic number (ASCII "UBI!") */ +#define UBI_VID_HDR_MAGIC 0x55424921 + +/* + * Volume type constants used in the volume identifier header. + * + * @UBI_VID_DYNAMIC: dynamic volume + * @UBI_VID_STATIC: static volume + */ +enum { + UBI_VID_DYNAMIC = 1, + UBI_VID_STATIC = 2 +}; + +/* + * Compatibility constants used by internal volumes. + * + * @UBI_COMPAT_DELETE: delete this internal volume before anything is written + * to the flash + * @UBI_COMPAT_RO: attach this device in read-only mode + * @UBI_COMPAT_PRESERVE: preserve this internal volume - do not touch its + * physical eraseblocks, don't allow the wear-leveling unit to move them + * @UBI_COMPAT_REJECT: reject this UBI image + */ +enum { + UBI_COMPAT_DELETE = 1, + UBI_COMPAT_RO = 2, + UBI_COMPAT_PRESERVE = 4, + UBI_COMPAT_REJECT = 5 +}; + +/* + * ubi16_t/ubi32_t/ubi64_t - 16, 32, and 64-bit integers used in UBI on-flash + * data structures. + */ +typedef struct { + uint16_t int16; +} __attribute__ ((packed)) ubi16_t; + +typedef struct { + uint32_t int32; +} __attribute__ ((packed)) ubi32_t; + +typedef struct { + uint64_t int64; +} __attribute__ ((packed)) ubi64_t; + +/* + * In this implementation of UBI uses the big-endian format for on-flash + * integers. The below are the corresponding conversion macros. + */ +#define cpu_to_ubi16(x) ((ubi16_t){__cpu_to_be16(x)}) +#define ubi16_to_cpu(x) ((uint16_t)__be16_to_cpu((x).int16)) + +#define cpu_to_ubi32(x) ((ubi32_t){__cpu_to_be32(x)}) +#define ubi32_to_cpu(x) ((uint32_t)__be32_to_cpu((x).int32)) + +#define cpu_to_ubi64(x) ((ubi64_t){__cpu_to_be64(x)}) +#define ubi64_to_cpu(x) ((uint64_t)__be64_to_cpu((x).int64)) + +/* Sizes of UBI headers */ +#define UBI_EC_HDR_SIZE sizeof(struct ubi_ec_hdr) +#define UBI_VID_HDR_SIZE sizeof(struct ubi_vid_hdr) + +/* Sizes of UBI headers without the ending CRC */ +#define UBI_EC_HDR_SIZE_CRC (UBI_EC_HDR_SIZE - sizeof(ubi32_t)) +#define UBI_VID_HDR_SIZE_CRC (UBI_VID_HDR_SIZE - sizeof(ubi32_t)) + +/** + * struct ubi_ec_hdr - UBI erase counter header. + * @magic: erase counter header magic number (%UBI_EC_HDR_MAGIC) + * @version: version of UBI implementation which is supposed to accept this + * UBI image + * @padding1: reserved for future, zeroes + * @ec: the erase counter + * @vid_hdr_offset: where the VID header starts + * @data_offset: where the user data start + * @padding2: reserved for future, zeroes + * @hdr_crc: erase counter header CRC checksum + * + * The erase counter header takes 64 bytes and has a plenty of unused space for + * future usage. The unused fields are zeroed. The @version field is used to + * indicate the version of UBI implementation which is supposed to be able to + * work with this UBI image. If @version is greater then the current UBI + * version, the image is rejected. This may be useful in future if something + * is changed radically. This field is duplicated in the volume identifier + * header. + * + * The @vid_hdr_offset and @data_offset fields contain the offset of the the + * volume identifier header and user data, relative to the beginning of the + * physical eraseblock. These values have to be the same for all physical + * eraseblocks. + */ +struct ubi_ec_hdr { + ubi32_t magic; + uint8_t version; + uint8_t padding1[3]; + ubi64_t ec; /* Warning: the current limit is 31-bit anyway! */ + ubi32_t vid_hdr_offset; + ubi32_t data_offset; + uint8_t padding2[36]; + ubi32_t hdr_crc; +} __attribute__ ((packed)); + +/** + * struct ubi_vid_hdr - on-flash UBI volume identifier header. + * @magic: volume identifier header magic number (%UBI_VID_HDR_MAGIC) + * @version: UBI implementation version which is supposed to accept this UBI + * image (%UBI_VERSION) + * @vol_type: volume type (%UBI_VID_DYNAMIC or %UBI_VID_STATIC) + * @copy_flag: if this logical eraseblock was copied from another physical + * eraseblock (for wear-leveling reasons) + * @compat: compatibility of this volume (%0, %UBI_COMPAT_DELETE, + * %UBI_COMPAT_IGNORE, %UBI_COMPAT_PRESERVE, or %UBI_COMPAT_REJECT) + * @vol_id: ID of this volume + * @lnum: logical eraseblock number + * @leb_ver: version of this logical eraseblock (IMPORTANT: obsolete, to be + * removed, kept only for not breaking older UBI users) + * @data_size: how many bytes of data this logical eraseblock contains + * @used_ebs: total number of used logical eraseblocks in this volume + * @data_pad: how many bytes at the end of this physical eraseblock are not + * used + * @data_crc: CRC checksum of the data stored in this logical eraseblock + * @padding1: reserved for future, zeroes + * @sqnum: sequence number + * @padding2: reserved for future, zeroes + * @hdr_crc: volume identifier header CRC checksum + * + * The @sqnum is the value of the global sequence counter at the time when this + * VID header was created. The global sequence counter is incremented each time + * UBI writes a new VID header to the flash, i.e. when it maps a logical + * eraseblock to a new physical eraseblock. The global sequence counter is an + * unsigned 64-bit integer and we assume it never overflows. The @sqnum + * (sequence number) is used to distinguish between older and newer versions of + * logical eraseblocks. + * + * There are 2 situations when there may be more then one physical eraseblock + * corresponding to the same logical eraseblock, i.e., having the same @vol_id + * and @lnum values in the volume identifier header. Suppose we have a logical + * eraseblock L and it is mapped to the physical eraseblock P. + * + * 1. Because UBI may erase physical eraseblocks asynchronously, the following + * situation is possible: L is asynchronously erased, so P is scheduled for + * erasure, then L is written to,i.e. mapped to another physical eraseblock P1, + * so P1 is written to, then an unclean reboot happens. Result - there are 2 + * physical eraseblocks P and P1 corresponding to the same logical eraseblock + * L. But P1 has greater sequence number, so UBI picks P1 when it attaches the + * flash. + * + * 2. From time to time UBI moves logical eraseblocks to other physical + * eraseblocks for wear-leveling reasons. If, for example, UBI moves L from P + * to P1, and an unclean reboot happens before P is physically erased, there + * are two physical eraseblocks P and P1 corresponding to L and UBI has to + * select one of them when the flash is attached. The @sqnum field says which + * PEB is the original (obviously P will have lower @sqnum) and the copy. But + * it is not enough to select the physical eraseblock with the higher sequence + * number, because the unclean reboot could have happen in the middle of the + * copying process, so the data in P is corrupted. It is also not enough to + * just select the physical eraseblock with lower sequence number, because the + * data there may be old (consider a case if more data was added to P1 after + * the copying). Moreover, the unclean reboot may happen when the erasure of P + * was just started, so it result in unstable P, which is "mostly" OK, but + * still has unstable bits. + * + * UBI uses the @copy_flag field to indicate that this logical eraseblock is a + * copy. UBI also calculates data CRC when the data is moved and stores it at + * the @data_crc field of the copy (P1). So when UBI needs to pick one physical + * eraseblock of two (P or P1), the @copy_flag of the newer one (P1) is + * examined. If it is cleared, the situation* is simple and the newer one is + * picked. If it is set, the data CRC of the copy (P1) is examined. If the CRC + * checksum is correct, this physical eraseblock is selected (P1). Otherwise + * the older one (P) is selected. + * + * Note, there is an obsolete @leb_ver field which was used instead of @sqnum + * in the past. But it is not used anymore and we keep it in order to be able + * to deal with old UBI images. It will be removed at some point. + * + * There are 2 sorts of volumes in UBI: user volumes and internal volumes. + * Internal volumes are not seen from outside and are used for various internal + * UBI purposes. In this implementation there is only one internal volume - the + * layout volume. Internal volumes are the main mechanism of UBI extensions. + * For example, in future one may introduce a journal internal volume. Internal + * volumes have their own reserved range of IDs. + * + * The @compat field is only used for internal volumes and contains the "degree + * of their compatibility". It is always zero for user volumes. This field + * provides a mechanism to introduce UBI extensions and to be still compatible + * with older UBI binaries. For example, if someone introduced a journal in + * future, he would probably use %UBI_COMPAT_DELETE compatibility for the + * journal volume. And in this case, older UBI binaries, which know nothing + * about the journal volume, would just delete this volume and work perfectly + * fine. This is similar to what Ext2fs does when it is fed by an Ext3fs image + * - it just ignores the Ext3fs journal. + * + * The @data_crc field contains the CRC checksum of the contents of the logical + * eraseblock if this is a static volume. In case of dynamic volumes, it does + * not contain the CRC checksum as a rule. The only exception is when the + * data of the physical eraseblock was moved by the wear-leveling unit, then + * the wear-leveling unit calculates the data CRC and stores it in the + * @data_crc field. And of course, the @copy_flag is %in this case. + * + * The @data_size field is used only for static volumes because UBI has to know + * how many bytes of data are stored in this eraseblock. For dynamic volumes, + * this field usually contains zero. The only exception is when the data of the + * physical eraseblock was moved to another physical eraseblock for + * wear-leveling reasons. In this case, UBI calculates CRC checksum of the + * contents and uses both @data_crc and @data_size fields. In this case, the + * @data_size field contains data size. + * + * The @used_ebs field is used only for static volumes and indicates how many + * eraseblocks the data of the volume takes. For dynamic volumes this field is + * not used and always contains zero. + * + * The @data_pad is calculated when volumes are created using the alignment + * parameter. So, effectively, the @data_pad field reduces the size of logical + * eraseblocks of this volume. This is very handy when one uses block-oriented + * software (say, cramfs) on top of the UBI volume. + */ +struct ubi_vid_hdr { + ubi32_t magic; + uint8_t version; + uint8_t vol_type; + uint8_t copy_flag; + uint8_t compat; + ubi32_t vol_id; + ubi32_t lnum; + ubi32_t leb_ver; /* obsolete, to be removed, don't use */ + ubi32_t data_size; + ubi32_t used_ebs; + ubi32_t data_pad; + ubi32_t data_crc; + uint8_t padding1[4]; + ubi64_t sqnum; + uint8_t padding2[12]; + ubi32_t hdr_crc; +} __attribute__ ((packed)); + +/* Internal UBI volumes count */ +#define UBI_INT_VOL_COUNT 1 + +/* + * Starting ID of internal volumes. There is reserved room for 4096 internal + * volumes. + */ +#define UBI_INTERNAL_VOL_START (0x7FFFFFFF - 4096) + +/* The layout volume contains the volume table */ + +#define UBI_LAYOUT_VOL_ID UBI_INTERNAL_VOL_START +#define UBI_LAYOUT_VOLUME_EBS 2 +#define UBI_LAYOUT_VOLUME_NAME "layout volume" +#define UBI_LAYOUT_VOLUME_COMPAT UBI_COMPAT_REJECT + +/* The maximum number of volumes per one UBI device */ +#define UBI_MAX_VOLUMES 128 + +/* The maximum volume name length */ +#define UBI_VOL_NAME_MAX 127 + +/* Size of the volume table record */ +#define UBI_VTBL_RECORD_SIZE sizeof(struct ubi_vtbl_record) + +/* Size of the volume table record without the ending CRC */ +#define UBI_VTBL_RECORD_SIZE_CRC (UBI_VTBL_RECORD_SIZE - sizeof(ubi32_t)) + +/** + * struct ubi_vtbl_record - a record in the volume table. + * @reserved_pebs: how many physical eraseblocks are reserved for this volume + * @alignment: volume alignment + * @data_pad: how many bytes are unused at the end of the each physical + * eraseblock to satisfy the requested alignment + * @vol_type: volume type (%UBI_DYNAMIC_VOLUME or %UBI_STATIC_VOLUME) + * @upd_marker: if volume update was started but not finished + * @name_len: volume name length + * @name: the volume name + * @padding2: reserved, zeroes + * @crc: a CRC32 checksum of the record + * + * The volume table records are stored in the volume table, which is stored in + * the layout volume. The layout volume consists of 2 logical eraseblock, each + * of which contains a copy of the volume table (i.e., the volume table is + * duplicated). The volume table is an array of &struct ubi_vtbl_record + * objects indexed by the volume ID. + * + * If the size of the logical eraseblock is large enough to fit + * %UBI_MAX_VOLUMES records, the volume table contains %UBI_MAX_VOLUMES + * records. Otherwise, it contains as many records as it can fit (i.e., size of + * logical eraseblock divided by sizeof(struct ubi_vtbl_record)). + * + * The @upd_marker flag is used to implement volume update. It is set to %1 + * before update and set to %0 after the update. So if the update operation was + * interrupted, UBI knows that the volume is corrupted. + * + * The @alignment field is specified when the volume is created and cannot be + * later changed. It may be useful, for example, when a block-oriented file + * system works on top of UBI. The @data_pad field is calculated using the + * logical eraseblock size and @alignment. The alignment must be multiple to the + * minimal flash I/O unit. If @alignment is 1, all the available space of + * the physical eraseblocks is used. + * + * Empty records contain all zeroes and the CRC checksum of those zeroes. + */ +struct ubi_vtbl_record { + ubi32_t reserved_pebs; + ubi32_t alignment; + ubi32_t data_pad; + uint8_t vol_type; + uint8_t upd_marker; + ubi16_t name_len; + uint8_t name[UBI_VOL_NAME_MAX+1]; + uint8_t padding2[24]; + ubi32_t crc; +} __attribute__ ((packed)); + +#endif /* !__UBI_HEADER_H__ */ diff --git a/include/linux/mtd/ubi-user.h b/include/linux/mtd/ubi-user.h new file mode 100644 index 0000000..fe06ded --- /dev/null +++ b/include/linux/mtd/ubi-user.h @@ -0,0 +1,161 @@ +/* + * Copyright (c) International Business Machines Corp., 2006 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + * the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Author: Artem Bityutskiy (Битюцкий Ðртём) + */ + +#ifndef __UBI_USER_H__ +#define __UBI_USER_H__ + +/* + * UBI volume creation + * ~~~~~~~~~~~~~~~~~~~ + * + * UBI volumes are created via the %UBI_IOCMKVOL IOCTL command of UBI character + * device. A &struct ubi_mkvol_req object has to be properly filled and a + * pointer to it has to be passed to the IOCTL. + * + * UBI volume deletion + * ~~~~~~~~~~~~~~~~~~~ + * + * To delete a volume, the %UBI_IOCRMVOL IOCTL command of the UBI character + * device should be used. A pointer to the 32-bit volume ID hast to be passed + * to the IOCTL. + * + * UBI volume re-size + * ~~~~~~~~~~~~~~~~~~ + * + * To re-size a volume, the %UBI_IOCRSVOL IOCTL command of the UBI character + * device should be used. A &struct ubi_rsvol_req object has to be properly + * filled and a pointer to it has to be passed to the IOCTL. + * + * UBI volume update + * ~~~~~~~~~~~~~~~~~ + * + * Volume update should be done via the %UBI_IOCVOLUP IOCTL command of the + * corresponding UBI volume character device. A pointer to a 64-bit update + * size should be passed to the IOCTL. After then, UBI expects user to write + * this number of bytes to the volume character device. The update is finished + * when the claimed number of bytes is passed. So, the volume update sequence + * is something like: + * + * fd = open("/dev/my_volume"); + * ioctl(fd, UBI_IOCVOLUP, &image_size); + * write(fd, buf, image_size); + * close(fd); + */ + +/* + * When a new volume is created, users may either specify the volume number they + * want to create or to let UBI automatically assign a volume number using this + * constant. + */ +#define UBI_VOL_NUM_AUTO (-1) + +/* Maximum volume name length */ +#define UBI_MAX_VOLUME_NAME 127 + +/* IOCTL commands of UBI character devices */ + +#define UBI_IOC_MAGIC 'o' + +/* Create an UBI volume */ +#define UBI_IOCMKVOL _IOW(UBI_IOC_MAGIC, 0, struct ubi_mkvol_req) +/* Remove an UBI volume */ +#define UBI_IOCRMVOL _IOW(UBI_IOC_MAGIC, 1, int32_t) +/* Re-size an UBI volume */ +#define UBI_IOCRSVOL _IOW(UBI_IOC_MAGIC, 2, struct ubi_rsvol_req) + +/* IOCTL commands of UBI volume character devices */ + +#define UBI_VOL_IOC_MAGIC 'O' + +/* Start UBI volume update */ +#define UBI_IOCVOLUP _IOW(UBI_VOL_IOC_MAGIC, 0, int64_t) +/* An eraseblock erasure command, used for debugging, disabled by default */ +#define UBI_IOCEBER _IOW(UBI_VOL_IOC_MAGIC, 1, int32_t) + +/* + * UBI volume type constants. + * + * @UBI_DYNAMIC_VOLUME: dynamic volume + * @UBI_STATIC_VOLUME: static volume + */ +enum { + UBI_DYNAMIC_VOLUME = 3, + UBI_STATIC_VOLUME = 4 +}; + +/** + * struct ubi_mkvol_req - volume description data structure used in + * volume creation requests. + * @vol_id: volume number + * @alignment: volume alignment + * @bytes: volume size in bytes + * @vol_type: volume type (%UBI_DYNAMIC_VOLUME or %UBI_STATIC_VOLUME) + * @padding1: reserved for future, not used + * @name_len: volume name length + * @padding2: reserved for future, not used + * @name: volume name + * + * This structure is used by userspace programs when creating new volumes. The + * @used_bytes field is only necessary when creating static volumes. + * + * The @alignment field specifies the required alignment of the volume logical + * eraseblock. This means, that the size of logical eraseblocks will be aligned + * to this number, i.e., + * (UBI device logical eraseblock size) mod (@alignment) = 0. + * + * To put it differently, the logical eraseblock of this volume may be slightly + * shortened in order to make it properly aligned. The alignment has to be + * multiple of the flash minimal input/output unit, or %1 to utilize the entire + * available space of logical eraseblocks. + * + * The @alignment field may be useful, for example, when one wants to maintain + * a block device on top of an UBI volume. In this case, it is desirable to fit + * an integer number of blocks in logical eraseblocks of this UBI volume. With + * alignment it is possible to update this volume using plane UBI volume image + * BLOBs, without caring about how to properly align them. + */ +struct ubi_mkvol_req { + int32_t vol_id; + int32_t alignment; + int64_t bytes; + int8_t vol_type; + int8_t padding1; + int16_t name_len; + int8_t padding2[4]; + char name[UBI_MAX_VOLUME_NAME+1]; +} __attribute__ ((packed)); + +/** + * struct ubi_rsvol_req - a data structure used in volume re-size requests. + * @vol_id: ID of the volume to re-size + * @bytes: new size of the volume in bytes + * + * Re-sizing is possible for both dynamic and static volumes. But while dynamic + * volumes may be re-sized arbitrarily, static volumes cannot be made to be + * smaller then the number of bytes they bear. To arbitrarily shrink a static + * volume, it must be wiped out first (by means of volume update operation with + * zero number of bytes). + */ +struct ubi_rsvol_req { + int64_t bytes; + int32_t vol_id; +} __attribute__ ((packed)); + +#endif /* __UBI_USER_H__ */ diff --git a/include/mpc512x.h b/include/mpc512x.h index b4cc2b9..a76b1ca 100644 --- a/include/mpc512x.h +++ b/include/mpc512x.h @@ -347,41 +347,226 @@ /* IO Control Register */ +#define IOCTL_MEM 0x000 +#define IOCTL_GP 0x004 +#define IOCTL_LPC_CLK 0x008 +#define IOCTL_LPC_OE 0x00C +#define IOCTL_LPC_RWB 0x010 +#define IOCTL_LPC_ACK 0x014 +#define IOCTL_LPC_CS0 0x018 +#define IOCTL_NFC_CE0 0x01C +#define IOCTL_LPC_CS1 0x020 +#define IOCTL_LPC_CS2 0x024 +#define IOCTL_LPC_AX03 0x028 +#define IOCTL_EMB_AX02 0x02C +#define IOCTL_EMB_AX01 0x030 +#define IOCTL_EMB_AX00 0x034 +#define IOCTL_EMB_AD31 0x038 +#define IOCTL_EMB_AD30 0x03C +#define IOCTL_EMB_AD29 0x040 +#define IOCTL_EMB_AD28 0x044 +#define IOCTL_EMB_AD27 0x048 +#define IOCTL_EMB_AD26 0x04C +#define IOCTL_EMB_AD25 0x050 +#define IOCTL_EMB_AD24 0x054 +#define IOCTL_EMB_AD23 0x058 +#define IOCTL_EMB_AD22 0x05C +#define IOCTL_EMB_AD21 0x060 +#define IOCTL_EMB_AD20 0x064 +#define IOCTL_EMB_AD19 0x068 +#define IOCTL_EMB_AD18 0x06C +#define IOCTL_EMB_AD17 0x070 +#define IOCTL_EMB_AD16 0x074 +#define IOCTL_EMB_AD15 0x078 +#define IOCTL_EMB_AD14 0x07C +#define IOCTL_EMB_AD13 0x080 +#define IOCTL_EMB_AD12 0x084 +#define IOCTL_EMB_AD11 0x088 +#define IOCTL_EMB_AD10 0x08C +#define IOCTL_EMB_AD09 0x090 +#define IOCTL_EMB_AD08 0x094 +#define IOCTL_EMB_AD07 0x098 +#define IOCTL_EMB_AD06 0x09C +#define IOCTL_EMB_AD05 0x0A0 +#define IOCTL_EMB_AD04 0x0A4 +#define IOCTL_EMB_AD03 0x0A8 +#define IOCTL_EMB_AD02 0x0AC +#define IOCTL_EMB_AD01 0x0B0 +#define IOCTL_EMB_AD00 0x0B4 +#define IOCTL_PATA_CE1 0x0B8 +#define IOCTL_PATA_CE2 0x0BC +#define IOCTL_PATA_ISOLATE 0x0C0 +#define IOCTL_PATA_IOR 0x0C4 +#define IOCTL_PATA_IOW 0x0C8 +#define IOCTL_PATA_IOCHRDY 0x0CC +#define IOCTL_PATA_INTRQ 0x0D0 +#define IOCTL_PATA_DRQ 0x0D4 +#define IOCTL_PATA_DACK 0x0D8 +#define IOCTL_NFC_WP 0x0DC +#define IOCTL_NFC_RB 0x0E0 +#define IOCTL_NFC_ALE 0x0E4 +#define IOCTL_NFC_CLE 0x0E8 +#define IOCTL_NFC_WE 0x0EC +#define IOCTL_NFC_RE 0x0F0 +#define IOCTL_PCI_AD31 0x0F4 +#define IOCTL_PCI_AD30 0x0F8 +#define IOCTL_PCI_AD29 0x0FC +#define IOCTL_PCI_AD28 0x100 +#define IOCTL_PCI_AD27 0x104 +#define IOCTL_PCI_AD26 0x108 +#define IOCTL_PCI_AD25 0x10C +#define IOCTL_PCI_AD24 0x110 +#define IOCTL_PCI_AD23 0x114 +#define IOCTL_PCI_AD22 0x118 +#define IOCTL_PCI_AD21 0x11C +#define IOCTL_PCI_AD20 0x120 +#define IOCTL_PCI_AD19 0x124 +#define IOCTL_PCI_AD18 0x128 +#define IOCTL_PCI_AD17 0x12C +#define IOCTL_PCI_AD16 0x130 +#define IOCTL_PCI_AD15 0x134 +#define IOCTL_PCI_AD14 0x138 +#define IOCTL_PCI_AD13 0x13C +#define IOCTL_PCI_AD12 0x140 +#define IOCTL_PCI_AD11 0x144 +#define IOCTL_PCI_AD10 0x148 +#define IOCTL_PCI_AD09 0x14C +#define IOCTL_PCI_AD08 0x150 +#define IOCTL_PCI_AD07 0x154 +#define IOCTL_PCI_AD06 0x158 +#define IOCTL_PCI_AD05 0x15C +#define IOCTL_PCI_AD04 0x160 +#define IOCTL_PCI_AD03 0x164 +#define IOCTL_PCI_AD02 0x168 +#define IOCTL_PCI_AD01 0x16C +#define IOCTL_PCI_AD00 0x170 +#define IOCTL_PCI_CBE0 0x174 +#define IOCTL_PCI_CBE1 0x178 +#define IOCTL_PCI_CBE2 0x17C +#define IOCTL_PCI_CBE3 0x180 +#define IOCTL_PCI_GNT2 0x184 +#define IOCTL_PCI_REQ2 0x188 +#define IOCTL_PCI_GNT1 0x18C +#define IOCTL_PCI_REQ1 0x190 +#define IOCTL_PCI_GNT0 0x194 +#define IOCTL_PCI_REQ0 0x198 +#define IOCTL_PCI_INTA 0x19C +#define IOCTL_PCI_CLK 0x1A0 +#define IOCTL_PCI_RST_OUT 0x1A4 +#define IOCTL_PCI_FRAME 0x1A8 +#define IOCTL_PCI_IDSEL 0x1AC +#define IOCTL_PCI_DEVSEL 0x1B0 +#define IOCTL_PCI_IRDY 0x1B4 +#define IOCTL_PCI_TRDY 0x1B8 +#define IOCTL_PCI_STOP 0x1BC +#define IOCTL_PCI_PAR 0x1C0 +#define IOCTL_PCI_PERR 0x1C4 +#define IOCTL_PCI_SERR 0x1C8 +#define IOCTL_SPDIF_TXCLK 0x1CC +#define IOCTL_SPDIF_TX 0x1D0 +#define IOCTL_SPDIF_RX 0x1D4 +#define IOCTL_I2C0_SCL 0x1D8 +#define IOCTL_I2C0_SDA 0x1DC +#define IOCTL_I2C1_SCL 0x1E0 +#define IOCTL_I2C1_SDA 0x1E4 +#define IOCTL_I2C2_SCL 0x1E8 +#define IOCTL_I2C2_SDA 0x1EC +#define IOCTL_IRQ0 0x1F0 +#define IOCTL_IRQ1 0x1F4 +#define IOCTL_CAN1_TX 0x1F8 +#define IOCTL_CAN2_TX 0x1FC +#define IOCTL_J1850_TX 0x200 +#define IOCTL_J1850_RX 0x204 +#define IOCTL_PSC_MCLK_IN 0x208 +#define IOCTL_PSC0_0 0x20C +#define IOCTL_PSC0_1 0x210 +#define IOCTL_PSC0_2 0x214 +#define IOCTL_PSC0_3 0x218 +#define IOCTL_PSC0_4 0x21C +#define IOCTL_PSC1_0 0x220 +#define IOCTL_PSC1_1 0x224 +#define IOCTL_PSC1_2 0x228 +#define IOCTL_PSC1_3 0x22C +#define IOCTL_PSC1_4 0x230 +#define IOCTL_PSC2_0 0x234 +#define IOCTL_PSC2_1 0x238 +#define IOCTL_PSC2_2 0x23C +#define IOCTL_PSC2_3 0x240 +#define IOCTL_PSC2_4 0x244 +#define IOCTL_PSC3_0 0x248 +#define IOCTL_PSC3_1 0x24C +#define IOCTL_PSC3_2 0x250 +#define IOCTL_PSC3_3 0x254 +#define IOCTL_PSC3_4 0x258 +#define IOCTL_PSC4_0 0x25C +#define IOCTL_PSC4_1 0x260 +#define IOCTL_PSC4_2 0x264 +#define IOCTL_PSC4_3 0x268 +#define IOCTL_PSC4_4 0x26C +#define IOCTL_PSC5_0 0x270 +#define IOCTL_PSC5_1 0x274 +#define IOCTL_PSC5_2 0x278 +#define IOCTL_PSC5_3 0x27C +#define IOCTL_PSC5_4 0x280 +#define IOCTL_PSC6_0 0x284 +#define IOCTL_PSC6_1 0x288 +#define IOCTL_PSC6_2 0x28C +#define IOCTL_PSC6_3 0x290 +#define IOCTL_PSC6_4 0x294 +#define IOCTL_PSC7_0 0x298 +#define IOCTL_PSC7_1 0x29C +#define IOCTL_PSC7_2 0x2A0 +#define IOCTL_PSC7_3 0x2A4 +#define IOCTL_PSC7_4 0x2A8 +#define IOCTL_PSC8_0 0x2AC +#define IOCTL_PSC8_1 0x2B0 +#define IOCTL_PSC8_2 0x2B4 +#define IOCTL_PSC8_3 0x2B8 +#define IOCTL_PSC8_4 0x2BC +#define IOCTL_PSC9_0 0x2C0 +#define IOCTL_PSC9_1 0x2C4 +#define IOCTL_PSC9_2 0x2C8 +#define IOCTL_PSC9_3 0x2CC +#define IOCTL_PSC9_4 0x2D0 +#define IOCTL_PSC10_0 0x2D4 +#define IOCTL_PSC10_1 0x2D8 +#define IOCTL_PSC10_2 0x2DC +#define IOCTL_PSC10_3 0x2E0 +#define IOCTL_PSC10_4 0x2E4 +#define IOCTL_PSC11_0 0x2E8 +#define IOCTL_PSC11_1 0x2EC +#define IOCTL_PSC11_2 0x2F0 +#define IOCTL_PSC11_3 0x2F4 +#define IOCTL_PSC11_4 0x2F8 +#define IOCTL_HRESET 0x2FC +#define IOCTL_SRESET 0x300 +#define IOCTL_CKSTP_OUT 0x304 +#define IOCTL_USB2_VBUS_PWR_FAULT 0x308 +#define IOCTL_USB2_VBUS_PWR_SELECT 0x30C +#define IOCTL_USB2_PHY_DRVV_BUS 0x310 + +#ifndef __ASSEMBLY__ + + +/* IO pin fields */ +#define IO_PIN_FMUX(v) ((v) << 7) /* pin function */ +#define IO_PIN_HOLD(v) ((v) << 5) /* hold time, pci only */ +#define IO_PIN_PUD(v) ((v) << 4) /* if PUE, 0=pull-down, 1=pull-up */ +#define IO_PIN_PUE(v) ((v) << 3) /* pull up/down enable */ +#define IO_PIN_ST(v) ((v) << 2) /* schmitt trigger */ +#define IO_PIN_DS(v) ((v)) /* slew rate */ + +typedef struct iopin_t { + int p_offset; /* offset from IOCTL_MEM_OFFSET */ + int nr_pins; /* number of pins to set this way */ + int bit_or; /* or in the value instead of overwrite */ + u_long val; /* value to write or or */ +}iopin_t; + +void iopin_initialize(iopin_t *,int); +#endif /* Indexes in regs array */ -#define MEM_IDX 0x00 -#define PATA_CE1_IDX 0x2e -#define PATA_CE2_IDX 0x2f -#define PATA_ISOLATE_IDX 0x30 -#define PATA_IOR_IDX 0x31 -#define PATA_IOW_IDX 0x32 -#define PATA_IOCHRDY_IDX 0x33 -#define PATA_INTRQ_IDX 0x34 -#define PATA_DRQ_IDX 0x35 -#define PATA_DACK_IDX 0x36 -#define SPDIF_TXCLOCK_IDX 0x73 -#define SPDIF_TX_IDX 0x74 -#define SPDIF_RX_IDX 0x75 -#define PSC0_0_IDX 0x83 -#define PSC0_1_IDX 0x84 -#define PSC0_2_IDX 0x85 -#define PSC0_3_IDX 0x86 -#define PSC0_4_IDX 0x87 -#define PSC1_0_IDX 0x88 -#define PSC1_1_IDX 0x89 -#define PSC1_2_IDX 0x8a -#define PSC1_3_IDX 0x8b -#define PSC1_4_IDX 0x8c -#define PSC2_0_IDX 0x8d -#define PSC2_1_IDX 0x8e -#define PSC2_2_IDX 0x8f -#define PSC2_3_IDX 0x90 -#define PSC2_4_IDX 0x91 - -#define IOCTRL_FUNCMUX_SHIFT 7 -#define IOCTRL_FUNCMUX_FEC 1 -#define IOCTRL_MUX_FEC (IOCTRL_FUNCMUX_FEC << IOCTRL_FUNCMUX_SHIFT) - /* Set for DDR */ #define IOCTRL_MUX_DDR 0x00000036 diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 897ecd6..70a4de7 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -30,7 +30,9 @@ /* IMMRBAR - Internal Memory Register Base Address */ +#ifndef CONFIG_DEFAULT_IMMR #define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */ +#endif #define IMMRBAR 0x0000 /* Register offset to immr */ #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */ #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) diff --git a/include/nand.h b/include/nand.h index e1285cd..4c2b76d 100644 --- a/include/nand.h +++ b/include/nand.h @@ -26,7 +26,7 @@ extern void nand_init(void); -#ifndef CFG_NAND_LEGACY +#ifndef CONFIG_NAND_LEGACY #include <linux/mtd/compat.h> #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> @@ -84,6 +84,7 @@ struct nand_write_options { }; typedef struct nand_write_options nand_write_options_t; +typedef struct mtd_oob_ops mtd_oob_ops_t; struct nand_read_options { u_char *buffer; /* memory block in which read image is written*/ @@ -107,9 +108,10 @@ struct nand_erase_options { typedef struct nand_erase_options nand_erase_options_t; -int nand_write_opts(nand_info_t *meminfo, const nand_write_options_t *opts); - -int nand_read_opts(nand_info_t *meminfo, const nand_read_options_t *opts); +int nand_read_skip_bad(nand_info_t *nand, size_t offset, size_t *length, + u_char *buffer); +int nand_write_skip_bad(nand_info_t *nand, size_t offset, size_t *length, + u_char *buffer); int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts); #define NAND_LOCK_STATUS_TIGHT 0x01 @@ -124,5 +126,7 @@ int nand_get_lock_status(nand_info_t *meminfo, ulong offset); void board_nand_select_device(struct nand_chip *nand, int chip); #endif -#endif /* !CFG_NAND_LEGACY */ +__attribute__((noreturn)) void nand_boot(void); + +#endif /* !CONFIG_NAND_LEGACY */ #endif diff --git a/include/onenand_uboot.h b/include/onenand_uboot.h index 4449f98..4260ee7 100644 --- a/include/onenand_uboot.h +++ b/include/onenand_uboot.h @@ -39,6 +39,6 @@ extern int onenand_erase(struct mtd_info *mtd, struct erase_info *instr); extern int onenand_unlock(struct mtd_info *mtd, loff_t ofs, size_t len); -extern void onenand_print_device_info(int device, int verbose); +extern char *onenand_print_device_info(int device); #endif /* __UBOOT_ONENAND_H */ diff --git a/include/ppc405.h b/include/ppc405.h index 2231a5f..f19b67f 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -119,367 +119,6 @@ #define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ #define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */ -/****************************************************************************** - * Universal interrupt controller - ******************************************************************************/ -#define UIC_SR 0x0 /* UIC status */ -#define UIC_ER 0x2 /* UIC enable */ -#define UIC_CR 0x3 /* UIC critical */ -#define UIC_PR 0x4 /* UIC polarity */ -#define UIC_TR 0x5 /* UIC triggering */ -#define UIC_MSR 0x6 /* UIC masked status */ -#define UIC_VR 0x7 /* UIC vector */ -#define UIC_VCR 0x8 /* UIC vector configuration */ - -#define UIC_DCR_BASE 0xc0 -#define UIC0_DCR_BASE UIC_DCR_BASE -#define uicsr (UIC_DCR_BASE+0x0) /* UIC status */ -#define uicsrs (UIC_DCR_BASE+0x1) /* UIC status set */ -#define uicer (UIC_DCR_BASE+0x2) /* UIC enable */ -#define uiccr (UIC_DCR_BASE+0x3) /* UIC critical */ -#define uicpr (UIC_DCR_BASE+0x4) /* UIC polarity */ -#define uictr (UIC_DCR_BASE+0x5) /* UIC triggering */ -#define uicmsr (UIC_DCR_BASE+0x6) /* UIC masked status */ -#define uicvr (UIC_DCR_BASE+0x7) /* UIC vector */ -#define uicvcr (UIC_DCR_BASE+0x8) /* UIC vector configuration */ - -#if defined(CONFIG_405EX) -#define uic0sr uicsr /* UIC status */ -#define uic0srs uicsrs /* UIC status set */ -#define uic0er uicer /* UIC enable */ -#define uic0cr uiccr /* UIC critical */ -#define uic0pr uicpr /* UIC polarity */ -#define uic0tr uictr /* UIC triggering */ -#define uic0msr uicmsr /* UIC masked status */ -#define uic0vr uicvr /* UIC vector */ -#define uic0vcr uicvcr /* UIC vector configuration*/ - -#define UIC_DCR_BASE1 0xd0 -#define UIC1_DCR_BASE 0xd0 -#define uic1sr (UIC_DCR_BASE1+0x0) /* UIC status */ -#define uic1srs (UIC_DCR_BASE1+0x1) /* UIC status set */ -#define uic1er (UIC_DCR_BASE1+0x2) /* UIC enable */ -#define uic1cr (UIC_DCR_BASE1+0x3) /* UIC critical */ -#define uic1pr (UIC_DCR_BASE1+0x4) /* UIC polarity */ -#define uic1tr (UIC_DCR_BASE1+0x5) /* UIC triggering */ -#define uic1msr (UIC_DCR_BASE1+0x6) /* UIC masked status */ -#define uic1vr (UIC_DCR_BASE1+0x7) /* UIC vector */ -#define uic1vcr (UIC_DCR_BASE1+0x8) /* UIC vector configuration*/ - -#define UIC_DCR_BASE2 0xe0 -#define UIC2_DCR_BASE 0xe0 -#define uic2sr (UIC_DCR_BASE2+0x0) /* UIC status */ -#define uic2srs (UIC_DCR_BASE2+0x1) /* UIC status set */ -#define uic2er (UIC_DCR_BASE2+0x2) /* UIC enable */ -#define uic2cr (UIC_DCR_BASE2+0x3) /* UIC critical */ -#define uic2pr (UIC_DCR_BASE2+0x4) /* UIC polarity */ -#define uic2tr (UIC_DCR_BASE2+0x5) /* UIC triggering */ -#define uic2msr (UIC_DCR_BASE2+0x6) /* UIC masked status */ -#define uic2vr (UIC_DCR_BASE2+0x7) /* UIC vector */ -#define uic2vcr (UIC_DCR_BASE2+0x8) /* UIC vector configuration*/ -#endif - -/*-----------------------------------------------------------------------------+ -| Universal interrupt controller interrupts -+-----------------------------------------------------------------------------*/ -#if defined(CONFIG_405EZ) -#define UIC_DMA0 0x80000000 /* DMA chan. 0 */ -#define UIC_DMA1 0x40000000 /* DMA chan. 1 */ -#define UIC_DMA2 0x20000000 /* DMA chan. 2 */ -#define UIC_DMA3 0x10000000 /* DMA chan. 3 */ -#define UIC_1588 0x08000000 /* IEEE 1588 network synchronization */ -#define UIC_UART0 0x04000000 /* UART 0 */ -#define UIC_UART1 0x02000000 /* UART 1 */ -#define UIC_CAN0 0x01000000 /* CAN 0 */ -#define UIC_CAN1 0x00800000 /* CAN 1 */ -#define UIC_SPI 0x00400000 /* SPI */ -#define UIC_IIC 0x00200000 /* IIC */ -#define UIC_CHT0 0x00100000 /* Chameleon timer high pri interrupt */ -#define UIC_CHT1 0x00080000 /* Chameleon timer high pri interrupt */ -#define UIC_USBH1 0x00040000 /* USB Host 1 */ -#define UIC_USBH2 0x00020000 /* USB Host 2 */ -#define UIC_USBDEV 0x00010000 /* USB Device */ -#define UIC_ENET 0x00008000 /* Ethernet interrupt status */ -#define UIC_ENET1 0x00008000 /* dummy define */ -#define UIC_EMAC_WAKE 0x00004000 /* EMAC wake up */ - -#define UIC_MADMAL 0x00002000 /* Logical OR of following MadMAL int */ -#define UIC_MAL_SERR 0x00002000 /* MAL SERR */ -#define UIC_MAL_TXDE 0x00002000 /* MAL TXDE */ -#define UIC_MAL_RXDE 0x00002000 /* MAL RXDE */ - -#define UIC_MAL_TXEOB 0x00001000 /* MAL TXEOB */ -#define UIC_MAL_TXEOB1 0x00000800 /* MAL TXEOB1 */ -#define UIC_MAL_RXEOB 0x00000400 /* MAL RXEOB */ -#define UIC_NAND 0x00000200 /* NAND Flash controller */ -#define UIC_ADC 0x00000100 /* ADC */ -#define UIC_DAC 0x00000080 /* DAC */ -#define UIC_OPB2PLB 0x00000040 /* OPB to PLB bridge interrupt */ -#define UIC_RESERVED0 0x00000020 /* Reserved */ -#define UIC_EXT0 0x00000010 /* External interrupt 0 */ -#define UIC_EXT1 0x00000008 /* External interrupt 1 */ -#define UIC_EXT2 0x00000004 /* External interrupt 2 */ -#define UIC_EXT3 0x00000002 /* External interrupt 3 */ -#define UIC_EXT4 0x00000001 /* External interrupt 4 */ - -#elif defined(CONFIG_405EX) - -/* UIC 0 */ -#define UIC_U0 0x80000000 /* */ -#define UIC_U1 0x40000000 /* */ -#define UIC_IIC0 0x20000000 /* */ -#define UIC_PKA 0x10000000 /* */ -#define UIC_TRNG 0x08000000 /* */ -#define UIC_EBM 0x04000000 /* */ -#define UIC_BGI 0x02000000 /* */ -#define UIC_IIC1 0x01000000 /* */ -#define UIC_SPI 0x00800000 /* */ -#define UIC_EIRQ0 0x00400000 /**/ -#define UIC_MTE 0x00200000 /*MAL Tx EOB */ -#define UIC_MRE 0x00100000 /*MAL Rx EOB */ -#define UIC_DMA0 0x00080000 /* */ -#define UIC_DMA1 0x00040000 /* */ -#define UIC_DMA2 0x00020000 /* */ -#define UIC_DMA3 0x00010000 /* */ -#define UIC_PCIE0AL 0x00008000 /* */ -#define UIC_PCIE0VPD 0x00004000 /* */ -#define UIC_RPCIE0HRST 0x00002000 /* */ -#define UIC_FPCIE0HRST 0x00001000 /* */ -#define UIC_PCIE0TCR 0x00000800 /* */ -#define UIC_PCIEMSI0 0x00000400 /* */ -#define UIC_PCIEMSI1 0x00000200 /* */ -#define UIC_SECURITY 0x00000100 /* */ -#define UIC_ENET 0x00000080 /* */ -#define UIC_ENET1 0x00000040 /* */ -#define UIC_PCIEMSI2 0x00000020 /* */ -#define UIC_EIRQ4 0x00000010 /**/ -#define UICB0_UIC2NCI 0x00000008 /* */ -#define UICB0_UIC2CI 0x00000004 /* */ -#define UICB0_UIC1NCI 0x00000002 /* */ -#define UICB0_UIC1CI 0x00000001 /* */ - -#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | \ - UICB0_UIC1CI | UICB0_UIC2NCI) - -#define UIC_MAL_TXEOB UIC_MTE/* MAL TXEOB */ -#define UIC_MAL_RXEOB UIC_MRE/* MAL RXEOB */ -/* UIC 1 */ -#define UIC_MS 0x80000000 /* MAL SERR */ -#define UIC_MTDE 0x40000000 /* MAL TXDE */ -#define UIC_MRDE 0x20000000 /* MAL RXDE */ -#define UIC_PCIE0BMVC0 0x10000000 /* */ -#define UIC_PCIE0DCRERR 0x08000000 /* */ -#define UIC_EBC 0x04000000 /* */ -#define UIC_NDFC 0x02000000 /* */ -#define UIC_PCEI1DCRERR 0x01000000 /* */ -#define UIC_GPTCMPT8 0x00800000 /* */ -#define UIC_GPTCMPT9 0x00400000 /* */ -#define UIC_PCIE1AL 0x00200000 /* */ -#define UIC_PCIE1VPD 0x00100000 /* */ -#define UIC_RPCE1HRST 0x00080000 /* */ -#define UIC_FPCE1HRST 0x00040000 /* */ -#define UIC_PCIE1TCR 0x00020000 /* */ -#define UIC_PCIE1VC0 0x00010000 /* */ -#define UIC_GPTCMPT3 0x00008000 /* */ -#define UIC_GPTCMPT4 0x00004000 /* */ -#define UIC_EIRQ7 0x00002000 /* */ -#define UIC_EIRQ8 0x00001000 /* */ -#define UIC_EIRQ9 0x00000800 /* */ -#define UIC_GPTCMP5 0x00000400 /* */ -#define UIC_GPTCMP6 0x00000200 /* */ -#define UIC_GPTCMP7 0x00000100 /* */ -#define UIC_SROM 0x00000080 /* SERIAL ROM*/ -#define UIC_GPTDECPULS 0x00000040 /* GPT Decrement pulse*/ -#define UIC_EIRQ2 0x00000020 /* */ -#define UIC_EIRQ5 0x00000010 /* */ -#define UIC_EIRQ6 0x00000008 /* */ -#define UIC_EMAC0WAKE 0x00000004 /* */ -#define UIC_EIRQ1 0x00000002 /* */ -#define UIC_EMAC1WAKE 0x00000001 /* */ -#define UIC_MAL_SERR UIC_MS /* MAL SERR */ -#define UIC_MAL_TXDE UIC_MTDE /* MAL TXDE */ -#define UIC_MAL_RXDE UIC_MRDE /* MAL RXDE */ -/* UIC 2 */ -#define UIC_PCIE0INTA 0x80000000 /* PCIE0 INTA*/ -#define UIC_PCIE0INTB 0x40000000 /* PCIE0 INTB*/ -#define UIC_PCIE0INTC 0x20000000 /* PCIE0 INTC*/ -#define UIC_PCIE0INTD 0x10000000 /* PCIE0 INTD*/ -#define UIC_EIRQ3 0x08000000 /* External IRQ 3*/ -#define UIC_DDRMCUE 0x04000000 /* */ -#define UIC_DDRMCCE 0x02000000 /* */ -#define UIC_MALINTCOATX0 0x01000000 /* Interrupt coalecence TX0*/ -#define UIC_MALINTCOATX1 0x00800000 /* Interrupt coalecence TX1*/ -#define UIC_MALINTCOARX0 0x00400000 /* Interrupt coalecence RX0*/ -#define UIC_MALINTCOARX1 0x00200000 /* Interrupt coalecence RX1*/ -#define UIC_PCIE1INTA 0x00100000 /* PCIE0 INTA*/ -#define UIC_PCIE1INTB 0x00080000 /* PCIE0 INTB*/ -#define UIC_PCIE1INTC 0x00040000 /* PCIE0 INTC*/ -#define UIC_PCIE1INTD 0x00020000 /* PCIE0 INTD*/ -#define UIC_RPCIEMSI2 0x00010000 /* MSI level 2 Note this looks same as uic0-26*/ -#define UIC_PCIEMSI3 0x00008000 /* MSI level 2*/ -#define UIC_PCIEMSI4 0x00004000 /* MSI level 2*/ -#define UIC_PCIEMSI5 0x00002000 /* MSI level 2*/ -#define UIC_PCIEMSI6 0x00001000 /* MSI level 2*/ -#define UIC_PCIEMSI7 0x00000800 /* MSI level 2*/ -#define UIC_PCIEMSI8 0x00000400 /* MSI level 2*/ -#define UIC_PCIEMSI9 0x00000200 /* MSI level 2*/ -#define UIC_PCIEMSI10 0x00000100 /* MSI level 2*/ -#define UIC_PCIEMSI11 0x00000080 /* MSI level 2*/ -#define UIC_PCIEMSI12 0x00000040 /* MSI level 2*/ -#define UIC_PCIEMSI13 0x00000020 /* MSI level 2*/ -#define UIC_PCIEMSI14 0x00000010 /* MSI level 2*/ -#define UIC_PCIEMSI15 0x00000008 /* MSI level 2*/ -#define UIC_PLB4XAHB 0x00000004 /* PLBxAHB bridge*/ -#define UIC_USBWAKE 0x00000002 /* USB wakup*/ -#define UIC_USBOTG 0x00000001 /* USB OTG*/ -#define UIC_ETH0 UIC_ENET -#define UIC_ETH1 UIC_ENET1 - -#else /* !defined(CONFIG_405EZ) */ - -#define UIC_UART0 0x80000000 /* UART 0 */ -#define UIC_UART1 0x40000000 /* UART 1 */ -#define UIC_IIC 0x20000000 /* IIC */ -#define UIC_EXT_MAST 0x10000000 /* External Master */ -#define UIC_PCI 0x08000000 /* PCI write to command reg */ -#define UIC_DMA0 0x04000000 /* DMA chan. 0 */ -#define UIC_DMA1 0x02000000 /* DMA chan. 1 */ -#define UIC_DMA2 0x01000000 /* DMA chan. 2 */ -#define UIC_DMA3 0x00800000 /* DMA chan. 3 */ -#define UIC_EMAC_WAKE 0x00400000 /* EMAC wake up */ -#define UIC_MAL_SERR 0x00200000 /* MAL SERR */ -#define UIC_MAL_TXEOB 0x00100000 /* MAL TXEOB */ -#define UIC_MAL_RXEOB 0x00080000 /* MAL RXEOB */ -#define UIC_MAL_TXDE 0x00040000 /* MAL TXDE */ -#define UIC_MAL_RXDE 0x00020000 /* MAL RXDE */ -#define UIC_ENET 0x00010000 /* Ethernet0 */ -#define UIC_ENET1 0x00004000 /* Ethernet1 on 405EP */ -#define UIC_ECC_CE 0x00004000 /* ECC Correctable Error on 405GP */ -#define UIC_EXT_PCI_SERR 0x00008000 /* External PCI SERR# */ -#define UIC_PCI_PM 0x00002000 /* PCI Power Management */ -#define UIC_EXT0 0x00000040 /* External interrupt 0 */ -#define UIC_EXT1 0x00000020 /* External interrupt 1 */ -#define UIC_EXT2 0x00000010 /* External interrupt 2 */ -#define UIC_EXT3 0x00000008 /* External interrupt 3 */ -#define UIC_EXT4 0x00000004 /* External interrupt 4 */ -#define UIC_EXT5 0x00000002 /* External interrupt 5 */ -#define UIC_EXT6 0x00000001 /* External interrupt 6 */ -#endif /* defined(CONFIG_405EZ) */ - -/****************************************************************************** - * External Bus Controller (EBC) - *****************************************************************************/ - -/* Bank Configuration Register */ -#define EBC_BXCR_BAS_MASK PPC_REG_VAL(11, 0xFFF) -#define EBC_BXCR_BAS_ENCODE(n) (((static_cast(unsigned long, n)) & \ - EBC_BXCR_BAS_MASK) << 0) -#define EBC_BXCR_BS_MASK PPC_REG_VAL(14, 0x7) -#define EBC_BXCR_BS_1MB PPC_REG_VAL(14, 0x0) -#define EBC_BXCR_BS_2MB PPC_REG_VAL(14, 0x1) -#define EBC_BXCR_BS_4MB PPC_REG_VAL(14, 0x2) -#define EBC_BXCR_BS_8MB PPC_REG_VAL(14, 0x3) -#define EBC_BXCR_BS_16MB PPC_REG_VAL(14, 0x4) -#define EBC_BXCR_BS_32MB PPC_REG_VAL(14, 0x5) -#define EBC_BXCR_BS_64MB PPC_REG_VAL(14, 0x6) -#define EBC_BXCR_BS_128MB PPC_REG_VAL(14, 0x7) -#define EBC_BXCR_BU_MASK PPC_REG_VAL(16, 0x3) -#define EBC_BXCR_BU_NONE PPC_REG_VAL(16, 0x0) -#define EBC_BXCR_BU_R PPC_REG_VAL(16, 0x1) -#define EBC_BXCR_BU_W PPC_REG_VAL(16, 0x2) -#define EBC_BXCR_BU_RW PPC_REG_VAL(16, 0x3) -#define EBC_BXCR_BW_MASK PPC_REG_VAL(18, 0x3) -#define EBC_BXCR_BW_8BIT PPC_REG_VAL(18, 0x0) -#define EBC_BXCR_BW_16BIT PPC_REG_VAL(18, 0x1) -#define EBC_BXCR_BW_32BIT PPC_REG_VAL(18, 0x3) - -/* Bank Access Parameter Register */ -#define EBC_BXAP_BME_ENABLED PPC_REG_VAL(0, 0x1) -#define EBC_BXAP_BME_DISABLED PPC_REG_VAL(0, 0x0) -#define EBC_BXAP_TWT_ENCODE(n) PPC_REG_VAL(8, \ - (static_cast(unsigned long, n)) \ - & 0xFF) -#define EBC_BXAP_FWT_ENCODE(n) PPC_REG_VAL(5, \ - (static_cast(unsigned long, n)) \ - & 0x1F) -#define EBC_BXAP_BWT_ENCODE(n) PPC_REG_VAL(8, \ - (static_cast(unsigned long, n)) \ - & 0x7) -#define EBC_BXAP_BCE_DISABLE PPC_REG_VAL(9, 0x0) -#define EBC_BXAP_BCE_ENABLE PPC_REG_VAL(9, 0x1) -#define EBC_BXAP_BCT_MASK PPC_REG_VAL(11, 0x3) -#define EBC_BXAP_BCT_2TRANS PPC_REG_VAL(11, 0x0) -#define EBC_BXAP_BCT_4TRANS PPC_REG_VAL(11, 0x1) -#define EBC_BXAP_BCT_8TRANS PPC_REG_VAL(11, 0x2) -#define EBC_BXAP_BCT_16TRANS PPC_REG_VAL(11, 0x3) -#define EBC_BXAP_CSN_ENCODE(n) PPC_REG_VAL(13, \ - (static_cast(unsigned long, n)) \ - & 0x3) -#define EBC_BXAP_OEN_ENCODE(n) PPC_REG_VAL(15, \ - (static_cast(unsigned long, n)) \ - & 0x3) -#define EBC_BXAP_WBN_ENCODE(n) PPC_REG_VAL(17, \ - (static_cast(unsigned long, n)) \ - & 0x3) -#define EBC_BXAP_WBF_ENCODE(n) PPC_REG_VAL(19, \ - (static_cast(unsigned long, n)) \ - & 0x3) -#define EBC_BXAP_TH_ENCODE(n) PPC_REG_VAL(22, \ - (static_cast(unsigned long, n)) \ - & 0x7) -#define EBC_BXAP_RE_ENABLED PPC_REG_VAL(23, 0x1) -#define EBC_BXAP_RE_DISABLED PPC_REG_VAL(23, 0x0) -#define EBC_BXAP_SOR_DELAYED PPC_REG_VAL(24, 0x0) -#define EBC_BXAP_SOR_NONDELAYED PPC_REG_VAL(24, 0x1) -#define EBC_BXAP_BEM_WRITEONLY PPC_REG_VAL(25, 0x0) -#define EBC_BXAP_BEM_RW PPC_REG_VAL(25, 0x1) -#define EBC_BXAP_PEN_DISABLED PPC_REG_VAL(26, 0x0) -#define EBC_BXAP_PEN_ENABLED PPC_REG_VAL(26, 0x1) - -/* Configuration Register */ -#define EBC_CFG_LE_MASK PPC_REG_VAL(0, 0x1) -#define EBC_CFG_LE_UNLOCK PPC_REG_VAL(0, 0x0) -#define EBC_CFG_LE_LOCK PPC_REG_VAL(0, 0x1) -#define EBC_CFG_PTD_MASK PPC_REG_VAL(1, 0x1) -#define EBC_CFG_PTD_ENABLE PPC_REG_VAL(1, 0x0) -#define EBC_CFG_PTD_DISABLE PPC_REG_VAL(1, 0x1) -#define EBC_CFG_RTC_MASK PPC_REG_VAL(4, 0x7) -#define EBC_CFG_RTC_16PERCLK PPC_REG_VAL(4, 0x0) -#define EBC_CFG_RTC_32PERCLK PPC_REG_VAL(4, 0x1) -#define EBC_CFG_RTC_64PERCLK PPC_REG_VAL(4, 0x2) -#define EBC_CFG_RTC_128PERCLK PPC_REG_VAL(4, 0x3) -#define EBC_CFG_RTC_256PERCLK PPC_REG_VAL(4, 0x4) -#define EBC_CFG_RTC_512PERCLK PPC_REG_VAL(4, 0x5) -#define EBC_CFG_RTC_1024PERCLK PPC_REG_VAL(4, 0x6) -#define EBC_CFG_RTC_2048PERCLK PPC_REG_VAL(4, 0x7) -#define EBC_CFG_ATC_MASK PPC_REG_VAL(5, 0x1) -#define EBC_CFG_ATC_HI PPC_REG_VAL(5, 0x0) -#define EBC_CFG_ATC_PREVIOUS PPC_REG_VAL(5, 0x1) -#define EBC_CFG_DTC_MASK PPC_REG_VAL(6, 0x1) -#define EBC_CFG_DTC_HI PPC_REG_VAL(6, 0x0) -#define EBC_CFG_DTC_PREVIOUS PPC_REG_VAL(6, 0x1) -#define EBC_CFG_CTC_MASK PPC_REG_VAL(7, 0x1) -#define EBC_CFG_CTC_HI PPC_REG_VAL(7, 0x0) -#define EBC_CFG_CTC_PREVIOUS PPC_REG_VAL(7, 0x1) -#define EBC_CFG_OEO_MASK PPC_REG_VAL(8, 0x1) -#define EBC_CFG_OEO_DISABLE PPC_REG_VAL(8, 0x0) -#define EBC_CFG_OEO_ENABLE PPC_REG_VAL(8, 0x1) -#define EBC_CFG_EMC_MASK PPC_REG_VAL(9, 0x1) -#define EBC_CFG_EMC_NONDEFAULT PPC_REG_VAL(9, 0x0) -#define EBC_CFG_EMC_DEFAULT PPC_REG_VAL(9, 0x1) -#define EBC_CFG_PME_MASK PPC_REG_VAL(14, 0x1) -#define EBC_CFG_PME_DISABLE PPC_REG_VAL(14, 0x0) -#define EBC_CFG_PME_ENABLE PPC_REG_VAL(14, 0x1) -#define EBC_CFG_PMT_MASK PPC_REG_VAL(19, 0x1F) -#define EBC_CFG_PMT_ENCODE(n) PPC_REG_VAL(19, \ - (static_cast(unsigned long, n)) \ - & 0x1F) -#define EBC_CFG_PR_MASK PPC_REG_VAL(21, 0x3) -#define EBC_CFG_PR_16 PPC_REG_VAL(21, 0x0) -#define EBC_CFG_PR_32 PPC_REG_VAL(21, 0x1) -#define EBC_CFG_PR_64 PPC_REG_VAL(21, 0x2) -#define EBC_CFG_PR_128 PPC_REG_VAL(21, 0x3) - #ifndef CONFIG_405EP /****************************************************************************** * Decompression Controller @@ -1254,6 +893,42 @@ #if defined(CONFIG_405EX) #define SDR0_SRST 0x0200 +/* + * Software Reset Register + */ +#define SDR0_SRST_BGO PPC_REG_VAL(0, 1) +#define SDR0_SRST_PLB4 PPC_REG_VAL(1, 1) +#define SDR0_SRST_EBC PPC_REG_VAL(2, 1) +#define SDR0_SRST_OPB PPC_REG_VAL(3, 1) +#define SDR0_SRST_UART0 PPC_REG_VAL(4, 1) +#define SDR0_SRST_UART1 PPC_REG_VAL(5, 1) +#define SDR0_SRST_IIC0 PPC_REG_VAL(6, 1) +#define SDR0_SRST_BGI PPC_REG_VAL(7, 1) +#define SDR0_SRST_GPIO PPC_REG_VAL(8, 1) +#define SDR0_SRST_GPT PPC_REG_VAL(9, 1) +#define SDR0_SRST_DMC PPC_REG_VAL(10, 1) +#define SDR0_SRST_RGMII PPC_REG_VAL(11, 1) +#define SDR0_SRST_EMAC0 PPC_REG_VAL(12, 1) +#define SDR0_SRST_EMAC1 PPC_REG_VAL(13, 1) +#define SDR0_SRST_CPM PPC_REG_VAL(14, 1) +#define SDR0_SRST_EPLL PPC_REG_VAL(15, 1) +#define SDR0_SRST_UIC PPC_REG_VAL(16, 1) +#define SDR0_SRST_UPRST PPC_REG_VAL(17, 1) +#define SDR0_SRST_IIC1 PPC_REG_VAL(18, 1) +#define SDR0_SRST_SCP PPC_REG_VAL(19, 1) +#define SDR0_SRST_UHRST PPC_REG_VAL(20, 1) +#define SDR0_SRST_DMA PPC_REG_VAL(21, 1) +#define SDR0_SRST_DMAC PPC_REG_VAL(22, 1) +#define SDR0_SRST_MAL PPC_REG_VAL(23, 1) +#define SDR0_SRST_EBM PPC_REG_VAL(24, 1) +#define SDR0_SRST_GPTR PPC_REG_VAL(25, 1) +#define SDR0_SRST_PE0 PPC_REG_VAL(26, 1) +#define SDR0_SRST_PE1 PPC_REG_VAL(27, 1) +#define SDR0_SRST_CRYP PPC_REG_VAL(28, 1) +#define SDR0_SRST_PKP PPC_REG_VAL(29, 1) +#define SDR0_SRST_AHB PPC_REG_VAL(30, 1) +#define SDR0_SRST_NDFC PPC_REG_VAL(31, 1) + #define sdr_uart0 0x0120 /* UART0 Config */ #define sdr_uart1 0x0121 /* UART1 Config */ #define sdr_mfr 0x4300 /* SDR0_MFR reg */ diff --git a/include/ppc440.h b/include/ppc440.h index c581f1b..92db15f 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -77,7 +77,6 @@ #define tbl 0x11c /* time base lower (supervisor)*/ #define tbu 0x11d /* time base upper (supervisor)*/ #define pir 0x11e /* processor id register */ -/*#define pvr 0x11f processor version register */ #define dbsr 0x130 /* debug status register */ #define dbcr0 0x134 /* debug control register 0 */ #define dbcr1 0x135 /* debug control register 1 */ @@ -268,86 +267,6 @@ #define sdr_sdstp6 0x4005 #define sdr_sdstp7 0x4007 -/****************************************************************************** - * PCI express defines - ******************************************************************************/ -#define SDR0_PE0UTLSET1 0x00000300 /* PE0 Upper transaction layer conf setting */ -#define SDR0_PE0UTLSET2 0x00000301 /* PE0 Upper transaction layer conf setting 2 */ -#define SDR0_PE0DLPSET 0x00000302 /* PE0 Data link & logical physical configuration */ -#define SDR0_PE0LOOP 0x00000303 /* PE0 Loopback interface status */ -#define SDR0_PE0RCSSET 0x00000304 /* PE0 Reset, clock & shutdown setting */ -#define SDR0_PE0RCSSTS 0x00000305 /* PE0 Reset, clock & shutdown status */ -#define SDR0_PE0HSSSET1L0 0x00000306 /* PE0 HSS Control Setting 1: Lane 0 */ -#define SDR0_PE0HSSSET2L0 0x00000307 /* PE0 HSS Control Setting 2: Lane 0 */ -#define SDR0_PE0HSSSTSL0 0x00000308 /* PE0 HSS Control Status : Lane 0 */ -#define SDR0_PE0HSSSET1L1 0x00000309 /* PE0 HSS Control Setting 1: Lane 1 */ -#define SDR0_PE0HSSSET2L1 0x0000030A /* PE0 HSS Control Setting 2: Lane 1 */ -#define SDR0_PE0HSSSTSL1 0x0000030B /* PE0 HSS Control Status : Lane 1 */ -#define SDR0_PE0HSSSET1L2 0x0000030C /* PE0 HSS Control Setting 1: Lane 2 */ -#define SDR0_PE0HSSSET2L2 0x0000030D /* PE0 HSS Control Setting 2: Lane 2 */ -#define SDR0_PE0HSSSTSL2 0x0000030E /* PE0 HSS Control Status : Lane 2 */ -#define SDR0_PE0HSSSET1L3 0x0000030F /* PE0 HSS Control Setting 1: Lane 3 */ -#define SDR0_PE0HSSSET2L3 0x00000310 /* PE0 HSS Control Setting 2: Lane 3 */ -#define SDR0_PE0HSSSTSL3 0x00000311 /* PE0 HSS Control Status : Lane 3 */ -#define SDR0_PE0HSSSET1L4 0x00000312 /* PE0 HSS Control Setting 1: Lane 4 */ -#define SDR0_PE0HSSSET2L4 0x00000313 /* PE0 HSS Control Setting 2: Lane 4 */ -#define SDR0_PE0HSSSTSL4 0x00000314 /* PE0 HSS Control Status : Lane 4 */ -#define SDR0_PE0HSSSET1L5 0x00000315 /* PE0 HSS Control Setting 1: Lane 5 */ -#define SDR0_PE0HSSSET2L5 0x00000316 /* PE0 HSS Control Setting 2: Lane 5 */ -#define SDR0_PE0HSSSTSL5 0x00000317 /* PE0 HSS Control Status : Lane 5 */ -#define SDR0_PE0HSSSET1L6 0x00000318 /* PE0 HSS Control Setting 1: Lane 6 */ -#define SDR0_PE0HSSSET2L6 0x00000319 /* PE0 HSS Control Setting 2: Lane 6 */ -#define SDR0_PE0HSSSTSL6 0x0000031A /* PE0 HSS Control Status : Lane 6 */ -#define SDR0_PE0HSSSET1L7 0x0000031B /* PE0 HSS Control Setting 1: Lane 7 */ -#define SDR0_PE0HSSSET2L7 0x0000031C /* PE0 HSS Control Setting 2: Lane 7 */ -#define SDR0_PE0HSSSTSL7 0x0000031D /* PE0 HSS Control Status : Lane 7 */ -#define SDR0_PE0HSSSEREN 0x0000031E /* PE0 Serdes Transmitter Enable */ -#define SDR0_PE0LANEABCD 0x0000031F /* PE0 Lanes ABCD affectation */ -#define SDR0_PE0LANEEFGH 0x00000320 /* PE0 Lanes EFGH affectation */ - -#define SDR0_PE1UTLSET1 0x00000340 /* PE1 Upper transaction layer conf setting */ -#define SDR0_PE1UTLSET2 0x00000341 /* PE1 Upper transaction layer conf setting 2 */ -#define SDR0_PE1DLPSET 0x00000342 /* PE1 Data link & logical physical configuration */ -#define SDR0_PE1LOOP 0x00000343 /* PE1 Loopback interface status */ -#define SDR0_PE1RCSSET 0x00000344 /* PE1 Reset, clock & shutdown setting */ -#define SDR0_PE1RCSSTS 0x00000345 /* PE1 Reset, clock & shutdown status */ -#define SDR0_PE1HSSSET1L0 0x00000346 /* PE1 HSS Control Setting 1: Lane 0 */ -#define SDR0_PE1HSSSET2L0 0x00000347 /* PE1 HSS Control Setting 2: Lane 0 */ -#define SDR0_PE1HSSSTSL0 0x00000348 /* PE1 HSS Control Status : Lane 0 */ -#define SDR0_PE1HSSSET1L1 0x00000349 /* PE1 HSS Control Setting 1: Lane 1 */ -#define SDR0_PE1HSSSET2L1 0x0000034A /* PE1 HSS Control Setting 2: Lane 1 */ -#define SDR0_PE1HSSSTSL1 0x0000034B /* PE1 HSS Control Status : Lane 1 */ -#define SDR0_PE1HSSSET1L2 0x0000034C /* PE1 HSS Control Setting 1: Lane 2 */ -#define SDR0_PE1HSSSET2L2 0x0000034D /* PE1 HSS Control Setting 2: Lane 2 */ -#define SDR0_PE1HSSSTSL2 0x0000034E /* PE1 HSS Control Status : Lane 2 */ -#define SDR0_PE1HSSSET1L3 0x0000034F /* PE1 HSS Control Setting 1: Lane 3 */ -#define SDR0_PE1HSSSET2L3 0x00000350 /* PE1 HSS Control Setting 2: Lane 3 */ -#define SDR0_PE1HSSSTSL3 0x00000351 /* PE1 HSS Control Status : Lane 3 */ -#define SDR0_PE1HSSSEREN 0x00000352 /* PE1 Serdes Transmitter Enable */ -#define SDR0_PE1LANEABCD 0x00000353 /* PE1 Lanes ABCD affectation */ -#define SDR0_PE2UTLSET1 0x00000370 /* PE2 Upper transaction layer conf setting */ -#define SDR0_PE2UTLSET2 0x00000371 /* PE2 Upper transaction layer conf setting 2 */ -#define SDR0_PE2DLPSET 0x00000372 /* PE2 Data link & logical physical configuration */ -#define SDR0_PE2LOOP 0x00000373 /* PE2 Loopback interface status */ -#define SDR0_PE2RCSSET 0x00000374 /* PE2 Reset, clock & shutdown setting */ -#define SDR0_PE2RCSSTS 0x00000375 /* PE2 Reset, clock & shutdown status */ -#define SDR0_PE2HSSSET1L0 0x00000376 /* PE2 HSS Control Setting 1: Lane 0 */ -#define SDR0_PE2HSSSET2L0 0x00000377 /* PE2 HSS Control Setting 2: Lane 0 */ -#define SDR0_PE2HSSSTSL0 0x00000378 /* PE2 HSS Control Status : Lane 0 */ -#define SDR0_PE2HSSSET1L1 0x00000379 /* PE2 HSS Control Setting 1: Lane 1 */ -#define SDR0_PE2HSSSET2L1 0x0000037A /* PE2 HSS Control Setting 2: Lane 1 */ -#define SDR0_PE2HSSSTSL1 0x0000037B /* PE2 HSS Control Status : Lane 1 */ -#define SDR0_PE2HSSSET1L2 0x0000037C /* PE2 HSS Control Setting 1: Lane 2 */ -#define SDR0_PE2HSSSET2L2 0x0000037D /* PE2 HSS Control Setting 2: Lane 2 */ -#define SDR0_PE2HSSSTSL2 0x0000037E /* PE2 HSS Control Status : Lane 2 */ -#define SDR0_PE2HSSSET1L3 0x0000037F /* PE2 HSS Control Setting 1: Lane 3 */ -#define SDR0_PE2HSSSET2L3 0x00000380 /* PE2 HSS Control Setting 2: Lane 3 */ -#define SDR0_PE2HSSSTSL3 0x00000381 /* PE2 HSS Control Status : Lane 3 */ -#define SDR0_PE2HSSSEREN 0x00000382 /* PE2 Serdes Transmitter Enable */ -#define SDR0_PE2LANEABCD 0x00000383 /* PE2 Lanes ABCD affectation */ -#define SDR0_PEGPLLSET1 0x000003A0 /* PE Pll LC Tank Setting1 */ -#define SDR0_PEGPLLSET2 0x000003A1 /* PE Pll LC Tank Setting2 */ -#define SDR0_PEGPLLSTS 0x000003A2 /* PE Pll LC Tank Status */ #endif /* CONFIG_440SPE */ /*----------------------------------------------------------------------------- @@ -749,7 +668,8 @@ +----------------------------------------------------------------------------*/ #if defined (CONFIG_440GX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) #define L2_CACHE_BASE 0x030 #define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */ #define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */ @@ -837,7 +757,8 @@ /*----------------------------------------------------------------------------- | Clocking, Power Management and Chip Control +----------------------------------------------------------------------------*/ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) #define CNTRL_DCR_BASE 0x160 #else #define CNTRL_DCR_BASE 0x0b0 @@ -863,193 +784,6 @@ #define cntrl1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */ /*----------------------------------------------------------------------------- - | Universal interrupt controller - +----------------------------------------------------------------------------*/ -#define UIC_SR 0x0 /* UIC status */ -#define UIC_ER 0x2 /* UIC enable */ -#define UIC_CR 0x3 /* UIC critical */ -#define UIC_PR 0x4 /* UIC polarity */ -#define UIC_TR 0x5 /* UIC triggering */ -#define UIC_MSR 0x6 /* UIC masked status */ -#define UIC_VR 0x7 /* UIC vector */ -#define UIC_VCR 0x8 /* UIC vector configuration */ - -#define UIC0_DCR_BASE 0xc0 -#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */ -#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */ -#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */ -#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */ -#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */ -#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */ -#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */ -#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */ - -#define UIC1_DCR_BASE 0xd0 -#define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */ -#define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */ -#define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */ -#define uic1pr (UIC1_DCR_BASE+0x4) /* UIC1 polarity */ -#define uic1tr (UIC1_DCR_BASE+0x5) /* UIC1 triggering */ -#define uic1msr (UIC1_DCR_BASE+0x6) /* UIC1 masked status */ -#define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */ -#define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */ - -#if defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define UIC2_DCR_BASE 0xe0 -#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */ -#define uic2srs (UIC2_DCR_BASE+0x1) /* UIC2 status-Read Set */ -#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */ -#define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */ -#define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */ -#define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */ -#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */ -#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */ -#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */ - -#define UIC3_DCR_BASE 0xf0 -#define uic3sr (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */ -#define uic3srs (UIC3_DCR_BASE+0x1) /* UIC3 status-Read Set */ -#define uic3er (UIC3_DCR_BASE+0x2) /* UIC3 enable */ -#define uic3cr (UIC3_DCR_BASE+0x3) /* UIC3 critical */ -#define uic3pr (UIC3_DCR_BASE+0x4) /* UIC3 polarity */ -#define uic3tr (UIC3_DCR_BASE+0x5) /* UIC3 triggering */ -#define uic3msr (UIC3_DCR_BASE+0x6) /* UIC3 masked status */ -#define uic3vr (UIC3_DCR_BASE+0x7) /* UIC3 vector */ -#define uic3vcr (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */ -#endif /* CONFIG_440SPE */ - -#if defined(CONFIG_440GX) -#define UIC2_DCR_BASE 0x210 -#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status */ -#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */ -#define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */ -#define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */ -#define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */ -#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */ -#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */ -#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */ - - -#define UIC_DCR_BASE 0x200 -#define uicb0sr (UIC_DCR_BASE+0x0) /* UIC Base Status Register */ -#define uicb0er (UIC_DCR_BASE+0x2) /* UIC Base enable */ -#define uicb0cr (UIC_DCR_BASE+0x3) /* UIC Base critical */ -#define uicb0pr (UIC_DCR_BASE+0x4) /* UIC Base polarity */ -#define uicb0tr (UIC_DCR_BASE+0x5) /* UIC Base triggering */ -#define uicb0msr (UIC_DCR_BASE+0x6) /* UIC Base masked status */ -#define uicb0vr (UIC_DCR_BASE+0x7) /* UIC Base vector */ -#define uicb0vcr (UIC_DCR_BASE+0x8) /* UIC Base vector configuration */ -#endif /* CONFIG_440GX */ - -/* The following is for compatibility with 405 code */ -#define uicsr uic0sr -#define uicer uic0er -#define uiccr uic0cr -#define uicpr uic0pr -#define uictr uic0tr -#define uicmsr uic0msr -#define uicvr uic0vr -#define uicvcr uic0vcr - -#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) -/*----------------------------------------------------------------------------+ -| Clock / Power-on-reset DCR's. -+----------------------------------------------------------------------------*/ -#define CPR0_CLKUPD 0x20 -#define CPR0_CLKUPD_BSY_MASK 0x80000000 -#define CPR0_CLKUPD_BSY_COMPLETED 0x00000000 -#define CPR0_CLKUPD_BSY_BUSY 0x80000000 -#define CPR0_CLKUPD_CUI_MASK 0x80000000 -#define CPR0_CLKUPD_CUI_DISABLE 0x00000000 -#define CPR0_CLKUPD_CUI_ENABLE 0x80000000 -#define CPR0_CLKUPD_CUD_MASK 0x40000000 -#define CPR0_CLKUPD_CUD_DISABLE 0x00000000 -#define CPR0_CLKUPD_CUD_ENABLE 0x40000000 - -#define CPR0_PLLC 0x40 -#define CPR0_PLLC_RST_MASK 0x80000000 -#define CPR0_PLLC_RST_PLLLOCKED 0x00000000 -#define CPR0_PLLC_RST_PLLRESET 0x80000000 -#define CPR0_PLLC_ENG_MASK 0x40000000 -#define CPR0_PLLC_ENG_DISABLE 0x00000000 -#define CPR0_PLLC_ENG_ENABLE 0x40000000 -#define CPR0_PLLC_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) -#define CPR0_PLLC_ENG_DECODE(n) ((((unsigned long)(n))>>30)&0x01) -#define CPR0_PLLC_SRC_MASK 0x20000000 -#define CPR0_PLLC_SRC_PLLOUTA 0x00000000 -#define CPR0_PLLC_SRC_PLLOUTB 0x20000000 -#define CPR0_PLLC_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<29) -#define CPR0_PLLC_SRC_DECODE(n) ((((unsigned long)(n))>>29)&0x01) -#define CPR0_PLLC_SEL_MASK 0x07000000 -#define CPR0_PLLC_SEL_PLLOUT 0x00000000 -#define CPR0_PLLC_SEL_CPU 0x01000000 -#define CPR0_PLLC_SEL_EBC 0x05000000 -#define CPR0_PLLC_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) -#define CPR0_PLLC_SEL_DECODE(n) ((((unsigned long)(n))>>24)&0x07) -#define CPR0_PLLC_TUNE_MASK 0x000003FF -#define CPR0_PLLC_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) -#define CPR0_PLLC_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF) - -#define CPR0_PLLD 0x60 -#define CPR0_PLLD_FBDV_MASK 0x1F000000 -#define CPR0_PLLD_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) -#define CPR0_PLLD_FBDV_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x1F)+1) -#define CPR0_PLLD_FWDVA_MASK 0x000F0000 -#define CPR0_PLLD_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<16) -#define CPR0_PLLD_FWDVA_DECODE(n) ((((((unsigned long)(n))>>16)-1)&0x0F)+1) -#define CPR0_PLLD_FWDVB_MASK 0x00000700 -#define CPR0_PLLD_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<8) -#define CPR0_PLLD_FWDVB_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x07)+1) -#define CPR0_PLLD_LFBDV_MASK 0x0000003F -#define CPR0_PLLD_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0) -#define CPR0_PLLD_LFBDV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1) - -#define CPR0_PRIMAD 0x80 -#define CPR0_PRIMAD_PRADV0_MASK 0x07000000 -#define CPR0_PRIMAD_PRADV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) -#define CPR0_PRIMAD_PRADV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1) - -#define CPR0_PRIMBD 0xA0 -#define CPR0_PRIMBD_PRBDV0_MASK 0x07000000 -#define CPR0_PRIMBD_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) -#define CPR0_PRIMBD_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1) - -#define CPR0_OPBD 0xC0 -#define CPR0_OPBD_OPBDV0_MASK 0x03000000 -#define CPR0_OPBD_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) -#define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) - -#define CPR0_PERD 0xE0 -#if !defined(CONFIG_440EPX) -#define CPR0_PERD_PERDV0_MASK 0x03000000 -#define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) -#define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) -#endif - -#define CPR0_MALD 0x100 -#define CPR0_MALD_MALDV0_MASK 0x03000000 -#define CPR0_MALD_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) -#define CPR0_MALD_MALDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) - -#define CPR0_ICFG 0x140 -#define CPR0_ICFG_RLI_MASK 0x80000000 -#define CPR0_ICFG_RLI_RESETCPR 0x00000000 -#define CPR0_ICFG_RLI_PRESERVECPR 0x80000000 -#define CPR0_ICFG_ICS_MASK 0x00000007 -#define CPR0_ICFG_ICS_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0) -#define CPR0_ICFG_ICS_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1) - -/************************/ -/* IIC defines */ -/************************/ -#define IIC0_MMIO_BASE 0xA0000400 -#define IIC1_MMIO_BASE 0xA0000500 - -#endif /* CONFIG_440SP */ - -/*----------------------------------------------------------------------------- | DMA +----------------------------------------------------------------------------*/ #if defined(CONFIG_460EX) || defined(CONFIG_460GT) @@ -1136,708 +870,6 @@ #define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */ #endif /* CONFIG_440GX */ - -/*---------------------------------------------------------------------------+ -| Universal interrupt controller 0 interrupts (UIC0) -+---------------------------------------------------------------------------*/ -#if defined(CONFIG_440SP) -#define UIC_U0 0x80000000 /* UART 0 */ -#define UIC_U1 0x40000000 /* UART 1 */ -#define UIC_IIC0 0x20000000 /* IIC */ -#define UIC_IIC1 0x10000000 /* IIC */ -#define UIC_PIM 0x08000000 /* PCI0 inbound message */ -#define UIC_PCRW 0x04000000 /* PCI0 command write register */ -#define UIC_PPM 0x02000000 /* PCI0 power management */ -#define UIC_PVPD 0x01000000 /* PCI0 VPD Access */ -#define UIC_MSI0 0x00800000 /* PCI0 MSI level 0 */ -#define UIC_P1IM 0x00400000 /* PCI1 Inbound Message */ -#define UIC_P1CRW 0x00200000 /* PCI1 command write register */ -#define UIC_P1PM 0x00100000 /* PCI1 power management */ -#define UIC_P1VPD 0x00080000 /* PCI1 VPD Access */ -#define UIC_P1MSI0 0x00040000 /* PCI1 MSI level 0 */ -#define UIC_P2IM 0x00020000 /* PCI2 inbound message */ -#define UIC_P2CRW 0x00010000 /* PCI2 command register write */ -#define UIC_P2PM 0x00008000 /* PCI2 power management */ -#define UIC_P2VPD 0x00004000 /* PCI2 VPD access */ -#define UIC_P2MSI0 0x00002000 /* PCI2 MSI level 0 */ -#define UIC_D0CPF 0x00001000 /* DMA0 command pointer */ -#define UIC_D0CSF 0x00000800 /* DMA0 command status */ -#define UIC_D1CPF 0x00000400 /* DMA1 command pointer */ -#define UIC_D1CSF 0x00000200 /* DMA1 command status */ -#define UIC_I2OID 0x00000100 /* I2O inbound doorbell */ -#define UIC_I2OPLF 0x00000080 /* I2O inbound post list */ -#define UIC_I2O0LL 0x00000040 /* I2O0 low latency PLB write */ -#define UIC_I2O1LL 0x00000020 /* I2O1 low latency PLB write */ -#define UIC_I2O0HB 0x00000010 /* I2O0 high bandwidth PLB write */ -#define UIC_I2O1HB 0x00000008 /* I2O1 high bandwidth PLB write */ -#define UIC_GPTCT 0x00000004 /* GPT count timer */ -#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ -#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ -#elif defined(CONFIG_440GX) || defined(CONFIG_440EP) -#define UIC_U0 0x80000000 /* UART 0 */ -#define UIC_U1 0x40000000 /* UART 1 */ -#define UIC_IIC0 0x20000000 /* IIC */ -#define UIC_IIC1 0x10000000 /* IIC */ -#define UIC_PIM 0x08000000 /* PCI inbound message */ -#define UIC_PCRW 0x04000000 /* PCI command register write */ -#define UIC_PPM 0x02000000 /* PCI power management */ -#define UIC_MSI0 0x01000000 /* PCI MSI level 0 */ -#define UIC_MSI1 0x00800000 /* PCI MSI level 1 */ -#define UIC_MSI2 0x00400000 /* PCI MSI level 2 */ -#define UIC_MTE 0x00200000 /* MAL TXEOB */ -#define UIC_MRE 0x00100000 /* MAL RXEOB */ -#define UIC_D0 0x00080000 /* DMA channel 0 */ -#define UIC_D1 0x00040000 /* DMA channel 1 */ -#define UIC_D2 0x00020000 /* DMA channel 2 */ -#define UIC_D3 0x00010000 /* DMA channel 3 */ -#define UIC_RSVD0 0x00008000 /* Reserved */ -#define UIC_RSVD1 0x00004000 /* Reserved */ -#define UIC_CT0 0x00002000 /* GPT compare timer 0 */ -#define UIC_CT1 0x00001000 /* GPT compare timer 1 */ -#define UIC_CT2 0x00000800 /* GPT compare timer 2 */ -#define UIC_CT3 0x00000400 /* GPT compare timer 3 */ -#define UIC_CT4 0x00000200 /* GPT compare timer 4 */ -#define UIC_EIR0 0x00000100 /* External interrupt 0 */ -#define UIC_EIR1 0x00000080 /* External interrupt 1 */ -#define UIC_EIR2 0x00000040 /* External interrupt 2 */ -#define UIC_EIR3 0x00000020 /* External interrupt 3 */ -#define UIC_EIR4 0x00000010 /* External interrupt 4 */ -#define UIC_EIR5 0x00000008 /* External interrupt 5 */ -#define UIC_EIR6 0x00000004 /* External interrupt 6 */ -#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ -#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ - -#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) - -#define UIC_U0 0x80000000 /* UART 0 */ -#define UIC_U1 0x40000000 /* UART 1 */ -#define UIC_IIC0 0x20000000 /* IIC */ -#define UIC_KRD 0x10000000 /* Kasumi Ready for data */ -#define UIC_KDA 0x08000000 /* Kasumi Data Available */ -#define UIC_PCRW 0x04000000 /* PCI command register write */ -#define UIC_PPM 0x02000000 /* PCI power management */ -#define UIC_IIC1 0x01000000 /* IIC */ -#define UIC_SPI 0x00800000 /* SPI */ -#define UIC_EPCISER 0x00400000 /* External PCI SERR */ -#define UIC_MTE 0x00200000 /* MAL TXEOB */ -#define UIC_MRE 0x00100000 /* MAL RXEOB */ -#define UIC_D0 0x00080000 /* DMA channel 0 */ -#define UIC_D1 0x00040000 /* DMA channel 1 */ -#define UIC_D2 0x00020000 /* DMA channel 2 */ -#define UIC_D3 0x00010000 /* DMA channel 3 */ -#define UIC_UD0 0x00008000 /* UDMA irq 0 */ -#define UIC_UD1 0x00004000 /* UDMA irq 1 */ -#define UIC_UD2 0x00002000 /* UDMA irq 2 */ -#define UIC_UD3 0x00001000 /* UDMA irq 3 */ -#define UIC_HSB2D 0x00000800 /* USB2.0 Device */ -#define UIC_OHCI1 0x00000400 /* USB2.0 Host OHCI irq 1 */ -#define UIC_OHCI2 0x00000200 /* USB2.0 Host OHCI irq 2 */ -#define UIC_EIP94 0x00000100 /* Security EIP94 */ -#define UIC_ETH0 0x00000080 /* Emac 0 */ -#define UIC_ETH1 0x00000040 /* Emac 1 */ -#define UIC_EHCI 0x00000020 /* USB2.0 Host EHCI */ -#define UIC_EIR4 0x00000010 /* External interrupt 4 */ -#define UIC_UIC2NC 0x00000008 /* UIC2 non-critical interrupt */ -#define UIC_UIC2C 0x00000004 /* UIC2 critical interrupt */ -#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ -#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ - -/* For compatibility with 405 code */ -#define UIC_MAL_TXEOB UIC_MTE -#define UIC_MAL_RXEOB UIC_MRE - -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) - -#define UIC_RSVD0 0x80000000 /* N/A - unused */ -#define UIC_U1 0x40000000 /* UART 1 */ -#define UIC_IIC0 0x20000000 /* IIC */ -#define UIC_IIC1 0x10000000 /* IIC */ -#define UIC_PIM 0x08000000 /* PCI inbound message */ -#define UIC_PCRW 0x04000000 /* PCI command register write */ -#define UIC_PPM 0x02000000 /* PCI power management */ -#define UIC_PCIVPD 0x01000000 /* PCI VPD */ -#define UIC_MSI0 0x00800000 /* PCI MSI level 0 */ -#define UIC_EIR0 0x00400000 /* External interrupt 0 */ -#define UIC_UIC2NC 0x00200000 /* UIC2 non-critical interrupt */ -#define UIC_UIC2C 0x00100000 /* UIC2 critical interrupt */ -#define UIC_D0 0x00080000 /* DMA channel 0 */ -#define UIC_D1 0x00040000 /* DMA channel 1 */ -#define UIC_D2 0x00020000 /* DMA channel 2 */ -#define UIC_D3 0x00010000 /* DMA channel 3 */ -#define UIC_UIC3NC 0x00008000 /* UIC3 non-critical interrupt */ -#define UIC_UIC3C 0x00004000 /* UIC3 critical interrupt */ -#define UIC_EIR1 0x00002000 /* External interrupt 1 */ -#define UIC_TRNGDA 0x00001000 /* TRNG data available */ -#define UIC_PKAR1 0x00000800 /* PKA ready (PKA[1]) */ -#define UIC_D1CPFF 0x00000400 /* DMA1 cp fifo full */ -#define UIC_D1CSNS 0x00000200 /* DMA1 cs fifo needs service */ -#define UIC_I2OID 0x00000100 /* I2O inbound door bell */ -#define UIC_I2OLNE 0x00000080 /* I2O Inbound Post List FIFO Not Empty */ -#define UIC_I20R0LL 0x00000040 /* I2O Region 0 Low Latency PLB Write */ -#define UIC_I2OR1LL 0x00000020 /* I2O Region 1 Low Latency PLB Write */ -#define UIC_I20R0HB 0x00000010 /* I2O Region 0 High Bandwidth PLB Write */ -#define UIC_I2OR1HB 0x00000008 /* I2O Region 1 High Bandwidth PLB Write */ -#define UIC_EIP94 0x00000004 /* Security EIP94 */ -#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ -#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ - -#elif !defined(CONFIG_440SPE) -#define UIC_U0 0x80000000 /* UART 0 */ -#define UIC_U1 0x40000000 /* UART 1 */ -#define UIC_IIC0 0x20000000 /* IIC */ -#define UIC_IIC1 0x10000000 /* IIC */ -#define UIC_PIM 0x08000000 /* PCI inbound message */ -#define UIC_PCRW 0x04000000 /* PCI command register write */ -#define UIC_PPM 0x02000000 /* PCI power management */ -#define UIC_MSI0 0x01000000 /* PCI MSI level 0 */ -#define UIC_MSI1 0x00800000 /* PCI MSI level 1 */ -#define UIC_MSI2 0x00400000 /* PCI MSI level 2 */ -#define UIC_MTE 0x00200000 /* MAL TXEOB */ -#define UIC_MRE 0x00100000 /* MAL RXEOB */ -#define UIC_D0 0x00080000 /* DMA channel 0 */ -#define UIC_D1 0x00040000 /* DMA channel 1 */ -#define UIC_D2 0x00020000 /* DMA channel 2 */ -#define UIC_D3 0x00010000 /* DMA channel 3 */ -#define UIC_RSVD0 0x00008000 /* Reserved */ -#define UIC_RSVD1 0x00004000 /* Reserved */ -#define UIC_CT0 0x00002000 /* GPT compare timer 0 */ -#define UIC_CT1 0x00001000 /* GPT compare timer 1 */ -#define UIC_CT2 0x00000800 /* GPT compare timer 2 */ -#define UIC_CT3 0x00000400 /* GPT compare timer 3 */ -#define UIC_CT4 0x00000200 /* GPT compare timer 4 */ -#define UIC_EIR0 0x00000100 /* External interrupt 0 */ -#define UIC_EIR1 0x00000080 /* External interrupt 1 */ -#define UIC_EIR2 0x00000040 /* External interrupt 2 */ -#define UIC_EIR3 0x00000020 /* External interrupt 3 */ -#define UIC_EIR4 0x00000010 /* External interrupt 4 */ -#define UIC_EIR5 0x00000008 /* External interrupt 5 */ -#define UIC_EIR6 0x00000004 /* External interrupt 6 */ -#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ -#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ -#endif /* CONFIG_440GX */ - -/* For compatibility with 405 code */ -#define UIC_MAL_TXEOB UIC_MTE -#define UIC_MAL_RXEOB UIC_MRE - -/*---------------------------------------------------------------------------+ -| Universal interrupt controller 1 interrupts (UIC1) -+---------------------------------------------------------------------------*/ -#if defined(CONFIG_440SP) -#define UIC_EIR0 0x80000000 /* External interrupt 0 */ -#define UIC_MS 0x40000000 /* MAL SERR */ -#define UIC_MTDE 0x20000000 /* MAL TXDE */ -#define UIC_MRDE 0x10000000 /* MAL RXDE */ -#define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */ -#define UIC_EBCO 0x04000000 /* EBCO interrupt status */ -#define UIC_MTE 0x02000000 /* MAL TXEOB */ -#define UIC_MRE 0x01000000 /* MAL RXEOB */ -#define UIC_P0MSI1 0x00800000 /* PCI0 MSI level 1 */ -#define UIC_P1MSI1 0x00400000 /* PCI1 MSI level 1 */ -#define UIC_P2MSI1 0x00200000 /* PCI2 MSI level 1 */ -#define UIC_L2C 0x00100000 /* L2 cache */ -#define UIC_CT0 0x00080000 /* GPT compare timer 0 */ -#define UIC_CT1 0x00040000 /* GPT compare timer 1 */ -#define UIC_CT2 0x00020000 /* GPT compare timer 2 */ -#define UIC_CT3 0x00010000 /* GPT compare timer 3 */ -#define UIC_CT4 0x00008000 /* GPT compare timer 4 */ -#define UIC_EIR1 0x00004000 /* External interrupt 1 */ -#define UIC_EIR2 0x00002000 /* External interrupt 2 */ -#define UIC_EIR3 0x00001000 /* External interrupt 3 */ -#define UIC_EIR4 0x00000800 /* External interrupt 4 */ -#define UIC_EIR5 0x00000400 /* External interrupt 5 */ -#define UIC_DMAE 0x00000200 /* DMA error */ -#define UIC_I2OE 0x00000100 /* I2O error */ -#define UIC_SRE 0x00000080 /* Serial ROM error */ -#define UIC_P0AE 0x00000040 /* PCI0 asynchronous error */ -#define UIC_P1AE 0x00000020 /* PCI1 asynchronous error */ -#define UIC_P2AE 0x00000010 /* PCI2 asynchronous error */ -#define UIC_ETH0 0x00000008 /* Ethernet 0 */ -#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ -#define UIC_ETH1 0x00000002 /* Reserved */ -#define UIC_XOR 0x00000001 /* XOR */ -#elif defined(CONFIG_440GX) || defined(CONFIG_440EP) -#define UIC_MS 0x80000000 /* MAL SERR */ -#define UIC_MTDE 0x40000000 /* MAL TXDE */ -#define UIC_MRDE 0x20000000 /* MAL RXDE */ -#define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/ -#define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */ -#define UIC_EBCO 0x04000000 /* EBCO interrupt status */ -#define UIC_EBMI 0x02000000 /* EBMI interrupt status */ -#define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */ -#define UIC_MSI3 0x00800000 /* PCI MSI level 3 */ -#define UIC_MSI4 0x00400000 /* PCI MSI level 4 */ -#define UIC_MSI5 0x00200000 /* PCI MSI level 5 */ -#define UIC_MSI6 0x00100000 /* PCI MSI level 6 */ -#define UIC_MSI7 0x00080000 /* PCI MSI level 7 */ -#define UIC_MSI8 0x00040000 /* PCI MSI level 8 */ -#define UIC_MSI9 0x00020000 /* PCI MSI level 9 */ -#define UIC_MSI10 0x00010000 /* PCI MSI level 10 */ -#define UIC_MSI11 0x00008000 /* PCI MSI level 11 */ -#define UIC_PPMI 0x00004000 /* PPM interrupt status */ -#define UIC_EIR7 0x00002000 /* External interrupt 7 */ -#define UIC_EIR8 0x00001000 /* External interrupt 8 */ -#define UIC_EIR9 0x00000800 /* External interrupt 9 */ -#define UIC_EIR10 0x00000400 /* External interrupt 10 */ -#define UIC_EIR11 0x00000200 /* External interrupt 11 */ -#define UIC_EIR12 0x00000100 /* External interrupt 12 */ -#define UIC_SRE 0x00000080 /* Serial ROM error */ -#define UIC_RSVD2 0x00000040 /* Reserved */ -#define UIC_RSVD3 0x00000020 /* Reserved */ -#define UIC_PAE 0x00000010 /* PCI asynchronous error */ -#define UIC_ETH0 0x00000008 /* Ethernet 0 */ -#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ -#define UIC_ETH1 0x00000002 /* Ethernet 1 */ -#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */ - -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) - -#define UIC_EIR2 0x80000000 /* External interrupt 2 */ -#define UIC_U0 0x40000000 /* UART 0 */ -#define UIC_SPI 0x20000000 /* SPI */ -#define UIC_TRNGAL 0x10000000 /* TRNG alarm */ -#define UIC_DEUE 0x08000000 /* DDR SDRAM ECC correct/uncorrectable error */ -#define UIC_EBCO 0x04000000 /* EBCO interrupt status */ -#define UIC_NDFC 0x02000000 /* NDFC */ -#define UIC_EIPPKPSE 0x01000000 /* EIPPKP slave error */ -#define UIC_P0MSI1 0x00800000 /* PCI0 MSI level 1 */ -#define UIC_P0MSI2 0x00400000 /* PCI0 MSI level 2 */ -#define UIC_P0MSI3 0x00200000 /* PCI0 MSI level 3 */ -#define UIC_L2C 0x00100000 /* L2 cache */ -#define UIC_CT0 0x00080000 /* GPT compare timer 0 */ -#define UIC_CT1 0x00040000 /* GPT compare timer 1 */ -#define UIC_CT2 0x00020000 /* GPT compare timer 2 */ -#define UIC_CT3 0x00010000 /* GPT compare timer 3 */ -#define UIC_CT4 0x00008000 /* GPT compare timer 4 */ -#define UIC_CT5 0x00004000 /* GPT compare timer 5 */ -#define UIC_CT6 0x00002000 /* GPT compare timer 6 */ -#define UIC_GPTDC 0x00001000 /* GPT decrementer pulse */ -#define UIC_EIR3 0x00000800 /* External interrupt 3 */ -#define UIC_EIR4 0x00000400 /* External interrupt 4 */ -#define UIC_DMAE 0x00000200 /* DMA error */ -#define UIC_I2OE 0x00000100 /* I2O error */ -#define UIC_SRE 0x00000080 /* Serial ROM error */ -#define UIC_P0AE 0x00000040 /* PCI0 asynchronous error */ -#define UIC_EIR5 0x00000020 /* External interrupt 5 */ -#define UIC_EIR6 0x00000010 /* External interrupt 6 */ -#define UIC_U2 0x00000008 /* UART 2 */ -#define UIC_U3 0x00000004 /* UART 3 */ -#define UIC_EIR7 0x00000002 /* External interrupt 7 */ -#define UIC_EIR8 0x00000001 /* External interrupt 8 */ - -#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) - -#define UIC_MS 0x80000000 /* MAL SERR */ -#define UIC_MTDE 0x40000000 /* MAL TXDE */ -#define UIC_MRDE 0x20000000 /* MAL RXDE */ -#define UIC_U2 0x10000000 /* UART 2 */ -#define UIC_U3 0x08000000 /* UART 3 */ -#define UIC_EBCO 0x04000000 /* EBCO interrupt status */ -#define UIC_NDFC 0x02000000 /* NDFC */ -#define UIC_KSLE 0x01000000 /* KASUMI slave error */ -#define UIC_CT5 0x00800000 /* GPT compare timer 5 */ -#define UIC_CT6 0x00400000 /* GPT compare timer 6 */ -#define UIC_PLB34I0 0x00200000 /* PLB3X4X MIRQ0 */ -#define UIC_PLB34I1 0x00100000 /* PLB3X4X MIRQ1 */ -#define UIC_PLB34I2 0x00080000 /* PLB3X4X MIRQ2 */ -#define UIC_PLB34I3 0x00040000 /* PLB3X4X MIRQ3 */ -#define UIC_PLB34I4 0x00020000 /* PLB3X4X MIRQ4 */ -#define UIC_PLB34I5 0x00010000 /* PLB3X4X MIRQ5 */ -#define UIC_CT0 0x00008000 /* GPT compare timer 0 */ -#define UIC_CT1 0x00004000 /* GPT compare timer 1 */ -#define UIC_EIR7 0x00002000 /* External interrupt 7 */ -#define UIC_EIR8 0x00001000 /* External interrupt 8 */ -#define UIC_EIR9 0x00000800 /* External interrupt 9 */ -#define UIC_CT2 0x00000400 /* GPT compare timer 2 */ -#define UIC_CT3 0x00000200 /* GPT compare timer 3 */ -#define UIC_CT4 0x00000100 /* GPT compare timer 4 */ -#define UIC_SRE 0x00000080 /* Serial ROM error */ -#define UIC_GPTDC 0x00000040 /* GPT decrementer pulse */ -#define UIC_RSVD0 0x00000020 /* Reserved */ -#define UIC_EPCIPER 0x00000010 /* External PCI PERR */ -#define UIC_EIR0 0x00000008 /* External interrupt 0 */ -#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ -#define UIC_EIR1 0x00000002 /* External interrupt 1 */ -#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */ - -/* For compatibility with 405 code */ -#define UIC_MAL_SERR UIC_MS -#define UIC_MAL_TXDE UIC_MTDE -#define UIC_MAL_RXDE UIC_MRDE -#define UIC_ENET UIC_ETH0 - -#elif !defined(CONFIG_440SPE) -#define UIC_MS 0x80000000 /* MAL SERR */ -#define UIC_MTDE 0x40000000 /* MAL TXDE */ -#define UIC_MRDE 0x20000000 /* MAL RXDE */ -#define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/ -#define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */ -#define UIC_EBCO 0x04000000 /* EBCO interrupt status */ -#define UIC_EBMI 0x02000000 /* EBMI interrupt status */ -#define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */ -#define UIC_MSI3 0x00800000 /* PCI MSI level 3 */ -#define UIC_MSI4 0x00400000 /* PCI MSI level 4 */ -#define UIC_MSI5 0x00200000 /* PCI MSI level 5 */ -#define UIC_MSI6 0x00100000 /* PCI MSI level 6 */ -#define UIC_MSI7 0x00080000 /* PCI MSI level 7 */ -#define UIC_MSI8 0x00040000 /* PCI MSI level 8 */ -#define UIC_MSI9 0x00020000 /* PCI MSI level 9 */ -#define UIC_MSI10 0x00010000 /* PCI MSI level 10 */ -#define UIC_MSI11 0x00008000 /* PCI MSI level 11 */ -#define UIC_PPMI 0x00004000 /* PPM interrupt status */ -#define UIC_EIR7 0x00002000 /* External interrupt 7 */ -#define UIC_EIR8 0x00001000 /* External interrupt 8 */ -#define UIC_EIR9 0x00000800 /* External interrupt 9 */ -#define UIC_EIR10 0x00000400 /* External interrupt 10 */ -#define UIC_EIR11 0x00000200 /* External interrupt 11 */ -#define UIC_EIR12 0x00000100 /* External interrupt 12 */ -#define UIC_SRE 0x00000080 /* Serial ROM error */ -#define UIC_RSVD2 0x00000040 /* Reserved */ -#define UIC_RSVD3 0x00000020 /* Reserved */ -#define UIC_PAE 0x00000010 /* PCI asynchronous error */ -#define UIC_ETH0 0x00000008 /* Ethernet 0 */ -#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ -#define UIC_ETH1 0x00000002 /* Ethernet 1 */ -#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */ -#endif /* CONFIG_440SP */ - -/* For compatibility with 405 code */ -#define UIC_MAL_SERR UIC_MS -#define UIC_MAL_TXDE UIC_MTDE -#define UIC_MAL_RXDE UIC_MRDE -#define UIC_ENET UIC_ETH0 - -/*---------------------------------------------------------------------------+ -| Universal interrupt controller 2 interrupts (UIC2) -+---------------------------------------------------------------------------*/ -#if defined(CONFIG_440GX) -#define UIC_ETH2 0x80000000 /* Ethernet 2 */ -#define UIC_EWU2 0x40000000 /* Ethernet 2 wakeup */ -#define UIC_ETH3 0x20000000 /* Ethernet 3 */ -#define UIC_EWU3 0x10000000 /* Ethernet 3 wakeup */ -#define UIC_TAH0 0x08000000 /* TAH 0 */ -#define UIC_TAH1 0x04000000 /* TAH 1 */ -#define UIC_IMUOBFQ 0x02000000 /* IMU outbound free queue */ -#define UIC_IMUIBPQ 0x01000000 /* IMU inbound post queue */ -#define UIC_IMUIRQDB 0x00800000 /* IMU irq doorbell */ -#define UIC_IMUIBDB 0x00400000 /* IMU inbound doorbell */ -#define UIC_IMUMSG0 0x00200000 /* IMU inbound message 0 */ -#define UIC_IMUMSG1 0x00100000 /* IMU inbound message 1 */ -#define UIC_IMUTO 0x00080000 /* IMU timeout */ -#define UIC_MSI12 0x00040000 /* PCI MSI level 12 */ -#define UIC_MSI13 0x00020000 /* PCI MSI level 13 */ -#define UIC_MSI14 0x00010000 /* PCI MSI level 14 */ -#define UIC_MSI15 0x00008000 /* PCI MSI level 15 */ -#define UIC_EIR13 0x00004000 /* External interrupt 13 */ -#define UIC_EIR14 0x00002000 /* External interrupt 14 */ -#define UIC_EIR15 0x00001000 /* External interrupt 15 */ -#define UIC_EIR16 0x00000800 /* External interrupt 16 */ -#define UIC_EIR17 0x00000400 /* External interrupt 17 */ -#define UIC_PCIVPD 0x00000200 /* PCI VPD */ -#define UIC_L2C 0x00000100 /* L2 Cache */ -#define UIC_ETH2PCS 0x00000080 /* Ethernet 2 PCS */ -#define UIC_ETH3PCS 0x00000040 /* Ethernet 3 PCS */ -#define UIC_RSVD26 0x00000020 /* Reserved */ -#define UIC_RSVD27 0x00000010 /* Reserved */ -#define UIC_RSVD28 0x00000008 /* Reserved */ -#define UIC_RSVD29 0x00000004 /* Reserved */ -#define UIC_RSVD30 0x00000002 /* Reserved */ -#define UIC_RSVD31 0x00000001 /* Reserved */ - -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) - -#define UIC_TAH0 0x80000000 /* TAHOE 0 */ -#define UIC_TAH1 0x40000000 /* TAHOE 1 */ -#define UIC_EIR9 0x20000000 /* External interrupt 9 */ -#define UIC_MS 0x10000000 /* MAL SERR */ -#define UIC_MTDE 0x08000000 /* MAL TXDE */ -#define UIC_MRDE 0x04000000 /* MAL RXDE */ -#define UIC_MTE 0x02000000 /* MAL TXEOB */ -#define UIC_MRE 0x01000000 /* MAL RXEOB */ -#define UIC_MCTX0 0x00800000 /* MAL interrupt coalescence TX0 */ -#define UIC_MCTX1 0x00400000 /* MAL interrupt coalescence TX1 */ -#define UIC_MCTX2 0x00200000 /* MAL interrupt coalescence TX2 */ -#define UIC_MCTX3 0x00100000 /* MAL interrupt coalescence TX3 */ -#define UIC_MCTR0 0x00080000 /* MAL interrupt coalescence TR0 */ -#define UIC_MCTR1 0x00040000 /* MAL interrupt coalescence TR1 */ -#define UIC_MCTR2 0x00020000 /* MAL interrupt coalescence TR2 */ -#define UIC_MCTR3 0x00010000 /* MAL interrupt coalescence TR3 */ -#define UIC_ETH0 0x00008000 /* Ethernet 0 */ -#define UIC_ETH1 0x00004000 /* Ethernet 1 */ -#define UIC_ETH2 0x00002000 /* Ethernet 2 */ -#define UIC_ETH3 0x00001000 /* Ethernet 3 */ -#define UIC_EWU0 0x00000800 /* Ethernet 0 wakeup */ -#define UIC_EWU1 0x00000400 /* Ethernet 1 wakeup */ -#define UIC_EWU2 0x00000200 /* Ethernet 2 wakeup */ -#define UIC_EWU3 0x00000100 /* Ethernet 3 wakeup */ -#define UIC_EIR10 0x00000080 /* External interrupt 10 */ -#define UIC_EIR11 0x00000040 /* External interrupt 11 */ -#define UIC_RSVD2 0x00000020 /* Reserved */ -#define UIC_PLB4XAHB 0x00000010 /* PLB4XAHB / AHBARB error */ -#define UIC_OTG 0x00000008 /* USB2.0 OTG */ -#define UIC_EHCI 0x00000004 /* USB2.0 Host EHCI */ -#define UIC_OHCI 0x00000002 /* USB2.0 Host OHCI */ -#define UIC_OHCISMI 0x00000001 /* USB2.0 Host OHCI SMI */ - -#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* UIC2 */ - -#define UIC_EIR5 0x80000000 /* External interrupt 5 */ -#define UIC_EIR6 0x40000000 /* External interrupt 6 */ -#define UIC_OPB 0x20000000 /* OPB to PLB bridge interrupt stat */ -#define UIC_EIR2 0x10000000 /* External interrupt 2 */ -#define UIC_EIR3 0x08000000 /* External interrupt 3 */ -#define UIC_DDR2 0x04000000 /* DDR2 sdram */ -#define UIC_MCTX0 0x02000000 /* MAl intp coalescence TX0 */ -#define UIC_MCTX1 0x01000000 /* MAl intp coalescence TX1 */ -#define UIC_MCTR0 0x00800000 /* MAl intp coalescence TR0 */ -#define UIC_MCTR1 0x00400000 /* MAl intp coalescence TR1 */ - -#endif /* CONFIG_440GX */ - -/*---------------------------------------------------------------------------+ -| Universal interrupt controller Base 0 interrupts (UICB0) -+---------------------------------------------------------------------------*/ -#if defined(CONFIG_440GX) -#define UICB0_UIC0CI 0x80000000 /* UIC0 Critical Interrupt */ -#define UICB0_UIC0NCI 0x40000000 /* UIC0 Noncritical Interrupt */ -#define UICB0_UIC1CI 0x20000000 /* UIC1 Critical Interrupt */ -#define UICB0_UIC1NCI 0x10000000 /* UIC1 Noncritical Interrupt */ -#define UICB0_UIC2CI 0x08000000 /* UIC2 Critical Interrupt */ -#define UICB0_UIC2NCI 0x04000000 /* UIC2 Noncritical Interrupt */ - -#define UICB0_ALL (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \ - UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI) - -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) - -#define UICB0_UIC1NCI 0x00000002 /* UIC1 Noncritical Interrupt */ -#define UICB0_UIC1CI 0x00000001 /* UIC1 Critical Interrupt */ -#define UICB0_UIC2NCI 0x00200000 /* UIC2 Noncritical Interrupt */ -#define UICB0_UIC2CI 0x00100000 /* UIC2 Critical Interrupt */ -#define UICB0_UIC3NCI 0x00008000 /* UIC3 Noncritical Interrupt */ -#define UICB0_UIC3CI 0x00004000 /* UIC3 Critical Interrupt */ - -#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | UICB0_UIC2CI | \ - UICB0_UIC2NCI | UICB0_UIC3CI | UICB0_UIC3NCI) - -#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) - -#define UICB0_UIC1CI 0x00000001 /* UIC1 Critical Interrupt */ -#define UICB0_UIC1NCI 0x00000002 /* UIC1 Noncritical Interrupt */ -#define UICB0_UIC2CI 0x00000004 /* UIC2 Critical Interrupt */ -#define UICB0_UIC2NCI 0x00000008 /* UIC2 Noncritical Interrupt */ - -#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | \ - UICB0_UIC1CI | UICB0_UIC2NCI) - -#elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \ - defined(CONFIG_440EP) || defined(CONFIG_440GR) - -#define UICB0_UIC1CI 0x00000001 /* UIC1 Critical Interrupt */ -#define UICB0_UIC1NCI 0x00000002 /* UIC1 Noncritical Interrupt */ - -#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI) - -#endif /* CONFIG_440GX */ -/*---------------------------------------------------------------------------+ -| Universal interrupt controller interrupts -+---------------------------------------------------------------------------*/ -#if defined(CONFIG_440SPE) -/*#define UICB0_UIC0CI 0x80000000*/ /* UIC0 Critical Interrupt */ -/*#define UICB0_UIC0NCI 0x40000000*/ /* UIC0 Noncritical Interrupt */ -#define UICB0_UIC1CI 0x00000002 /* UIC1 Critical Interrupt */ -#define UICB0_UIC1NCI 0x00000001 /* UIC1 Noncritical Interrupt */ -#define UICB0_UIC2CI 0x00200000 /* UIC2 Critical Interrupt */ -#define UICB0_UIC2NCI 0x00100000 /* UIC2 Noncritical Interrupt */ -#define UICB0_UIC3CI 0x00008000 /* UIC3 Critical Interrupt */ -#define UICB0_UIC3NCI 0x00004000 /* UIC3 Noncritical Interrupt */ - -#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | UICB0_UIC2CI | \ - UICB0_UIC2NCI | UICB0_UIC3CI | UICB0_UIC3NCI) -/*---------------------------------------------------------------------------+ -| Universal interrupt controller 0 interrupts (UIC0) -+---------------------------------------------------------------------------*/ -#define UIC_U0 0x80000000 /* UART 0 */ -#define UIC_U1 0x40000000 /* UART 1 */ -#define UIC_IIC0 0x20000000 /* IIC */ -#define UIC_IIC1 0x10000000 /* IIC */ -#define UIC_PIM 0x08000000 /* PCI inbound message */ -#define UIC_PCRW 0x04000000 /* PCI command register write */ -#define UIC_PPM 0x02000000 /* PCI power management */ -#define UIC_PVPDA 0x01000000 /* PCIx 0 vpd access */ -#define UIC_MSI0 0x00800000 /* PCIx MSI level 0 */ -#define UIC_EIR15 0x00400000 /* External intp 15 */ -#define UIC_PEMSI0 0x00080000 /* PCIe MSI level 0 */ -#define UIC_PEMSI1 0x00040000 /* PCIe MSI level 1 */ -#define UIC_PEMSI2 0x00020000 /* PCIe MSI level 2 */ -#define UIC_PEMSI3 0x00010000 /* PCIe MSI level 3 */ -#define UIC_EIR14 0x00002000 /* External interrupt 14 */ -#define UIC_D0CPFF 0x00001000 /* DMA0 cp fifo full */ -#define UIC_D0CSNS 0x00000800 /* DMA0 cs fifo needs service */ -#define UIC_D1CPFF 0x00000400 /* DMA1 cp fifo full */ -#define UIC_D1CSNS 0x00000200 /* DMA1 cs fifo needs service */ -#define UIC_I2OID 0x00000100 /* I2O inbound door bell */ -#define UIC_I2OLNE 0x00000080 /* I2O Inbound Post List FIFO Not Empty */ -#define UIC_I20R0LL 0x00000040 /* I2O Region 0 Low Latency PLB Write */ -#define UIC_I2OR1LL 0x00000020 /* I2O Region 1 Low Latency PLB Write */ -#define UIC_I20R0HB 0x00000010 /* I2O Region 0 High Bandwidth PLB Write */ -#define UIC_I2OR1HB 0x00000008 /* I2O Region 1 High Bandwidth PLB Write */ -#define UIC_CPTCNT 0x00000004 /* GPT Count Timer */ -/*---------------------------------------------------------------------------+ -| Universal interrupt controller 1 interrupts (UIC1) -+---------------------------------------------------------------------------*/ -#define UIC_EIR13 0x80000000 /* externei intp 13 */ -#define UIC_MS 0x40000000 /* MAL SERR */ -#define UIC_MTDE 0x20000000 /* MAL TXDE */ -#define UIC_MRDE 0x10000000 /* MAL RXDE */ -#define UIC_DEUE 0x08000000 /* DDR SDRAM ECC correct/uncorrectable error */ -#define UIC_EBCO 0x04000000 /* EBCO interrupt status */ -#define UIC_MTE 0x02000000 /* MAL TXEOB */ -#define UIC_MRE 0x01000000 /* MAL RXEOB */ -#define UIC_MSI1 0x00800000 /* PCI MSI level 1 */ -#define UIC_MSI2 0x00400000 /* PCI MSI level 2 */ -#define UIC_MSI3 0x00200000 /* PCI MSI level 3 */ -#define UIC_L2C 0x00100000 /* L2 cache */ -#define UIC_CT0 0x00080000 /* GPT compare timer 0 */ -#define UIC_CT1 0x00040000 /* GPT compare timer 1 */ -#define UIC_CT2 0x00020000 /* GPT compare timer 2 */ -#define UIC_CT3 0x00010000 /* GPT compare timer 3 */ -#define UIC_CT4 0x00008000 /* GPT compare timer 4 */ -#define UIC_EIR12 0x00004000 /* External interrupt 12 */ -#define UIC_EIR11 0x00002000 /* External interrupt 11 */ -#define UIC_EIR10 0x00001000 /* External interrupt 10 */ -#define UIC_EIR9 0x00000800 /* External interrupt 9 */ -#define UIC_EIR8 0x00000400 /* External interrupt 8 */ -#define UIC_DMAE 0x00000200 /* dma error */ -#define UIC_I2OE 0x00000100 /* i2o error */ -#define UIC_SRE 0x00000080 /* Serial ROM error */ -#define UIC_PCIXAE 0x00000040 /* Pcix0 async error */ -#define UIC_EIR7 0x00000020 /* External interrupt 7 */ -#define UIC_EIR6 0x00000010 /* External interrupt 6 */ -#define UIC_ETH0 0x00000008 /* Ethernet 0 */ -#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ -#define UIC_ETH1 0x00000002 /* reserved */ -#define UIC_XOR 0x00000001 /* xor */ - -/*---------------------------------------------------------------------------+ -| Universal interrupt controller 2 interrupts (UIC2) -+---------------------------------------------------------------------------*/ -#define UIC_PEOAL 0x80000000 /* PE0 AL */ -#define UIC_PEOVA 0x40000000 /* PE0 VPD access */ -#define UIC_PEOHRR 0x20000000 /* PE0 Host reset request rising */ -#define UIC_PE0HRF 0x10000000 /* PE0 Host reset request falling */ -#define UIC_PE0TCR 0x08000000 /* PE0 TCR */ -#define UIC_PE0BVCO 0x04000000 /* PE0 Busmaster VCO */ -#define UIC_PE0DCRE 0x02000000 /* PE0 DCR error */ -#define UIC_PE1AL 0x00800000 /* PE1 AL */ -#define UIC_PE1VA 0x00400000 /* PE1 VPD access */ -#define UIC_PE1HRR 0x00200000 /* PE1 Host reset request rising */ -#define UIC_PE1HRF 0x00100000 /* PE1 Host reset request falling */ -#define UIC_PE1TCR 0x00080000 /* PE1 TCR */ -#define UIC_PE1BVCO 0x00040000 /* PE1 Busmaster VCO */ -#define UIC_PE1DCRE 0x00020000 /* PE1 DCR error */ -#define UIC_PE2AL 0x00008000 /* PE2 AL */ -#define UIC_PE2VA 0x00004000 /* PE2 VPD access */ -#define UIC_PE2HRR 0x00002000 /* PE2 Host reset request rising */ -#define UIC_PE2HRF 0x00001000 /* PE2 Host reset request falling */ -#define UIC_PE2TCR 0x00000800 /* PE2 TCR */ -#define UIC_PE2BVCO 0x00000400 /* PE2 Busmaster VCO */ -#define UIC_PE2DCRE 0x00000200 /* PE2 DCR error */ -#define UIC_EIR5 0x00000080 /* External interrupt 5 */ -#define UIC_EIR4 0x00000040 /* External interrupt 4 */ -#define UIC_EIR3 0x00000020 /* External interrupt 3 */ -#define UIC_EIR2 0x00000010 /* External interrupt 2 */ -#define UIC_EIR1 0x00000008 /* External interrupt 1 */ -#define UIC_EIR0 0x00000004 /* External interrupt 0 */ -#endif /* CONFIG_440SPE */ - -/*-----------------------------------------------------------------------------+ -| External Bus Controller Bit Settings -+-----------------------------------------------------------------------------*/ -#define EBC_CFGADDR_MASK 0x0000003F - -#define EBC_BXCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0) -#define EBC_BXCR_BS_MASK 0x000E0000 -#define EBC_BXCR_BS_1MB 0x00000000 -#define EBC_BXCR_BS_2MB 0x00020000 -#define EBC_BXCR_BS_4MB 0x00040000 -#define EBC_BXCR_BS_8MB 0x00060000 -#define EBC_BXCR_BS_16MB 0x00080000 -#define EBC_BXCR_BS_32MB 0x000A0000 -#define EBC_BXCR_BS_64MB 0x000C0000 -#define EBC_BXCR_BS_128MB 0x000E0000 -#define EBC_BXCR_BU_MASK 0x00018000 -#define EBC_BXCR_BU_R 0x00008000 -#define EBC_BXCR_BU_W 0x00010000 -#define EBC_BXCR_BU_RW 0x00018000 -#define EBC_BXCR_BW_MASK 0x00006000 -#define EBC_BXCR_BW_8BIT 0x00000000 -#define EBC_BXCR_BW_16BIT 0x00002000 -#define EBC_BXCR_BW_32BIT 0x00006000 -#define EBC_BXAP_BME_ENABLED 0x80000000 -#define EBC_BXAP_BME_DISABLED 0x00000000 -#define EBC_BXAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23) -#define EBC_BXAP_BCE_DISABLE 0x00000000 -#define EBC_BXAP_BCE_ENABLE 0x00400000 -#define EBC_BXAP_BCT_MASK 0x00300000 -#define EBC_BXAP_BCT_2TRANS 0x00000000 -#define EBC_BXAP_BCT_4TRANS 0x00100000 -#define EBC_BXAP_BCT_8TRANS 0x00200000 -#define EBC_BXAP_BCT_16TRANS 0x00300000 -#define EBC_BXAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18) -#define EBC_BXAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) -#define EBC_BXAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14) -#define EBC_BXAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12) -#define EBC_BXAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9) -#define EBC_BXAP_RE_ENABLED 0x00000100 -#define EBC_BXAP_RE_DISABLED 0x00000000 -#define EBC_BXAP_SOR_DELAYED 0x00000000 -#define EBC_BXAP_SOR_NONDELAYED 0x00000080 -#define EBC_BXAP_BEM_WRITEONLY 0x00000000 -#define EBC_BXAP_BEM_RW 0x00000040 -#define EBC_BXAP_PEN_DISABLED 0x00000000 - -#define EBC_CFG_LE_MASK 0x80000000 -#define EBC_CFG_LE_UNLOCK 0x00000000 -#define EBC_CFG_LE_LOCK 0x80000000 -#define EBC_CFG_PTD_MASK 0x40000000 -#define EBC_CFG_PTD_ENABLE 0x00000000 -#define EBC_CFG_PTD_DISABLE 0x40000000 -#define EBC_CFG_RTC_MASK 0x38000000 -#define EBC_CFG_RTC_16PERCLK 0x00000000 -#define EBC_CFG_RTC_32PERCLK 0x08000000 -#define EBC_CFG_RTC_64PERCLK 0x10000000 -#define EBC_CFG_RTC_128PERCLK 0x18000000 -#define EBC_CFG_RTC_256PERCLK 0x20000000 -#define EBC_CFG_RTC_512PERCLK 0x28000000 -#define EBC_CFG_RTC_1024PERCLK 0x30000000 -#define EBC_CFG_RTC_2048PERCLK 0x38000000 -#define EBC_CFG_ATC_MASK 0x04000000 -#define EBC_CFG_ATC_HI 0x00000000 -#define EBC_CFG_ATC_PREVIOUS 0x04000000 -#define EBC_CFG_DTC_MASK 0x02000000 -#define EBC_CFG_DTC_HI 0x00000000 -#define EBC_CFG_DTC_PREVIOUS 0x02000000 -#define EBC_CFG_CTC_MASK 0x01000000 -#define EBC_CFG_CTC_HI 0x00000000 -#define EBC_CFG_CTC_PREVIOUS 0x01000000 -#define EBC_CFG_OEO_MASK 0x00800000 -#define EBC_CFG_OEO_HI 0x00000000 -#define EBC_CFG_OEO_PREVIOUS 0x00800000 -#define EBC_CFG_EMC_MASK 0x00400000 -#define EBC_CFG_EMC_NONDEFAULT 0x00000000 -#define EBC_CFG_EMC_DEFAULT 0x00400000 -#define EBC_CFG_PME_MASK 0x00200000 -#define EBC_CFG_PME_DISABLE 0x00000000 -#define EBC_CFG_PME_ENABLE 0x00200000 -#define EBC_CFG_PMT_MASK 0x001F0000 -#define EBC_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12) -#define EBC_CFG_PR_MASK 0x0000C000 -#define EBC_CFG_PR_16 0x00000000 -#define EBC_CFG_PR_32 0x00004000 -#define EBC_CFG_PR_64 0x00008000 -#define EBC_CFG_PR_128 0x0000C000 - /*-----------------------------------------------------------------------------+ | SDR0 Bit Settings +-----------------------------------------------------------------------------*/ @@ -1855,7 +887,7 @@ #define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF) #endif -#if defined(CONFIG_440SPE) +#if defined(CONFIG_440SPE) || defined(CONFIG_460SX) #define SDR0_CP440 0x0180 #define SDR0_CP440_ERPN_MASK 0x30000000 #define SDR0_CP440_ERPN_MASK_HI 0x3000 @@ -2793,7 +1825,8 @@ /*-----------------------------------------------------------------------------+ | Clocking +-----------------------------------------------------------------------------*/ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) #define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */ #define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */ #define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */ @@ -2873,118 +1906,10 @@ #endif /* CONFIG_440GX */ #if defined (CONFIG_440EPX) || defined (CONFIG_440GRX) -/*--------------------------------------*/ -#define CPR0_PLLC 0x40 -#define CPR0_PLLC_RST_MASK 0x80000000 -#define CPR0_PLLC_RST_PLLLOCKED 0x00000000 -#define CPR0_PLLC_RST_PLLRESET 0x80000000 -#define CPR0_PLLC_ENG_MASK 0x40000000 -#define CPR0_PLLC_ENG_DISABLE 0x00000000 -#define CPR0_PLLC_ENG_ENABLE 0x40000000 -#define CPR0_PLLC_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) -#define CPR0_PLLC_ENG_DECODE(n) ((((unsigned long)(n))>>30)&0x01) -#define CPR0_PLLC_SRC_MASK 0x20000000 -#define CPR0_PLLC_SRC_PLLOUTA 0x00000000 -#define CPR0_PLLC_SRC_PLLOUTB 0x20000000 -#define CPR0_PLLC_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<29) -#define CPR0_PLLC_SRC_DECODE(n) ((((unsigned long)(n))>>29)&0x01) -#define CPR0_PLLC_SEL_MASK 0x07000000 -#define CPR0_PLLC_SEL_PLL 0x00000000 -#define CPR0_PLLC_SEL_CPU 0x01000000 -#define CPR0_PLLC_SEL_PER 0x05000000 -#define CPR0_PLLC_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) -#define CPR0_PLLC_SEL_DECODE(n) ((((unsigned long)(n))>>24)&0x07) -#define CPR0_PLLC_TUNE_MASK 0x000003FF -#define CPR0_PLLC_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) -#define CPR0_PLLC_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF) -/*--------------------------------------*/ -#define CPR0_PLLD 0x60 -#define CPR0_PLLD_FBDV_MASK 0x1F000000 -#define CPR0_PLLD_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) -#define CPR0_PLLD_FBDV_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x1F)+1) -#define CPR0_PLLD_FWDVA_MASK 0x000F0000 -#define CPR0_PLLD_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<16) -#define CPR0_PLLD_FWDVA_DECODE(n) ((((((unsigned long)(n))>>16)-1)&0x0F)+1) -#define CPR0_PLLD_FWDVB_MASK 0x00000700 -#define CPR0_PLLD_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<8) -#define CPR0_PLLD_FWDVB_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x07)+1) -#define CPR0_PLLD_LFBDV_MASK 0x0000003F -#define CPR0_PLLD_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0) -#define CPR0_PLLD_LFBDV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1) -/*--------------------------------------*/ -#define CPR0_PRIMAD 0x80 -#define CPR0_PRIMAD_PRADV0_MASK 0x07000000 -#define CPR0_PRIMAD_PRADV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) -#define CPR0_PRIMAD_PRADV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1) -/*--------------------------------------*/ -#define CPR0_PRIMBD 0xA0 -#define CPR0_PRIMBD_PRBDV0_MASK 0x07000000 -#define CPR0_PRIMBD_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) -#define CPR0_PRIMBD_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1) -/*--------------------------------------*/ -#if 0 -#define CPR0_CPM0_ER 0xB0 /* CPM Enable Register */ -#define CPR0_CPM0_FR 0xB1 /* CPM Force Register */ -#define CPR0_CPM0_SR 0xB2 /* CPM Status Register */ -#define CPR0_CPM0_IIC0 0x80000000 /* Inter-Intergrated Circuit0 */ -#define CPR0_CPM0_IIC1 0x40000000 /* Inter-Intergrated Circuit1 */ -#define CPR0_CPM0_PCI 0x20000000 /* Peripheral Component Interconnect */ -#define CPR0_CPM0_USB1H 0x08000000 /* USB1.1 Host */ -#define CPR0_CPM0_FPU 0x04000000 /* PPC440 FPU */ -#define CPR0_CPM0_CPU 0x02000000 /* PPC440x5 Processor Core */ -#define CPR0_CPM0_DMA 0x01000000 /* Direct Memory Access Controller */ -#define CPR0_CPM0_BGO 0x00800000 /* PLB to OPB Bridge */ -#define CPR0_CPM0_BGI 0x00400000 /* OPB to PLB Bridge */ -#define CPR0_CPM0_EBC 0x00200000 /* External Bus Controller */ -#define CPR0_CPM0_NDFC 0x00100000 /* Nand Flash Controller */ -#define CPR0_CPM0_MADMAL 0x00080000 /* DDR SDRAM Controller or MADMAL ??? */ -#define CPR0_CPM0_DMC 0x00080000 /* DDR SDRAM Controller or MADMAL ??? */ -#define CPR0_CPM0_PLB4 0x00040000 /* PLB4 Arbiter */ -#define CPR0_CPM0_PLB4x3x 0x00020000 /* PLB4 to PLB3 */ -#define CPR0_CPM0_PLB3x4x 0x00010000 /* PLB3 to PLB4 */ -#define CPR0_CPM0_PLB3 0x00008000 /* PLB3 Arbiter */ -#define CPR0_CPM0_PPM 0x00002000 /* PLB Performance Monitor */ -#define CPR0_CPM0_UIC1 0x00001000 /* Universal Interrupt Controller 1 */ -#define CPR0_CPM0_GPIO 0x00000800 /* General Purpose IO */ -#define CPR0_CPM0_GPT 0x00000400 /* General Purpose Timer */ -#define CPR0_CPM0_UART0 0x00000200 /* Universal Asynchronous Rcver/Xmitter 0 */ -#define CPR0_CPM0_UART1 0x00000100 /* Universal Asynchronous Rcver/Xmitter 1 */ -#define CPR0_CPM0_UIC0 0x00000080 /* Universal Interrupt Controller 0 */ -#define CPR0_CPM0_TMRCLK 0x00000040 /* CPU Timer */ -#define CPR0_CPM0_EMC0 0x00000020 /* Ethernet 0 */ -#define CPR0_CPM0_EMC1 0x00000010 /* Ethernet 1 */ -#define CPR0_CPM0_UART2 0x00000008 /* Universal Asynchronous Rcver/Xmitter 2 */ -#define CPR0_CPM0_UART3 0x00000004 /* Universal Asynchronous Rcver/Xmitter 3 */ -#define CPR0_CPM0_USB2D 0x00000002 /* USB2.0 Device */ -#define CPR0_CPM0_USB2H 0x00000001 /* USB2.0 Host */ +#define CPR0_ICFG_RLI_MASK 0x80000000 +#define CPR0_SPCID_SPCIDV0_MASK 0x03000000 +#define CPR0_PERD_PERDV0_MASK 0x07000000 #endif -/*--------------------------------------*/ -#define CPR0_OPBD 0xC0 -#define CPR0_OPBD_OPBDV0_MASK 0x03000000 -#define CPR0_OPBD_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) -#define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) -/*--------------------------------------*/ -#define CPR0_PERD 0xE0 -#define CPR0_PERD_PERDV0_MASK 0x07000000 -#define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) -#define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1) -/*--------------------------------------*/ -#define CPR0_MALD 0x100 -#define CPR0_MALD_MALDV0_MASK 0x03000000 -#define CPR0_MALD_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) -#define CPR0_MALD_MALDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) -/*--------------------------------------*/ -#define CPR0_SPCID 0x120 -#define CPR0_SPCID_SPCIDV0_MASK 0x03000000 -#define CPR0_SPCID_SPCIDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) -#define CPR0_SPCID_SPCIDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) -/*--------------------------------------*/ -#define CPR0_ICFG 0x140 -#define CPR0_ICFG_RLI_MASK 0x80000000 -#define CPR0_ICFG_RLI_RESETCPR 0x00000000 -#define CPR0_ICFG_RLI_PRESERVECPR 0x80000000 -#define CPR0_ICFG_ICS_MASK 0x00000007 -#endif /* defined (CONFIG_440EPX) || defined (CONFIG_440GRX) */ /*----------------------------------------------------------------------------- | IIC Register Offsets @@ -3006,20 +1931,6 @@ #define IICDIRECTCNTL 0x10 /*----------------------------------------------------------------------------- -| UART Register Offsets -'----------------------------------------------------------------------------*/ -#define DATA_REG 0x00 -#define DL_LSB 0x00 -#define DL_MSB 0x01 -#define INT_ENABLE 0x01 -#define FIFO_CONTROL 0x02 -#define LINE_CONTROL 0x03 -#define MODEM_CONTROL 0x04 -#define LINE_STATUS 0x05 -#define MODEM_STATUS 0x06 -#define SCRATCH 0x07 - -/*----------------------------------------------------------------------------- | PCI Internal Registers et. al. (accessed via plb) +----------------------------------------------------------------------------*/ #define PCIX0_CFGADR (CFG_PCI_BASE + 0x0ec00000) @@ -3145,7 +2056,8 @@ * GPIO macro register defines ******************************************************************************/ #if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460SX) #define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000700) #define GPIO0_OR (GPIO0_BASE+0x0) diff --git a/include/ppc4xx.h b/include/ppc4xx.h index 1d06da8..c71da60 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -41,7 +41,8 @@ #if defined(CONFIG_405EX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) #define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ #endif @@ -58,6 +59,10 @@ #endif #include <asm/ppc4xx-sdram.h> +#include <asm/ppc4xx-ebc.h> +#if !defined(CONFIG_XILINX_440) +#include <asm/ppc4xx-uic.h> +#endif /* * Macro for generating register field mnemonics diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h index 4c97b36..b74c6fc 100644 --- a/include/ppc4xx_enet.h +++ b/include/ppc4xx_enet.h @@ -153,6 +153,20 @@ typedef struct emac_4xx_hw_st { #define SDR0_PFC1_EM_1000 (0x00200000) #endif +/* + * XMII bridge configurations for those systems (e.g. 405EX(r)) that do + * not have a pin function control (PFC) register to otherwise determine + * the bridge configuration. + */ +#define EMAC_PHY_MODE_NONE 0 +#define EMAC_PHY_MODE_NONE_RGMII 1 +#define EMAC_PHY_MODE_RGMII_NONE 2 +#define EMAC_PHY_MODE_RGMII_RGMII 3 +#define EMAC_PHY_MODE_NONE_GMII 4 +#define EMAC_PHY_MODE_GMII_NONE 5 +#define EMAC_PHY_MODE_NONE_MII 6 +#define EMAC_PHY_MODE_MII_NONE 7 + /* ZMII Bridge Register addresses */ #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ @@ -218,12 +232,12 @@ typedef struct emac_4xx_hw_st { #endif /* RGMII Function Enable (FER) Register Bit Definitions */ -/* Note: for EMAC 2 and 3 only, 440GX only */ #define RGMII_FER_DIS (0x00) #define RGMII_FER_RTBI (0x04) #define RGMII_FER_RGMII (0x05) #define RGMII_FER_TBI (0x06) #define RGMII_FER_GMII (0x07) +#define RGMII_FER_MII (RGMII_FER_GMII) #define RGMII_FER_V(__x) ((__x - 2) * 4) diff --git a/include/usb.h b/include/usb.h index 5a6ffdd..e68e98e 100644 --- a/include/usb.h +++ b/include/usb.h @@ -171,7 +171,7 @@ struct usb_device { #if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || \ defined(CONFIG_USB_OHCI_NEW) || defined (CONFIG_USB_SL811HS) || \ - defined(CONFIG_USB_ISP116X_HCD) + defined(CONFIG_USB_ISP116X_HCD) || defined(CONFIG_USB_R8A66597_HCD) int usb_lowlevel_init(void); int usb_lowlevel_stop(void); |