mpc83xx: Update 83xx to use fsl_i2c.c

Update the 83xx tree to use I2C support in drivers/fsl_i2c.c.  Delete
cpu/mpc83xx/i2c.c, include/asm-ppc/i2c.h, and all references to those files.
Added multiple I2C bus support to fsl_i2c.c.

Signed-off-by: Timur Tabi <timur@freescale.com>

6 files changed, 39 insertions, 119 deletions

diff --git a/include/asm-ppc/i2c.h b/include/asm-ppc/i2c.h
deleted file mode 100644
index 3784766..0000000
--- a/include/asm-ppc/i2c.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Freescale I2C Controller
- *
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * Copyright 2004 Freescale Semiconductor.
- * (C) Copyright 2003, Motorola, Inc.
- * author: Eran Liberty (liberty@freescale.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _ASM_I2C_H_
-#define _ASM_I2C_H_
-
-#include <asm/types.h>
-
-typedef struct i2c
-{
-    u8 adr;          /**< I2C slave address              */
-#define I2C_ADR	      0xFE
-#define I2C_ADR_SHIFT 1
-#define I2C_ADR_RES   ~(I2C_ADR)
-    u8 res0[3];
-    u8 fdr;          /**< I2C frequency divider register */
-#define IC2_FDR       0x3F
-#define IC2_FDR_SHIFT 0
-#define IC2_FDR_RES   ~(IC2_FDR)
-    u8 res1[3];
-    u8 cr;           /**< I2C control redister           */
-#define I2C_CR_MEN	  0x80
-#define I2C_CR_MIEN	  0x40
-#define I2C_CR_MSTA   0x20
-#define I2C_CR_MTX    0x10
-#define I2C_CR_TXAK   0x08
-#define I2C_CR_RSTA   0x04
-#define I2C_CR_BCST   0x01
-    u8 res2[3];
-    u8 sr;           /**< I2C status register            */
-#define I2C_SR_MCF    0x80
-#define I2C_SR_MAAS   0x40
-#define I2C_SR_MBB    0x20
-#define I2C_SR_MAL    0x10
-#define I2C_SR_BCSTM  0x08
-#define I2C_SR_SRW    0x04
-#define I2C_SR_MIF    0x02
-#define I2C_SR_RXAK   0x01
-    u8 res3[3];
-    u8 dr;           /**< I2C data register              */
-#define I2C_DR 0xFF
-#define I2C_DR_SHIFT 0
-#define I2C_DR_RES ~(I2C_DR)
-    u8 res4[3];
-    u8 dfsrr;        /**< I2C digital filter sampling rate register */
-#define I2C_DFSRR 0x3F
-#define I2C_DFSRR_SHIFT 0
-#define I2C_DFSRR_RES ~(I2C_DR)
-    u8 res5[3];
-    u8 res6[0xE8];
-} i2c_t;
-
-#ifndef CFG_HZ
-#error CFG_HZ is not defined in /include/configs/${BOARD}.h
-#endif
-#define I2C_TIMEOUT (CFG_HZ/4)
-
-#ifndef CFG_IMMR
-#error CFG_IMMR is not defined in /include/configs/${BOARD}.h
-#endif
-
-#ifndef CFG_I2C_OFFSET
-#error CFG_I2C_OFFSET is not defined in /include/configs/${BOARD}.h
-#endif
-
-#define I2C_1 ((i2c_t*)(CFG_IMMR + CFG_I2C_OFFSET))
-
-/* Optional support for second I2C bus */
-#ifdef	CFG_I2C2_OFFSET
-#define I2C_2 ((i2c_t*)(CFG_IMMR + CFG_I2C2_OFFSET))
-#endif	/* CFG_I2C2_OFFSET */
-
-#define I2C_READ  1
-#define I2C_WRITE 0
-
-#endif	/* _ASM_I2C_H_ */
diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h
index 09e08ba..2a76a05 100644
--- a/include/asm-ppc/immap_83xx.h
+++ b/include/asm-ppc/immap_83xx.h
@@ -39,7 +39,7 @@
 
 #include <config.h>
 #include <asm/types.h>
-#include <asm/i2c.h>
+#include <asm/fsl_i2c.h>
 
 /*
  * Local Access Window.
@@ -2007,7 +2007,7 @@ typedef struct immap {
 	qesba83xx_t qesba;	/* QE Secondary Bus Access Windows */
 #endif
 	ddr83xx_t ddr;		/* DDR Memory Controller Memory */
-	i2c_t i2c[2];		/* I2C1 Controller */
+	fsl_i2c_t i2c[2];	/* I2C Controllers */
 	u8 res2[0x1300];
 	duart83xx_t duart[2];	/* DUART */
 #if defined (CONFIG_MPC8349)
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 4a5b4bc..5bed2d0 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -335,6 +335,7 @@
 /* I2C */
 #define CONFIG_HARD_I2C			/* I2C with hardware support*/
 #undef CONFIG_SOFT_I2C			/* I2C bit-banged */
+#define CONFIG_FSL_I2C
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_I2C_CMD_TREE
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index c74e63a..8dc9635 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -41,14 +41,14 @@
  						Align.	Board
  Bus	Addr    Part No.	Description	Length	Location
  ----------------------------------------------------------------
- I2C1	0x50    M24256-BWMN6P	Board EEPROM	2       U64
+ I2C0	0x50    M24256-BWMN6P	Board EEPROM	2       U64
 
- I2C2	0x20    PCF8574		I2C Expander	0	U8
- I2C2	0x21    PCF8574		I2C Expander	0       U10
- I2C2	0x38    PCF8574A	I2C Expander    0	U8
- I2C2	0x39    PCF8574A	I2C Expander	0	U10
- I2C2	0x51    (DDR)		DDR EEPROM	1	U1
- I2C2	0x68    DS1339		RTC		1	U68
+ I2C1	0x20    PCF8574		I2C Expander	0	U8
+ I2C1	0x21    PCF8574		I2C Expander	0       U10
+ I2C1	0x38    PCF8574A	I2C Expander    0	U8
+ I2C1	0x39    PCF8574A	I2C Expander	0	U10
+ I2C1	0x51    (DDR)		DDR EEPROM	1	U1
+ I2C1	0x68    DS1339		RTC		1	U68
 
  Note that a given board has *either* a pair of 8574s or a pair of 8574As.
 */
@@ -77,19 +77,20 @@
 #define CONFIG_MISC_INIT_F
 #define CONFIG_MISC_INIT_R
 
+#define CONFIG_FSL_I2C
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_I2C_CMD_TREE
 #define CFG_I2C_OFFSET      	0x3000
 #define CFG_I2C2_OFFSET      	0x3100
-#define CFG_SPD_BUS_NUM		2
+#define CFG_SPD_BUS_NUM		1	/* The I2C bus for SPD */
 
-#define CFG_I2C_8574_ADDR1	0x20	/* I2C2, PCF8574 */
-#define CFG_I2C_8574_ADDR2	0x21	/* I2C2, PCF8574 */
-#define CFG_I2C_8574A_ADDR1	0x38	/* I2C2, PCF8574A */
-#define CFG_I2C_8574A_ADDR2	0x39	/* I2C2, PCF8574A */
-#define CFG_I2C_EEPROM_ADDR	0x50    /* I2C1, Board EEPROM */
-#define CFG_I2C_RTC_ADDR	0x68	/* I2C2, DS1339 RTC*/
-#define SPD_EEPROM_ADDRESS	0x51	/* I2C2, DDR */
+#define CFG_I2C_8574_ADDR1	0x20	/* I2C1, PCF8574 */
+#define CFG_I2C_8574_ADDR2	0x21	/* I2C1, PCF8574 */
+#define CFG_I2C_8574A_ADDR1	0x38	/* I2C1, PCF8574A */
+#define CFG_I2C_8574A_ADDR2	0x39	/* I2C1, PCF8574A */
+#define CFG_I2C_EEPROM_ADDR	0x50    /* I2C0, Board EEPROM */
+#define CFG_I2C_RTC_ADDR	0x68	/* I2C1, DS1339 RTC*/
+#define SPD_EEPROM_ADDRESS	0x51	/* I2C1, DDR */
 
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CFG_I2C_SLAVE		0x7F
@@ -175,6 +176,7 @@
 #define CFG_FLASH_CFI_DRIVER			/* use the CFI driver */
 #define CFG_FLASH_BASE		0xFE000000	/* start of FLASH   */
 #define CFG_FLASH_SIZE		16		/* FLASH size in MB */
+#define CFG_FLASH_EMPTY_INFO
 
 #define CFG_BR0_PRELIM		(CFG_FLASH_BASE | BR_PS_16 | BR_V)
 #define CFG_OR0_PRELIM		((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
@@ -610,7 +612,7 @@
 #define CFG_SPCR_TSEC1EP	3	/* TSEC1 emergency priority (0-3) */
 #define CFG_SPCR_TSEC2EP	3	/* TSEC2 emergency priority (0-3) */
 #define CFG_SCCR_TSEC1CM	1	/* TSEC1 clock mode (0-3) */
-#define CFG_SCCR_TSEC2CM	1	/* TSEC2 & I2C1 clock mode (0-3) */
+#define CFG_SCCR_TSEC2CM	1	/* TSEC2 & I2C0 clock mode (0-3) */
 #define CFG_ACR_RPTCNT		3	/* Arbiter repeat count */
 
 /* System IO Config */
@@ -708,6 +710,19 @@
 #define CONFIG_ETH1ADDR		00:E0:0C:00:8C:02
 #endif
 
+#if 1
+#define CONFIG_IPADDR		10.82.19.159
+#define CONFIG_SERVERIP		10.82.48.106
+#define CONFIG_GATEWAYIP	10.82.19.254
+#define CONFIG_NETMASK		255.255.252.0
+#define CONFIG_NETDEV		eth0
+
+#define CONFIG_HOSTNAME		mpc8349emitx
+#define CONFIG_ROOTPATH		/nfsroot0/u/timur/itx-ltib/rootfs
+#define CONFIG_BOOTFILE		timur/uImage
+
+#define CONFIG_UBOOTPATH	timur/u-boot.bin
+#else
 #define CONFIG_IPADDR		192.168.1.253
 #define CONFIG_SERVERIP		192.168.1.1
 #define CONFIG_GATEWAYIP	192.168.1.1
@@ -719,6 +734,8 @@
 #define CONFIG_BOOTFILE		uImage
 
 #define CONFIG_UBOOTPATH	u-boot.bin
+#endif
+
 #define CONFIG_UBOOTSTART	fe700000
 #define CONFIG_UBOOTEND		fe77ffff
 
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index a8f2df9..2ff5f48 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -330,7 +330,8 @@
 /* I2C */
 #define CONFIG_HARD_I2C		/* I2C with hardware support */
 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
-#define CFG_I2C_SPEED	0x3F	/* I2C speed and slave address */
+#define CONFIG_FSL_I2C
+#define CFG_I2C_SPEED	400000	/* I2C speed and slave address */
 #define CFG_I2C_SLAVE	0x7F
 #define CFG_I2C_NOPROBES	{0x52} /* Don't probe these addrs */
 #define CFG_I2C_OFFSET	0x3000
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index b0b0673..728083b 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -218,6 +218,7 @@ extern int tqm834x_num_flash_banks;
  */
 #define CONFIG_HARD_I2C				/* I2C with hardware support	*/
 #undef CONFIG_SOFT_I2C				/* I2C bit-banged		*/
+#define CONFIG_FSL_I2C
 #define CFG_I2C_SPEED			400000	/* I2C speed: 400KHz		*/
 #define CFG_I2C_SLAVE			0x7F	/* slave address		*/
 #define CFG_I2C_OFFSET			0x3000