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| author | Trent Piepho <tpiepho@freescale.com> | 2008-12-03 15:16:34 -0800 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2008-12-19 18:20:25 -0600 |
| commit | a5d212a263c58cc746481bf1fc878510533ce7d6 (patch) | |
| tree | eb08c782227ec1399e96eb6dc082db2123262e41 /include | |
| parent | 58ec4866ed916c7e422f5107bb27b0822084728e (diff) | |
| download | u-boot-imx-a5d212a263c58cc746481bf1fc878510533ce7d6.zip u-boot-imx-a5d212a263c58cc746481bf1fc878510533ce7d6.tar.gz u-boot-imx-a5d212a263c58cc746481bf1fc878510533ce7d6.tar.bz2 | |
mpc8xxx: LCRR[CLKDIV] is sometimes five bits
On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits
instead of four.
In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It
should be safe as the fifth bit was defined as reserved and set to 0.
Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-ppc/fsl_lbc.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h index 51fc5c1..e492c62 100644 --- a/include/asm-ppc/fsl_lbc.h +++ b/include/asm-ppc/fsl_lbc.h @@ -300,7 +300,10 @@ #define LCRR_EADC_2 0x00020000 #define LCRR_EADC_3 0x00030000 #define LCRR_EADC_4 0x00000000 -#define LCRR_CLKDIV 0x0000000F +/* CLKDIV is five bits only on 8536, 8572, and 8610, so far, but the fifth bit + * should always be zero on older parts that have a four bit CLKDIV. + */ +#define LCRR_CLKDIV 0x0000001F #define LCRR_CLKDIV_SHIFT 0 #define LCRR_CLKDIV_2 0x00000002 #define LCRR_CLKDIV_4 0x00000004 |